target/riscv: rvv: Allow fractional LMUL on vector SHA instructions

[PATCH] target/riscv: rvv: Allow fractional LMUL on vector SHA instructions

Anton Blanchard posted 1 patch 1 month ago

Download mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260104233724.192886-1-antonb@tenstorrent.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/insn_trans/trans_rvvk.c.inc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)

Expand all Fold all

[PATCH] target/riscv: rvv: Allow fractional LMUL on vector SHA instructions

Posted by Anton Blanchard 1 month ago

Vector SHA instructions incorrectly raise an illegal instruction exception
when LMUL < 1. The ISA only states that LMUL*VLEN >= EGW:

  For element-group instructions, LMUL*VLEN must always be at least as
  large as EGW, otherwise an illegal-instruction exception is raised, even
  if vl=0.

There is already a check for this:

  MAXSZ(s) >= egw_bytes

so just remove the check for a fractional LMUL.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
 target/riscv/insn_trans/trans_rvvk.c.inc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index 27bf3f0b68..32255d3aa0 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -426,8 +426,7 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a)
            vsha_check_sew(s) &&
            MAXSZ(s) >= egw_bytes &&
            !is_overlapped(a->rd, mult, a->rs1, mult) &&
-           !is_overlapped(a->rd, mult, a->rs2, mult) &&
-           s->lmul >= 0;
+           !is_overlapped(a->rd, mult, a->rs2, mult);
 }
 
 GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS)
-- 
2.34.1

Re: [PATCH] target/riscv: rvv: Allow fractional LMUL on vector SHA instructions

Posted by Daniel Henrique Barboza 1 month ago


On 1/4/26 8:37 PM, Anton Blanchard wrote:
> Vector SHA instructions incorrectly raise an illegal instruction exception
> when LMUL < 1. The ISA only states that LMUL*VLEN >= EGW:
> 
>    For element-group instructions, LMUL*VLEN must always be at least as
>    large as EGW, otherwise an illegal-instruction exception is raised, even
>    if vl=0.
> 
> There is already a check for this:
> 
>    MAXSZ(s) >= egw_bytes
> 
> so just remove the check for a fractional LMUL.
> 
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/insn_trans/trans_rvvk.c.inc | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
> index 27bf3f0b68..32255d3aa0 100644
> --- a/target/riscv/insn_trans/trans_rvvk.c.inc
> +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
> @@ -426,8 +426,7 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a)
>              vsha_check_sew(s) &&
>              MAXSZ(s) >= egw_bytes &&
>              !is_overlapped(a->rd, mult, a->rs1, mult) &&
> -           !is_overlapped(a->rd, mult, a->rs2, mult) &&
> -           s->lmul >= 0;
> +           !is_overlapped(a->rd, mult, a->rs2, mult);
>   }
>   
>   GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS)