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Sun, 04 Jan 2026 15:39:51 -0800 (PST) From: Anton Blanchard To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Anton Blanchard , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH] target/riscv: rvv: Allow fractional LMUL on vector SHA instructions Date: Sun, 4 Jan 2026 23:37:24 +0000 Message-Id: <20260104233724.192886-1-antonb@tenstorrent.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=antonb@tenstorrent.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1767570042494154100 Content-Type: text/plain; charset="utf-8" Vector SHA instructions incorrectly raise an illegal instruction exception when LMUL < 1. The ISA only states that LMUL*VLEN >=3D EGW: For element-group instructions, LMUL*VLEN must always be at least as large as EGW, otherwise an illegal-instruction exception is raised, even if vl=3D0. There is already a check for this: MAXSZ(s) >=3D egw_bytes so just remove the check for a fractional LMUL. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvvk.c.inc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 27bf3f0b68..32255d3aa0 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -426,8 +426,7 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a) vsha_check_sew(s) && MAXSZ(s) >=3D egw_bytes && !is_overlapped(a->rd, mult, a->rs1, mult) && - !is_overlapped(a->rd, mult, a->rs2, mult) && - s->lmul >=3D 0; + !is_overlapped(a->rd, mult, a->rs2, mult); } =20 GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS) --=20 2.34.1