[PATCH v2 0/9] i386/cpu: Support APX for KVM

Zhao Liu posted 9 patches 2 days, 8 hours ago
Failed in applying to current master (apply log)
configs/targets/x86_64-softmmu.mak |  2 +-
gdb-xml/i386-64bit-apx.xml         | 26 +++++++++++
include/migration/cpu.h            |  4 ++
target/i386/cpu-dump.c             | 30 +++++++++++--
target/i386/cpu.c                  | 68 ++++++++++++++++++++++++++++-
target/i386/cpu.h                  | 48 +++++++++++++++++++--
target/i386/gdbstub.c              | 69 +++++++++++++++++++++++++++++-
target/i386/machine.c              | 27 +++++++++++-
target/i386/monitor.c              | 16 +++++++
target/i386/xsave_helper.c         | 16 +++++++
10 files changed, 293 insertions(+), 13 deletions(-)
create mode 100644 gdb-xml/i386-64bit-apx.xml
[PATCH v2 0/9] i386/cpu: Support APX for KVM
Posted by Zhao Liu 2 days, 8 hours ago
Hi,

This series adds APX (Advanced Performance Extensions) support in QEMU
to enable APX in Guest based on KVM (RFC v1 [1]).

This series is based on CET v5:

https://lore.kernel.org/qemu-devel/20251211060801.3600039-1-zhao1.liu@intel.com/

And you can also find the code here:

https://gitlab.com/zhao.liu/qemu/-/commits/i386-all-for-dmr-v2.1-12-10-2025

Compared with v1 [2], v2 adds:
 * HMP support ("print" & "info registers").
 * gdbstub support.

Thanks for your review!


Overview
========

Intel Advanced Performance Extensions (Intel APX) expands the Intel 64
instruction set architecture with access to more registers (16
additional general-purpose registers (GPRs) R16–R31) and adds various
new features that improve general-purpose performance. The extensions
are designed to provide efficient performance gains across a variety of
workloads without significantly increasing silicon area or power
consumption of the core.

APX spec link (rev.07) is:
https://cdrdv2.intel.com/v1/dl/getContent/861610

At QEMU side, the enabling work mainly includes three parts:

1. save/restore/migrate the xstate of APX.
   * APX xstate is a user xstate, but it reuses MPX xstate area in
     un-compacted XSAVE buffer.
   * To address this, QEMU will reject both APX and MPX if their CPUID
     feature bits are set at the same (in Patch 1).

2. add related CPUIDs support in feature words.

3. debug support, including HMP & gdbstub.


Change Log
==========

Changes sicne v1:
 * Expend current GPR array (CPUX86State.regs) to 32 elements instead of
   a new array.
 * HMP support ("print" & "info registers").
 * gdbstub support.

[1]: KVM RFC: https://lore.kernel.org/kvm/20251110180131.28264-1-chang.seok.bae@intel.com/
[2]: QEMU APX v1: https://lore.kernel.org/qemu-devel/20251118065817.835017-1-zhao1.liu@intel.com/

Thanks and Best Regards,
Zhao
---
Zhao Liu (6):
  i386/machine: Use VMSTATE_UINTTL_SUB_ARRAY for vmstate of
    CPUX86State.regs
  i386/gdbstub: Add APX support for gdbstub
  i386/cpu-dump: Dump entended GPRs for APX supported guest
  i386/monitor: Support EGPRs in hmp_print
  i386/cpu: Support APX CPUIDs
  i386/cpu: Mark APX xstate as migratable

Zide Chen (3):
  i386/cpu: Add APX EGPRs into xsave area
  i386/cpu: Cache EGPRs in CPUX86State
  i386/cpu: Add APX migration support

 configs/targets/x86_64-softmmu.mak |  2 +-
 gdb-xml/i386-64bit-apx.xml         | 26 +++++++++++
 include/migration/cpu.h            |  4 ++
 target/i386/cpu-dump.c             | 30 +++++++++++--
 target/i386/cpu.c                  | 68 ++++++++++++++++++++++++++++-
 target/i386/cpu.h                  | 48 +++++++++++++++++++--
 target/i386/gdbstub.c              | 69 +++++++++++++++++++++++++++++-
 target/i386/machine.c              | 27 +++++++++++-
 target/i386/monitor.c              | 16 +++++++
 target/i386/xsave_helper.c         | 16 +++++++
 10 files changed, 293 insertions(+), 13 deletions(-)
 create mode 100644 gdb-xml/i386-64bit-apx.xml

-- 
2.34.1


Re: [PATCH v2 0/9] i386/cpu: Support APX for KVM
Posted by Paolo Bonzini 2 days, 7 hours ago
On 12/11/25 08:09, Zhao Liu wrote:
> Hi,
> 
> This series adds APX (Advanced Performance Extensions) support in QEMU
> to enable APX in Guest based on KVM (RFC v1 [1]).
> 
> This series is based on CET v5:
> 
> https://lore.kernel.org/qemu-devel/20251211060801.3600039-1-zhao1.liu@intel.com/
> 
> And you can also find the code here:
> 
> https://gitlab.com/zhao.liu/qemu/-/commits/i386-all-for-dmr-v2.1-12-10-2025
> 
> Compared with v1 [2], v2 adds:
>   * HMP support ("print" & "info registers").
>   * gdbstub support.
> 
> Thanks for your review!

Great, thanks!  Just one question, should the CPUID feature be "apx" or 
"apxf" (and therefore CPUID_7_1_EDX_APXF)?  I can fix that myself of course.

Thanks,

Paolo

> 
> Overview
> ========
> 
> Intel Advanced Performance Extensions (Intel APX) expands the Intel 64
> instruction set architecture with access to more registers (16
> additional general-purpose registers (GPRs) R16–R31) and adds various
> new features that improve general-purpose performance. The extensions
> are designed to provide efficient performance gains across a variety of
> workloads without significantly increasing silicon area or power
> consumption of the core.
> 
> APX spec link (rev.07) is:
> https://cdrdv2.intel.com/v1/dl/getContent/861610
> 
> At QEMU side, the enabling work mainly includes three parts:
> 
> 1. save/restore/migrate the xstate of APX.
>     * APX xstate is a user xstate, but it reuses MPX xstate area in
>       un-compacted XSAVE buffer.
>     * To address this, QEMU will reject both APX and MPX if their CPUID
>       feature bits are set at the same (in Patch 1).
> 
> 2. add related CPUIDs support in feature words.
> 
> 3. debug support, including HMP & gdbstub.
> 
> 
> Change Log
> ==========
> 
> Changes sicne v1:
>   * Expend current GPR array (CPUX86State.regs) to 32 elements instead of
>     a new array.
>   * HMP support ("print" & "info registers").
>   * gdbstub support.
> 
> [1]: KVM RFC: https://lore.kernel.org/kvm/20251110180131.28264-1-chang.seok.bae@intel.com/
> [2]: QEMU APX v1: https://lore.kernel.org/qemu-devel/20251118065817.835017-1-zhao1.liu@intel.com/
> 
> Thanks and Best Regards,
> Zhao
> ---
> Zhao Liu (6):
>    i386/machine: Use VMSTATE_UINTTL_SUB_ARRAY for vmstate of
>      CPUX86State.regs
>    i386/gdbstub: Add APX support for gdbstub
>    i386/cpu-dump: Dump entended GPRs for APX supported guest
>    i386/monitor: Support EGPRs in hmp_print
>    i386/cpu: Support APX CPUIDs
>    i386/cpu: Mark APX xstate as migratable
> 
> Zide Chen (3):
>    i386/cpu: Add APX EGPRs into xsave area
>    i386/cpu: Cache EGPRs in CPUX86State
>    i386/cpu: Add APX migration support
> 
>   configs/targets/x86_64-softmmu.mak |  2 +-
>   gdb-xml/i386-64bit-apx.xml         | 26 +++++++++++
>   include/migration/cpu.h            |  4 ++
>   target/i386/cpu-dump.c             | 30 +++++++++++--
>   target/i386/cpu.c                  | 68 ++++++++++++++++++++++++++++-
>   target/i386/cpu.h                  | 48 +++++++++++++++++++--
>   target/i386/gdbstub.c              | 69 +++++++++++++++++++++++++++++-
>   target/i386/machine.c              | 27 +++++++++++-
>   target/i386/monitor.c              | 16 +++++++
>   target/i386/xsave_helper.c         | 16 +++++++
>   10 files changed, 293 insertions(+), 13 deletions(-)
>   create mode 100644 gdb-xml/i386-64bit-apx.xml
> 


Re: [PATCH v2 0/9] i386/cpu: Support APX for KVM
Posted by Zhao Liu 2 days, 6 hours ago
On Thu, Dec 11, 2025 at 09:08:33AM +0100, Paolo Bonzini wrote:
> Date: Thu, 11 Dec 2025 09:08:33 +0100
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: Re: [PATCH v2 0/9] i386/cpu: Support APX for KVM
> 
> On 12/11/25 08:09, Zhao Liu wrote:
> > Hi,
> > 
> > This series adds APX (Advanced Performance Extensions) support in QEMU
> > to enable APX in Guest based on KVM (RFC v1 [1]).
> > 
> > This series is based on CET v5:
> > 
> > https://lore.kernel.org/qemu-devel/20251211060801.3600039-1-zhao1.liu@intel.com/
> > 
> > And you can also find the code here:
> > 
> > https://gitlab.com/zhao.liu/qemu/-/commits/i386-all-for-dmr-v2.1-12-10-2025
> > 
> > Compared with v1 [2], v2 adds:
> >   * HMP support ("print" & "info registers").
> >   * gdbstub support.
> > 
> > Thanks for your review!
> 
> Great, thanks!  Just one question, should the CPUID feature be "apx" or
> "apxf" (and therefore CPUID_7_1_EDX_APXF)?  I can fix that myself of course.

Good point! I didn't realize this.

1) Per APX spec:

(APX adds) CPUID Enumeration for APX_F (APX Foundation).

2) And gcc also use apx_f:

https://codebrowser.dev/gcc/gcc/config/i386/cpuid.h.html#_M/bit_APX_F

3) ...and we already have "avx512f".

So you're right, I should use "apxf" and CPUID_7_1_EDX_APXF.

Since APX CPUID appears in several patches, I can respin a new version
quickly.

Thanks,
Zhao
Re: [PATCH v2 0/9] i386/cpu: Support APX for KVM
Posted by Paolo Bonzini 2 days, 5 hours ago
On 12/11/25 10:16, Zhao Liu wrote:
> On Thu, Dec 11, 2025 at 09:08:33AM +0100, Paolo Bonzini wrote:
>> Great, thanks!  Just one question, should the CPUID feature be "apx" or
>> "apxf" (and therefore CPUID_7_1_EDX_APXF)?  I can fix that myself of course.
> 
> Good point! I didn't realize this.
> 
> 1) Per APX spec:
> 
> (APX adds) CPUID Enumeration for APX_F (APX Foundation).
> 
> 2) And gcc also use apx_f:
> 
> https://codebrowser.dev/gcc/gcc/config/i386/cpuid.h.html#_M/bit_APX_F
> 
> 3) ...and we already have "avx512f".
> 
> So you're right, I should use "apxf" and CPUID_7_1_EDX_APXF.
> 
> Since APX CPUID appears in several patches, I can respin a new version
> quickly.

No problem, I have done a quick pass with "sed" on the patches and 
reapplied them.  I do ask you to respin the Diamond Rapids series 
though, on top of the for-upstream tag of 
https://gitlab.com/bonzini/qemu (currently going through CI).

Applied for 11.0!

Paolo
Re: [PATCH v2 0/9] i386/cpu: Support APX for KVM
Posted by Zhao Liu 2 days, 3 hours ago
> No problem, I have done a quick pass with "sed" on the patches and reapplied
> them.  I do ask you to respin the Diamond Rapids series though, on top of
> the for-upstream tag of https://gitlab.com/bonzini/qemu (currently going
> through CI).
> 
> Applied for 11.0!

Thank you!

BTW, could you please have a look at this clean up on outdated SPR
comments:

https://lore.kernel.org/qemu-devel/20251118080837.837505-1-zhao1.liu@intel.com/

I feel it's better to clear SPR comments before DMR touches AMX.

Thanks,
Zhao