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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 1/9] i386/cpu: Add APX EGPRs into xsave area Date: Thu, 11 Dec 2025 15:09:34 +0800 Message-Id: <20251211070942.3612547-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765435560218158500 Content-Type: text/plain; charset="utf-8" From: Zide Chen APX feature bit is in CPUID_7_1_EDX[21], and APX has EGPR component with index 19 in xstate area, EGPR component has 16 64bit regs. Add EGRP component into xstate area. Note, APX re-uses the 128-byte XSAVE area that had been previously allocated by MPX which has been deprecated on Intel processors, so check whether APX and MPX are set at the same for Guest, if this case happens, mask off them both to avoid conflict for xsave area. Tested-by: Xudong Hao Signed-off-by: Zide Chen Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- target/i386/cpu.c | 25 +++++++++++++++++++++++++ target/i386/cpu.h | 17 +++++++++++++++-- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 84adfaf99dc8..16bc4b18266c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2111,6 +2111,12 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUN= T] =3D { { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }, }, }, + [XSTATE_APX_BIT] =3D { + .size =3D sizeof(XSaveAPX), + .features =3D { + { FEAT_7_1_EDX, CPUID_7_1_EDX_APX }, + }, + }, }; =20 uint32_t xsave_area_size(uint64_t mask, bool compacted) @@ -9116,6 +9122,25 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) env->features[FEAT_KVM] =3D 0; } =20 + /* + * Since Intel MPX had been previously deprecated, APX re-purposes the + * 128-byte XSAVE area that had been previously allocated by MPX (state + * component indices 3 and 4, making up a 128-byte area located at an + * offset of 960 bytes into an un-compacted XSAVE buffer), as a single + * state component housing 128-bytes of storage for EGPRs (8-bytes * 16 + * registers). + * + * Check the conflict between MPX and APX before initializing xsave + * components. + */ + if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_MPX) && + (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX)) { + mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_MPX, + "this feature is conflict with APX"); + mark_unavailable_features(cpu, FEAT_7_1_EDX, CPUID_7_1_EDX_APX, + "this feature is conflict with MPX"); + } + x86_cpu_enable_xsave_components(cpu); =20 /* CPUID[EAX=3D7,ECX=3D0].EBX always increased level automatically: */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 33350602edd3..932982bd5dd6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -604,6 +604,7 @@ typedef enum X86Seg { #define XSTATE_ARCH_LBR_BIT 15 #define XSTATE_XTILE_CFG_BIT 17 #define XSTATE_XTILE_DATA_BIT 18 +#define XSTATE_APX_BIT 19 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -620,6 +621,7 @@ typedef enum X86Seg { #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT) #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) +#define XSTATE_APX_MASK (1ULL << XSTATE_APX_BIT) =20 #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK) =20 @@ -636,7 +638,8 @@ typedef enum X86Seg { XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |= \ XSTATE_ZMM_Hi256_MASK | \ XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK |= \ - XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA= _MASK) + XSTATE_XTILE_CFG_MASK | \ + XSTATE_XTILE_DATA_MASK | XSTATE_APX_MASK) =20 /* CPUID feature bits available in XSS */ #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK | XSTATE_CET_U_MASK = | \ @@ -1039,6 +1042,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) /* Support for Advanced Vector Extensions 10 */ #define CPUID_7_1_EDX_AVX10 (1U << 19) +/* Support for Advanced Performance Extensions */ +#define CPUID_7_1_EDX_APX (1U << 21) =20 /* Indicate bit 7 of the IA32_SPEC_CTRL MSR is supported */ #define CPUID_7_2_EDX_PSFD (1U << 0) @@ -1681,6 +1686,8 @@ typedef struct { =20 #define ARCH_LBR_NR_ENTRIES 32 =20 +#define EGPR_NUM 16 + /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish * that APIC ID hasn't been set yet */ @@ -1791,6 +1798,11 @@ typedef struct XSaveXTILEDATA { uint8_t xtiledata[8][1024]; } XSaveXTILEDATA; =20 +/* Ext. save area 19: APX state */ +typedef struct XSaveAPX { + uint64_t egprs[EGPR_NUM]; +} XSaveAPX; + QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40); @@ -1803,6 +1815,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveCETS) !=3D 0x18); QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) !=3D 0x328); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) !=3D 0x2000); +QEMU_BUILD_BUG_ON(sizeof(XSaveAPX) !=3D 0x80); =20 typedef struct ExtSaveArea { uint32_t offset, size; @@ -1817,7 +1830,7 @@ typedef struct ExtSaveArea { const FeatureMask features[2]; } ExtSaveArea; =20 -#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) +#define XSAVE_STATE_AREA_COUNT (XSTATE_APX_BIT + 1) =20 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; =20 --=20 2.34.1 From nobody Mon Feb 9 16:58:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1765435565; cv=none; d=zohomail.com; s=zohoarc; b=bU2+oV8f4/zpkn4/wPn4JQS2z99Y1Nd4ZD6LKF2zCkNHnel2yyszRZSIoMVxFfW++ae9EaC8FJ0ApQ2VRYavtdXVCOUK6QqLFNnRa3woAxVOPX+2WoZ76vVR72SxU+a4h9PWQCE2iRART8ahfAG5v8CHtnmRrRnwrQ2cR1btcFk= ARC-Message-Signature: i=1; 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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 2/9] i386/machine: Use VMSTATE_UINTTL_SUB_ARRAY for vmstate of CPUX86State.regs Date: Thu, 11 Dec 2025 15:09:35 +0800 Message-Id: <20251211070942.3612547-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765435566384158500 Content-Type: text/plain; charset="utf-8" Before expanding the number of elements in the CPUX86State.regs array, first use VMSTATE_UINTTL_SUB_ARRAY for the regs' vmstate to avoid the type_check_array failure. VMSTATE_UINTTL_SUB_ARRAY will also be used for subsequently added elements in regs array. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Changes since v1: * New patch. --- include/migration/cpu.h | 4 ++++ target/i386/machine.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/migration/cpu.h b/include/migration/cpu.h index ca7cc0479e79..1335abe22301 100644 --- a/include/migration/cpu.h +++ b/include/migration/cpu.h @@ -21,6 +21,8 @@ VMSTATE_UINT64_V(_f, _s, _v) #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) +#define VMSTATE_UINTTL_SUB_ARRAY(_f, _s, _start, _num) \ + VMSTATE_UINT64_SUB_ARRAY(_f, _s, _start, _num) #define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \ VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, _v) #define VMSTATE_UINTTL_TEST(_f, _s, _t) \ @@ -40,6 +42,8 @@ VMSTATE_UINT32_V(_f, _s, _v) #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) +#define VMSTATE_UINTTL_SUB_ARRAY(_f, _s, _start, _num) \ + VMSTATE_UINT32_SUB_ARRAY(_f, _s, _start, _num) #define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \ VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, _v) #define VMSTATE_UINTTL_TEST(_f, _s, _t) \ diff --git a/target/i386/machine.c b/target/i386/machine.c index 57a968c30db3..0882dc3eb09e 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1748,7 +1748,7 @@ const VMStateDescription vmstate_x86_cpu =3D { .pre_save =3D cpu_pre_save, .post_load =3D cpu_post_load, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS), + VMSTATE_UINTTL_SUB_ARRAY(env.regs, X86CPU, 0, CPU_NB_REGS), VMSTATE_UINTTL(env.eip, X86CPU), VMSTATE_UINTTL(env.eflags, X86CPU), VMSTATE_UINT32(env.hflags, X86CPU), --=20 2.34.1 From nobody Mon Feb 9 16:58:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="67584435" X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="67584435" X-CSE-ConnectionGUID: ZxeGGYAaRgWHAdhTim1vjw== X-CSE-MsgGUID: sqYc29jNS3GluWcNGbyJzw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="196494962" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Xu , Fabiano Rosas Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, "Chang S . Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 3/9] i386/cpu: Cache EGPRs in CPUX86State Date: Thu, 11 Dec 2025 15:09:36 +0800 Message-Id: <20251211070942.3612547-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765435606402158500 Content-Type: text/plain; charset="utf-8" From: Zide Chen Expend general registers array "regs" of CPUX86State to cache entended GPRs. Tested-by: Xudong Hao Signed-off-by: Zide Chen Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes since v1: * Extend "regs" array instead of a new array. --- target/i386/cpu.h | 7 +++++-- target/i386/xsave_helper.c | 16 ++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 932982bd5dd6..9bf5d0b41efe 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1664,12 +1664,15 @@ typedef struct { uint64_t mask; } MTRRVar; =20 +#define CPU_NB_EREGS64 32 #define CPU_NB_REGS64 16 #define CPU_NB_REGS32 8 =20 #ifdef TARGET_X86_64 +#define CPU_NB_EREGS CPU_NB_EREGS64 #define CPU_NB_REGS CPU_NB_REGS64 #else +#define CPU_NB_EREGS CPU_NB_REGS32 #define CPU_NB_REGS CPU_NB_REGS32 #endif =20 @@ -1901,7 +1904,7 @@ typedef struct CPUCaches { =20 typedef struct CPUArchState { /* standard registers */ - target_ulong regs[CPU_NB_REGS]; + target_ulong regs[CPU_NB_EREGS]; target_ulong eip; target_ulong eflags; /* eflags register. During CPU emulation, CC flags and DF are set to zero because they are @@ -1958,7 +1961,7 @@ typedef struct CPUArchState { float_status mmx_status; /* for 3DNow! float ops */ float_status sse_status; uint32_t mxcsr; - ZMMReg xmm_regs[CPU_NB_REGS =3D=3D 8 ? 8 : 32] QEMU_ALIGNED(16); + ZMMReg xmm_regs[CPU_NB_EREGS] QEMU_ALIGNED(16); ZMMReg xmm_t0 QEMU_ALIGNED(16); MMXReg mmx_t0; =20 diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index 996e9f3bfef5..bab22587320d 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -140,6 +140,14 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, u= int32_t buflen) =20 memcpy(tiledata, &env->xtiledata, sizeof(env->xtiledata)); } + + e =3D &x86_ext_save_areas[XSTATE_APX_BIT]; + if (e->size && e->offset && buflen) { + XSaveAPX *apx =3D buf + e->offset; + + memcpy(apx, &env->regs[CPU_NB_REGS], + sizeof(env->regs[CPU_NB_REGS]) * (CPU_NB_EREGS - CPU_NB_REG= S)); + } #endif } =20 @@ -275,5 +283,13 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void = *buf, uint32_t buflen) =20 memcpy(&env->xtiledata, tiledata, sizeof(env->xtiledata)); } + + e =3D &x86_ext_save_areas[XSTATE_APX_BIT]; + if (e->size && e->offset) { + const XSaveAPX *apx =3D buf + e->offset; + + memcpy(&env->regs[CPU_NB_REGS], apx, + sizeof(env->regs[CPU_NB_REGS]) * (CPU_NB_EREGS - CPU_NB_REG= S)); + } #endif } --=20 2.34.1 From nobody Mon Feb 9 16:58:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1765435590; cv=none; d=zohomail.com; s=zohoarc; b=j9tCoNJoA7uQ97OGj4HR6jinG+xFv4hX6ZlmAH9kGNAvmYjqQqQlFANqC+42p8eilzVjK1yrX7IrndQaJ+tobW49mDtHBnXFLuOffHPMJvJybU4K+k+OjZKe96k5+k9HLvEFHplXgG0UJpeK1NH0cMKEGPkvE5ghDMZCmiFS31c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765435590; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 4/9] i386/gdbstub: Add APX support for gdbstub Date: Thu, 11 Dec 2025 15:09:37 +0800 Message-Id: <20251211070942.3612547-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765435592260158502 Content-Type: text/plain; charset="utf-8" Add i386-64bit-apx.xml from gdb to allow QEMU gdbstub parse APX EGPRs, and implement the callbacks to allow gdbstub access EGPRs of guest. Suggested-by: Paolo Bonzini Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Changes since v1: * New patch. --- configs/targets/x86_64-softmmu.mak | 2 +- gdb-xml/i386-64bit-apx.xml | 26 +++++++++++ target/i386/cpu.h | 16 +++++++ target/i386/gdbstub.c | 69 +++++++++++++++++++++++++++++- 4 files changed, 110 insertions(+), 3 deletions(-) create mode 100644 gdb-xml/i386-64bit-apx.xml diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index 5619b2bc6865..5180560d4d61 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -2,5 +2,5 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy -TARGET_XML_FILES=3D gdb-xml/i386-64bit.xml +TARGET_XML_FILES=3D gdb-xml/i386-64bit.xml gdb-xml/i386-64bit-apx.xml TARGET_LONG_BITS=3D64 diff --git a/gdb-xml/i386-64bit-apx.xml b/gdb-xml/i386-64bit-apx.xml new file mode 100644 index 000000000000..11a4ec67cae4 --- /dev/null +++ b/gdb-xml/i386-64bit-apx.xml @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9bf5d0b41efe..edc18e4b3da8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -61,6 +61,22 @@ enum { R_R13 =3D 13, R_R14 =3D 14, R_R15 =3D 15, + R_R16 =3D 16, + R_R17 =3D 17, + R_R18 =3D 18, + R_R19 =3D 19, + R_R20 =3D 20, + R_R21 =3D 21, + R_R22 =3D 22, + R_R23 =3D 23, + R_R24 =3D 24, + R_R25 =3D 25, + R_R26 =3D 26, + R_R27 =3D 27, + R_R28 =3D 28, + R_R29 =3D 29, + R_R30 =3D 30, + R_R31 =3D 31, =20 R_AL =3D 0, R_CL =3D 1, diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 04c49e802d7d..91943f5ab941 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -27,9 +27,11 @@ #endif =20 #ifdef TARGET_X86_64 -static const int gpr_map[16] =3D { +static const int gpr_map[CPU_NB_EREGS] =3D { R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP, - 8, 9, 10, 11, 12, 13, 14, 15 + R_R8, R_R9, R_R10, R_R11, R_R12, R_R13, R_R14, R_R15, + R_R16, R_R17, R_R18, R_R19, R_R20, R_R21, R_R22, R_R23, + R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30, R_R31, }; #else #define gpr_map gpr_map32 @@ -444,8 +446,71 @@ static int x86_cpu_gdb_write_linux_register(CPUState *= cs, uint8_t *mem_buf, =20 #endif =20 +#ifdef TARGET_X86_64 +static int i386_cpu_gdb_get_egprs(CPUState *cs, GByteArray *mem_buf, int n) +{ + CPUX86State *env =3D &X86_CPU(cs)->env; + + if (n >=3D 0 && n < EGPR_NUM) { + /* EGPRs can be only directly accessible in 64-bit mode. */ + if (env->hflags & HF_CS64_MASK) { + return gdb_get_reg64(mem_buf, env->regs[gpr_map[n + CPU_NB_REG= S]]); + } else { + return gdb_get_regl(mem_buf, 0); + } + } + + return 0; +} + +static int i386_cpu_gdb_set_egprs(CPUState *cs, uint8_t *mem_buf, int n) +{ + CPUX86State *env =3D &X86_CPU(cs)->env; + + if (n >=3D 0 && n < EGPR_NUM) { + /* + * EGPRs can be only directly accessible in 64-bit mode, and requi= re + * XCR0[APX_F] (at least for modification in gdbstub) to be enable= d. + */ + if (env->hflags & HF_CS64_MASK && env->xcr0 & XSTATE_APX_MASK) { + env->regs[gpr_map[n + CPU_NB_REGS]] =3D ldtul_p(mem_buf); + + /* + * Per SDM Vol 1, "Processor Tracking of XSAVE-Managed State", + * XSTATE_BV[i] *may* be either 0 or 1 if the state component = is + * in its initial configuration. + * + * However, it is observed on Diamond Rapids (DMR) that + * XSTATE_BV[APX_F] is set whenever EGPRs are modified, regard= less + * of the value written (even if zero). + * + * Since GDB modifies the software register cache directly, + * manually force the bit set to emulate this behavior observed + * on hardware. + */ + if (!(env->xstate_bv & XSTATE_APX_MASK)) { + env->xstate_bv |=3D XSTATE_APX_MASK; + } + } + return sizeof(target_ulong); + } + return 0; +} +#endif + void x86_cpu_gdb_init(CPUState *cs) { +#ifdef TARGET_X86_64 + CPUX86State *env =3D &X86_CPU(cs)->env; + + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX) { + gdb_register_coprocessor(cs, i386_cpu_gdb_get_egprs, + i386_cpu_gdb_set_egprs, + gdb_find_static_feature("i386-64bit-apx.x= ml"), + 0); + } +#endif + #ifdef CONFIG_LINUX_USER gdb_register_coprocessor(cs, x86_cpu_gdb_read_linux_register, x86_cpu_gdb_write_linux_register, --=20 2.34.1 From nobody Mon Feb 9 16:58:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 5/9] i386/cpu-dump: Dump entended GPRs for APX supported guest Date: Thu, 11 Dec 2025 15:09:38 +0800 Message-Id: <20251211070942.3612547-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765435600539158500 Content-Type: text/plain; charset="utf-8" Dump EGPRs when guest supports APX. Suggested-by: Paolo Bonzini Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Changes since v1: * New patch. --- target/i386/cpu-dump.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c index 67bf31e0caaf..b51076f87115 100644 --- a/target/i386/cpu-dump.c +++ b/target/i386/cpu-dump.c @@ -354,8 +354,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flag= s) qemu_fprintf(f, "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%= 016" PRIx64 " RDX=3D%016" PRIx64 "\n" "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016= " PRIx64 " RSP=3D%016" PRIx64 "\n" "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016= " PRIx64 " R11=3D%016" PRIx64 "\n" - "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n" - "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n", env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], @@ -371,7 +370,32 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) env->regs[12], env->regs[13], env->regs[14], - env->regs[15], + env->regs[15]); + + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX) { + qemu_fprintf(f, "R16=3D%016" PRIx64 " R17=3D%016" PRIx64 " R18= =3D%016" PRIx64 " R19=3D%016" PRIx64 "\n" + "R20=3D%016" PRIx64 " R21=3D%016" PRIx64 " R22=3D= %016" PRIx64 " R23=3D%016" PRIx64 "\n" + "R24=3D%016" PRIx64 " R25=3D%016" PRIx64 " R26=3D= %016" PRIx64 " R27=3D%016" PRIx64 "\n" + "R28=3D%016" PRIx64 " R29=3D%016" PRIx64 " R30=3D= %016" PRIx64 " R31=3D%016" PRIx64 "\n", + env->regs[16], + env->regs[17], + env->regs[18], + env->regs[19], + env->regs[20], + env->regs[21], + env->regs[22], + env->regs[23], + env->regs[24], + env->regs[25], + env->regs[26], + env->regs[27], + env->regs[28], + env->regs[29], + env->regs[30], + env->regs[31]); + } + + qemu_fprintf(f, "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] = CPL=3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", env->eip, eflags, eflags & DF_MASK ? 'D' : '-', eflags & CC_O ? 'O' : '-', --=20 2.34.1 From nobody Mon Feb 9 16:58:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1765435593; cv=none; d=zohomail.com; s=zohoarc; b=JQqY+787XOfcV91hER6DWD+HUWcQUeqhZDX5hkcag38hvUIw5JTrTrFgWX+Ldzft/kfDxG41919zqFSoHLFdjgbZFu7GndxBmw1+apQWK+CqS8C+C4Rgqk0tDVsRP1+hAsUYGOWMRO+cP/DmGQXjYADltoxyzarysZWTfjgfjIo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765435593; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2vM8a4z7AaCMMpkfeGIVgNYtAqVUEsDPMcMhcUyoEBs=; b=KobsVEJajKPWVZ8EHJex45TAUYhgo8fg30NufC/rcvTipWf9z//zmM/YND2buLd3sy1/WPtjGNeSiwbdNBSO3mV9ezIcI4hh2YVTpcuclIKqnrVsaZ2qwKR4NqqncaX4YNq0u3zhqYG0ncZgJYRWeKYPsv+rK+9x2hCuNyDT+rY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765435593363282.1711401783799; Wed, 10 Dec 2025 22:46:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vTaR0-0001wS-9P; Thu, 11 Dec 2025 01:45:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTaQd-0001ks-Mf for qemu-devel@nongnu.org; Thu, 11 Dec 2025 01:45:42 -0500 Received: from mgamail.intel.com ([198.175.65.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTaQb-00067P-LU for qemu-devel@nongnu.org; Thu, 11 Dec 2025 01:45:31 -0500 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2025 22:45:29 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa009.jf.intel.com with ESMTP; 10 Dec 2025 22:45:25 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765435530; x=1796971530; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d4fEjjgjaO1Mc5bLnP4bPrihTztTGRnCptHhP/Q5vnk=; b=iX08s+ysVRKNyoYi5oVFC098OHiGwsWqHpIElrDgC+00VIzhruuu3DN1 zuur7TgirBKX/bNx/3gr7Pr5YlFcODWevgDLR6O+9Jy28zAkpP8a6091D ZpS/9UjjmvsPLNzIXh1HbPk9i8hTCahgFv7Ah61dwk/gOE/Dnwx9q/MLb txKoLsdDQJqVTUmRD4OdWqKvG6078BChKuT8nC/jugrDfN07zIMD51Fyi rdb6S1Nm0FLWhzxmi60M/AfKN1C7AVsQ2LU/kOVHJ85js+4WrLDq6Imye tAhHwC4mJXBC90nrW4AmKpzbUouyLgPkyKu65gmuQEKkbn+vkHmyNytt9 Q==; X-CSE-ConnectionGUID: oNR8QO6SQha6HkccsA9+og== X-CSE-MsgGUID: sbpvM61jTFS4kPOrIBttUA== X-IronPort-AV: E=McAfee;i="6800,10657,11638"; a="67584467" X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="67584467" X-CSE-ConnectionGUID: 52B2NNYHQ4GOo6aL5RfDfw== X-CSE-MsgGUID: P3rtpxZpSCCAnIq8CXohyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="196495009" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Xu , Fabiano Rosas Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, "Chang S . Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 6/9] i386/monitor: Support EGPRs in hmp_print Date: Thu, 11 Dec 2025 15:09:39 +0800 Message-Id: <20251211070942.3612547-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765435594278158500 Content-Type: text/plain; charset="utf-8" Add EGPRs in monitor_defs[] to allow HMP to access EGPRs. For example, (qemu) print $r16 Since monitor_defs[] is used for read-only case, no need to consider xstate synchronization issues that might be caused by modifying EGPRs (like what gdbstub did). Suggested-by: Paolo Bonzini Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Changes since v1: * New patch. --- target/i386/monitor.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/i386/monitor.c b/target/i386/monitor.c index d2bb873d4947..99b32cb7b0f3 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -623,6 +623,22 @@ const MonitorDef monitor_defs[] =3D { { "r13", offsetof(CPUX86State, regs[13]) }, { "r14", offsetof(CPUX86State, regs[14]) }, { "r15", offsetof(CPUX86State, regs[15]) }, + { "r16", offsetof(CPUX86State, regs[16]) }, + { "r17", offsetof(CPUX86State, regs[17]) }, + { "r18", offsetof(CPUX86State, regs[18]) }, + { "r19", offsetof(CPUX86State, regs[19]) }, + { "r20", offsetof(CPUX86State, regs[20]) }, + { "r21", offsetof(CPUX86State, regs[21]) }, + { "r22", offsetof(CPUX86State, regs[22]) }, + { "r23", offsetof(CPUX86State, regs[23]) }, + { "r24", offsetof(CPUX86State, regs[24]) }, + { "r25", offsetof(CPUX86State, regs[25]) }, + { "r26", offsetof(CPUX86State, regs[26]) }, + { "r27", offsetof(CPUX86State, regs[27]) }, + { "r28", offsetof(CPUX86State, regs[28]) }, + { "r29", offsetof(CPUX86State, regs[29]) }, + { "r30", offsetof(CPUX86State, regs[30]) }, + { "r31", offsetof(CPUX86State, regs[31]) }, #endif { "eflags", offsetof(CPUX86State, eflags) }, { "eip", offsetof(CPUX86State, eip) }, --=20 2.34.1 From nobody Mon Feb 9 16:58:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="67584480" X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="67584480" X-CSE-ConnectionGUID: Q2YHT5SBQdOe7je04jo1ZQ== X-CSE-MsgGUID: gDb1d5ukQtOD7OhQ8nJKJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="196495019" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Xu , Fabiano Rosas Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, "Chang S . Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 7/9] i386/cpu: Add APX migration support Date: Thu, 11 Dec 2025 15:09:40 +0800 Message-Id: <20251211070942.3612547-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765435590338158500 Content-Type: text/plain; charset="utf-8" From: Zide Chen Add a VMStateDescription to migrate APX EGPRs. Tested-by: Xudong Hao Signed-off-by: Zide Chen Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes since v1: * Use CPUX86State.regs instead of a new array. --- target/i386/machine.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/i386/machine.c b/target/i386/machine.c index 0882dc3eb09e..df550dec4749 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1741,6 +1741,28 @@ static const VMStateDescription vmstate_cet =3D { }, }; =20 +#ifdef TARGET_X86_64 +static bool apx_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!(env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX); +} + +static const VMStateDescription vmstate_apx =3D { + .name =3D "cpu/apx", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D apx_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL_SUB_ARRAY(env.regs, X86CPU, CPU_NB_REGS, + CPU_NB_EREGS - CPU_NB_REGS), + VMSTATE_END_OF_LIST() + } +}; +#endif + const VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -1892,6 +1914,9 @@ const VMStateDescription vmstate_x86_cpu =3D { &vmstate_triple_fault, &vmstate_pl0_ssp, &vmstate_cet, +#ifdef TARGET_X86_64 + &vmstate_apx, +#endif NULL } }; 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Bae" , Zide Chen , Xudong Hao , Zhao Liu , Peter Fang Subject: [PATCH v2 8/9] i386/cpu: Support APX CPUIDs Date: Thu, 11 Dec 2025 15:09:41 +0800 Message-Id: <20251211070942.3612547-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765435592261158500 Content-Type: text/plain; charset="utf-8" APX is enumerated by CPUID.(EAX=3D0x7, ECX=3D1).EDX[21]. And this feature bit also indicates the existence of dedicated CPUID leaf 0x29, called the Intel APX Advanced Performance Extensions Leaf. This new CPUID leaf now is populated with enumerations for a select set of Intel APX sub-features. CPUID.(EAX=3D0x29, ECX=3D0) - EAX * Maximum Subleaf CPUID.(EAX=3D0x29, ECX=3D0).EAX[31:0] =3D 0 - EBX * Reserved CPUID.(EAX=3D0x29, ECX=3D0).EBX[31:1] =3D 0 * APX_NCI_NDD_NF CPUID.(EAX=3D0x29, ECX=3D0).EBX[0:0] =3D 1, which enumerates the presence of New Conditional Instructions (NCIs), explicit New Data Destination (NDD) controls, and explicit Flags Suppression (NF) controls for select sets of EVEX-encoded Intel APX instructions (present in EVEX map=3D4, and EVEX map=3D2 0x0F38). - ECX * Reserved CPUID.(EAX=3D0x29, ECX=3D0).ECX[31:0] =3D 0 - EDX * Reserved CPUID.(EAX=3D0x29, ECX=3D0).EDX[31:0] =3D 0 Note, APX_NCI_NDD_NF is documented as always enabled for Intel processors since APX spec (revision v7.0). Now any Intel processor that enumerates support for APX_F (CPUID.(EAX=3D0x7, ECX=3D1).EDX[21]) will also enumerate support for APX_NCI_NDD_NF. Tested-by: Xudong Hao Co-developed-by: Zide Chen Signed-off-by: Zide Chen Co-developed-by: Peter Fang Signed-off-by: Peter Fang Signed-off-by: Zhao Liu --- target/i386/cpu.c | 40 +++++++++++++++++++++++++++++++++++++++- target/i386/cpu.h | 8 ++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 16bc4b18266c..9cc553a86442 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1036,6 +1036,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t ven= dor1, #define TCG_SGX_12_0_EBX_FEATURES 0 #define TCG_SGX_12_1_EAX_FEATURES 0 #define TCG_24_0_EBX_FEATURES 0 +#define TCG_29_0_EBX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1301,7 +1302,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "amx-complex", NULL, "avx-vnni-int16", NULL, NULL, NULL, "prefetchiti", NULL, NULL, NULL, NULL, "avx10", - NULL, NULL, NULL, NULL, + NULL, "apx", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, @@ -1345,6 +1346,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_24_0_EBX_FEATURES, }, + [FEAT_29_0_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + "apx-nci-ndd-nf", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { + .eax =3D 0x29, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EBX, + }, + .tcg_features =3D TCG_29_0_EBX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -1996,6 +2016,10 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, .to =3D { FEAT_24_0_EBX, ~0ull }, }, + { + .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_APX }, + .to =3D { FEAT_29_0_EBX, ~0ull }, + }, }; =20 typedef struct X86RegisterInfo32 { @@ -8411,6 +8435,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x29: + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX) && count =3D= =3D 0) { + *ebx =3D env->features[FEAT_29_0_EBX]; + } + break; case 0x40000000: /* * CPUID code in kvm_arch_init_vcpu() ignores stuff @@ -9190,6 +9223,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); } =20 + /* Advanced Performance Extensions (APX) requires CPUID[0x29] */ + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x29); + } + /* SVM requires CPUID[0x8000000A] */ if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index edc18e4b3da8..08216b343afa 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -710,6 +710,7 @@ typedef enum FeatureWord { FEAT_7_1_EDX, /* CPUID[EAX=3D7,ECX=3D1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=3D7,ECX=3D2].EDX */ FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ + FEAT_29_0_EBX, /* CPUID[EAX=3D0x29,ECX=3D0].EBX */ FEATURE_WORDS, } FeatureWord; =20 @@ -1092,6 +1093,13 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w); CPUID_24_0_EBX_AVX10_256 | \ CPUID_24_0_EBX_AVX10_512) =20 +/* + * New Conditional Instructions (NCIs), explicit New Data Destination (NDD) + * controls, and explicit Flags Suppression (NF) controls for select sets = of + * EVEX-encoded Intel APX instructions + */ +#define CPUID_29_0_EBX_APX_NCI_NDD_NF (1U << 0) + /* RAS Features */ #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0) #define CPUID_8000_0007_EBX_SUCCOR (1U << 1) --=20 2.34.1 From nobody Mon Feb 9 16:58:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1765435569; cv=none; d=zohomail.com; s=zohoarc; b=jN1DzMKvyratykR+nk0M/zoSRQPLnnF24pgs5QiT7JIGN/tNGZszhg9nyxEvapWtI1GUSHqTAzm0YxsqDbxS/6fRHOBOegScLJaELpXisonPYmSXXvBLJPuwjpMO/Eah9NVC3RMcVKv6+Fh0b6WgL0HN+ZbUu0xrBCLx7mviEwQ= ARC-Message-Signature: i=1; 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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 9/9] i386/cpu: Mark APX xstate as migratable Date: Thu, 11 Dec 2025 15:09:42 +0800 Message-Id: <20251211070942.3612547-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765435570189158500 Content-Type: text/plain; charset="utf-8" APX xstate is user xstate. The related registers are cached in X86CPUState. And there's a vmsd "vmstate_apx" to migrate these registers. Thus, it's safe to mark it as migratable. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9cc553a86442..f703b1478d71 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1544,7 +1544,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .migratable_flags =3D XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_M= ASK | - XSTATE_PKRU_MASK | XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_M= ASK, + XSTATE_PKRU_MASK | XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_M= ASK | + XSTATE_APX_MASK, }, [FEAT_XSAVE_XCR0_HI] =3D { .type =3D CPUID_FEATURE_WORD, --=20 2.34.1