From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the AST1700 device as a child of the AST27X0 model to reflect
its role in DC-SCM 2.0 LTPI-based architectures. This patch wires
the AST1700 device into the platform without introducing functional
peripherals.
This forms the base for LTPI expander emulation in QEMU using
AST27X0 as the host controller.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 9 +++++++--
include/hw/misc/aspeed_ast1700.h | 1 +
hw/arm/aspeed_ast27x0.c | 30 ++++++++++++++++++++++--------
hw/misc/aspeed_ast1700.c | 6 ++++++
4 files changed, 36 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index bae60d85ea..00cd8df038 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -43,6 +43,7 @@
#include "hw/char/serial-mm.h"
#include "hw/intc/arm_gicv3.h"
#include "hw/misc/aspeed_ltpi.h"
+#include "hw/misc/aspeed_ast1700.h"
#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
@@ -109,10 +110,10 @@ struct AspeedSoCState {
UnimplementedDeviceState espi;
UnimplementedDeviceState udc;
UnimplementedDeviceState sgpiom;
- UnimplementedDeviceState ltpi;
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
AspeedAPB2OPBState fsi[2];
AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
+ AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM];
};
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -174,6 +175,7 @@ struct AspeedSoCClass {
int macs_num;
int uarts_num;
int uarts_base;
+ int ioexp_num;
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
@@ -186,7 +188,8 @@ enum {
ASPEED_DEV_IOMEM,
ASPEED_DEV_IOMEM0,
ASPEED_DEV_IOMEM1,
- ASPEED_DEV_LTPI,
+ ASPEED_DEV_LTPI_IO0,
+ ASPEED_DEV_LTPI_IO1,
ASPEED_DEV_UART0,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
@@ -280,6 +283,8 @@ enum {
ASPEED_DEV_IPC1,
ASPEED_DEV_LTPI_CTRL1,
ASPEED_DEV_LTPI_CTRL2,
+ ASPEED_DEV_IOEXP0_INTCIO,
+ ASPEED_DEV_IOEXP1_INTCIO,
};
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index b7c666eef2..624ef61eda 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -20,6 +20,7 @@
#include "hw/misc/unimp.h"
#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
+#define TYPE_ASPEED_AST1700_AST2700 "aspeed.ast1700-ast2700"
OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index c0d8639bde..054864467d 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -26,7 +26,6 @@
#define AST2700_SOC_IO_SIZE 0x00FE0000
#define AST2700_SOC_IOMEM_SIZE 0x01000000
#define AST2700_SOC_DPMCU_SIZE 0x00040000
-#define AST2700_SOC_LTPI_SIZE 0x01000000
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_VBOOTROM] = 0x00000000,
@@ -89,11 +88,14 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
[ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
[ASPEED_DEV_WDT] = 0x14C37000,
+ [ASPEED_DEV_LTPI_IO0] = 0x30000000,
+ [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
+ [ASPEED_DEV_LTPI_IO1] = 0x50000000,
+ [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
[ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
[ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
[ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
[ASPEED_DEV_SPI_BOOT] = 0x100000000,
- [ASPEED_DEV_LTPI] = 0x300000000,
[ASPEED_DEV_SDRAM] = 0x400000000,
};
@@ -549,10 +551,15 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "ltpi-ctrl[*]",
&s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
}
+
+ for (i = 0; i < sc->ioexp_num; i++) {
+ /* AST1700 IOEXP */
+ object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
+ TYPE_ASPEED_AST1700_AST2700);
+ }
+
object_initialize_child(obj, "dpmcu", &s->dpmcu,
TYPE_UNIMPLEMENTED_DEVICE);
- object_initialize_child(obj, "ltpi", &s->ltpi,
- TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "iomem", &s->iomem,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "iomem0", &s->iomem0,
@@ -1039,14 +1046,20 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
}
+
+ /* IO Expander */
+ for (i = 0; i < sc->ioexp_num; i++) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
+ sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
+ }
+
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
"aspeed.dpmcu",
sc->memmap[ASPEED_DEV_DPMCU],
AST2700_SOC_DPMCU_SIZE);
- aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi),
- "aspeed.ltpi",
- sc->memmap[ASPEED_DEV_LTPI],
- AST2700_SOC_LTPI_SIZE);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
"aspeed.io",
sc->memmap[ASPEED_DEV_IOMEM],
@@ -1112,6 +1125,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
sc->macs_num = 3;
sc->uarts_num = 13;
sc->num_cpus = 4;
+ sc->ioexp_num = 2;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast2700a1_irqmap;
sc->memmap = aspeed_soc_ast2700_memmap;
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index bb05e392f4..3125bec795 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -48,10 +48,16 @@ static const TypeInfo aspeed_ast1700_info = {
.instance_init = aspeed_ast1700_instance_init,
};
+static const TypeInfo aspeed_ast1700_ast2700_info = {
+ .name = TYPE_ASPEED_AST1700_AST2700,
+ .parent = TYPE_ASPEED_AST1700,
+};
+
static void aspeed_ast1700_register_types(void)
{
type_register_static(&aspeed_ast1700_info);
+ type_register_static(&aspeed_ast1700_ast2700_info);
}
type_init(aspeed_ast1700_register_types);
--
2.43.0On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the AST1700 device as a child of the AST27X0 model to reflect
> its role in DC-SCM 2.0 LTPI-based architectures. This patch wires
> the AST1700 device into the platform without introducing functional
> peripherals.
>
> This forms the base for LTPI expander emulation in QEMU using
> AST27X0 as the host controller.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/arm/aspeed_soc.h | 9 +++++++--
> include/hw/misc/aspeed_ast1700.h | 1 +
> hw/arm/aspeed_ast27x0.c | 30 ++++++++++++++++++++++--------
> hw/misc/aspeed_ast1700.c | 6 ++++++
> 4 files changed, 36 insertions(+), 10 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index bae60d85ea..00cd8df038 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -43,6 +43,7 @@
> #include "hw/char/serial-mm.h"
> #include "hw/intc/arm_gicv3.h"
> #include "hw/misc/aspeed_ltpi.h"
> +#include "hw/misc/aspeed_ast1700.h"
>
> #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
>
> @@ -109,10 +110,10 @@ struct AspeedSoCState {
> UnimplementedDeviceState espi;
> UnimplementedDeviceState udc;
> UnimplementedDeviceState sgpiom;
> - UnimplementedDeviceState ltpi;
> UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
> AspeedAPB2OPBState fsi[2];
> AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
> + AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM];
> };
>
> #define TYPE_ASPEED_SOC "aspeed-soc"
> @@ -174,6 +175,7 @@ struct AspeedSoCClass {
> int macs_num;
> int uarts_num;
> int uarts_base;
> + int ioexp_num;
> const int *irqmap;
> const hwaddr *memmap;
> uint32_t num_cpus;
> @@ -186,7 +188,8 @@ enum {
> ASPEED_DEV_IOMEM,
> ASPEED_DEV_IOMEM0,
> ASPEED_DEV_IOMEM1,
> - ASPEED_DEV_LTPI,
> + ASPEED_DEV_LTPI_IO0,
> + ASPEED_DEV_LTPI_IO1,
> ASPEED_DEV_UART0,
> ASPEED_DEV_UART1,
> ASPEED_DEV_UART2,
> @@ -280,6 +283,8 @@ enum {
> ASPEED_DEV_IPC1,
> ASPEED_DEV_LTPI_CTRL1,
> ASPEED_DEV_LTPI_CTRL2,
> + ASPEED_DEV_IOEXP0_INTCIO,
> + ASPEED_DEV_IOEXP1_INTCIO,
Please put the index number at the end of the enum definition.
These definitions are unused too. Please move in the next patch.
> };
>
> const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
> index b7c666eef2..624ef61eda 100644
> --- a/include/hw/misc/aspeed_ast1700.h
> +++ b/include/hw/misc/aspeed_ast1700.h
> @@ -20,6 +20,7 @@
> #include "hw/misc/unimp.h"
>
> #define TYPE_ASPEED_AST1700 "aspeed.ast1700"
> +#define TYPE_ASPEED_AST1700_AST2700 "aspeed.ast1700-ast2700"
>
> OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index c0d8639bde..054864467d 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -26,7 +26,6 @@
> #define AST2700_SOC_IO_SIZE 0x00FE0000
> #define AST2700_SOC_IOMEM_SIZE 0x01000000
> #define AST2700_SOC_DPMCU_SIZE 0x00040000
> -#define AST2700_SOC_LTPI_SIZE 0x01000000
>
> static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_VBOOTROM] = 0x00000000,
> @@ -89,11 +88,14 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
> [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
> [ASPEED_DEV_WDT] = 0x14C37000,
> + [ASPEED_DEV_LTPI_IO0] = 0x30000000,
> + [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
> + [ASPEED_DEV_LTPI_IO1] = 0x50000000,
> + [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
> [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
> [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
> [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
> [ASPEED_DEV_SPI_BOOT] = 0x100000000,
> - [ASPEED_DEV_LTPI] = 0x300000000,
> [ASPEED_DEV_SDRAM] = 0x400000000,
> };
>
> @@ -549,10 +551,15 @@ static void aspeed_soc_ast2700_init(Object *obj)
> object_initialize_child(obj, "ltpi-ctrl[*]",
> &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
> }
> +
> + for (i = 0; i < sc->ioexp_num; i++) {
> + /* AST1700 IOEXP */
> + object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
> + TYPE_ASPEED_AST1700_AST2700);
> + }
> +
> object_initialize_child(obj, "dpmcu", &s->dpmcu,
> TYPE_UNIMPLEMENTED_DEVICE);
> - object_initialize_child(obj, "ltpi", &s->ltpi,
> - TYPE_UNIMPLEMENTED_DEVICE);
> object_initialize_child(obj, "iomem", &s->iomem,
> TYPE_UNIMPLEMENTED_DEVICE);
> object_initialize_child(obj, "iomem0", &s->iomem0,
> @@ -1039,14 +1046,20 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> }
> aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
> }
> +
> + /* IO Expander */
> + for (i = 0; i < sc->ioexp_num; i++) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
> + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> + }
> +
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> "aspeed.dpmcu",
> sc->memmap[ASPEED_DEV_DPMCU],
> AST2700_SOC_DPMCU_SIZE);
> - aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi),
> - "aspeed.ltpi",
> - sc->memmap[ASPEED_DEV_LTPI],
> - AST2700_SOC_LTPI_SIZE);
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
> "aspeed.io",
> sc->memmap[ASPEED_DEV_IOMEM],
> @@ -1112,6 +1125,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
> sc->macs_num = 3;
> sc->uarts_num = 13;
> sc->num_cpus = 4;
> + sc->ioexp_num = 2;
> sc->uarts_base = ASPEED_DEV_UART0;
> sc->irqmap = aspeed_soc_ast2700a1_irqmap;
> sc->memmap = aspeed_soc_ast2700_memmap;
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> index bb05e392f4..3125bec795 100644
> --- a/hw/misc/aspeed_ast1700.c
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -48,10 +48,16 @@ static const TypeInfo aspeed_ast1700_info = {
> .instance_init = aspeed_ast1700_instance_init,
> };
>
> +static const TypeInfo aspeed_ast1700_ast2700_info = {
> + .name = TYPE_ASPEED_AST1700_AST2700,
> + .parent = TYPE_ASPEED_AST1700,
> +};
> +
As discussed earlier, this type is not useful.
Thanks,
C.
>
> static void aspeed_ast1700_register_types(void)
> {
> type_register_static(&aspeed_ast1700_info);
> + type_register_static(&aspeed_ast1700_ast2700_info);
> }
>
> type_init(aspeed_ast1700_register_types);
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