From nobody Fri Nov 14 17:01:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762315209; cv=none; d=zohomail.com; s=zohoarc; b=GkRlV6/P2NpptVJSQmET5Yr3wabNndNr+UBiljuqWA9B3vNZZt/B6nIifwvvdKhce6ErkusNdfXVrD0ggX0iNSv5pqZEuBT3BFvE0gGhlMnh9FTDoLzbGOlfk9i4trB4bYBiBEyHZzWiP3w/7Drtkb7qh+X1DAdRI0Dza914Hbk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762315209; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=gHR98yE9xY3un5wz9hLeVEbFzKXBfVgLmZ63ny4zggo=; b=NnxAmWnJnBR28VypvGtwlDUCU/ht4AQEJiMyViiPfZc4YqcBrc+1KtzlaFaXd8XbuZLYM11SOKKoxDcBBH5+fOWoi+blrMHeps2NdjBVVNFJ76c+BFLEt9PHfzqRZ8aacU/0nczYR8c0h8F/q4/+52AL8y9iO8XWnEZlavV6wgY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315209762171.1334910684409; Tue, 4 Nov 2025 20:00:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUg7-0007Vd-7m; Tue, 04 Nov 2025 22:59:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUg4-0007UV-Hl; Tue, 04 Nov 2025 22:59:20 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUg2-0006sZ-Sk; Tue, 04 Nov 2025 22:59:20 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 04/17] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Date: Wed, 5 Nov 2025 11:58:42 +0800 Message-ID: <20251105035859.3709907-5-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315213431154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the AST1700 device as a child of the AST27X0 model to reflect its role in DC-SCM 2.0 LTPI-based architectures. This patch wires the AST1700 device into the platform without introducing functional peripherals. This forms the base for LTPI expander emulation in QEMU using AST27X0 as the host controller. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 9 +++++++-- include/hw/misc/aspeed_ast1700.h | 1 + hw/arm/aspeed_ast27x0.c | 30 ++++++++++++++++++++++-------- hw/misc/aspeed_ast1700.c | 6 ++++++ 4 files changed, 36 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index bae60d85ea..00cd8df038 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -43,6 +43,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/misc/aspeed_ast1700.h" =20 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 @@ -109,10 +110,10 @@ struct AspeedSoCState { UnimplementedDeviceState espi; UnimplementedDeviceState udc; UnimplementedDeviceState sgpiom; - UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; + AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM]; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -174,6 +175,7 @@ struct AspeedSoCClass { int macs_num; int uarts_num; int uarts_base; + int ioexp_num; const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; @@ -186,7 +188,8 @@ enum { ASPEED_DEV_IOMEM, ASPEED_DEV_IOMEM0, ASPEED_DEV_IOMEM1, - ASPEED_DEV_LTPI, + ASPEED_DEV_LTPI_IO0, + ASPEED_DEV_LTPI_IO1, ASPEED_DEV_UART0, ASPEED_DEV_UART1, ASPEED_DEV_UART2, @@ -280,6 +283,8 @@ enum { ASPEED_DEV_IPC1, ASPEED_DEV_LTPI_CTRL1, ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_IOEXP0_INTCIO, + ASPEED_DEV_IOEXP1_INTCIO, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index b7c666eef2..624ef61eda 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -20,6 +20,7 @@ #include "hw/misc/unimp.h" =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" +#define TYPE_ASPEED_AST1700_AST2700 "aspeed.ast1700-ast2700" =20 OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700) =20 diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index c0d8639bde..054864467d 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -26,7 +26,6 @@ #define AST2700_SOC_IO_SIZE 0x00FE0000 #define AST2700_SOC_IOMEM_SIZE 0x01000000 #define AST2700_SOC_DPMCU_SIZE 0x00040000 -#define AST2700_SOC_LTPI_SIZE 0x01000000 =20 static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_VBOOTROM] =3D 0x00000000, @@ -89,11 +88,14 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL1] =3D 0x14C34000, [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, + [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_IOEXP0_INTCIO] =3D 0x30C18000, + [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, + [ASPEED_DEV_IOEXP1_INTCIO] =3D 0x50C18000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, - [ASPEED_DEV_LTPI] =3D 0x300000000, [ASPEED_DEV_SDRAM] =3D 0x400000000, }; =20 @@ -549,10 +551,15 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "ltpi-ctrl[*]", &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); } + + for (i =3D 0; i < sc->ioexp_num; i++) { + /* AST1700 IOEXP */ + object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], + TYPE_ASPEED_AST1700_AST2700); + } + object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); - object_initialize_child(obj, "ltpi", &s->ltpi, - TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem0", &s->iomem0, @@ -1039,14 +1046,20 @@ static void aspeed_soc_ast2700_realize(DeviceState = *dev, Error **errp) } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base= ); } + + /* IO Expander */ + for (i =3D 0; i < sc->ioexp_num; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0, + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); + } + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], AST2700_SOC_DPMCU_SIZE); - aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi), - "aspeed.ltpi", - sc->memmap[ASPEED_DEV_LTPI], - AST2700_SOC_LTPI_SIZE); aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", sc->memmap[ASPEED_DEV_IOMEM], @@ -1112,6 +1125,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->macs_num =3D 3; sc->uarts_num =3D 13; sc->num_cpus =3D 4; + sc->ioexp_num =3D 2; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; sc->memmap =3D aspeed_soc_ast2700_memmap; diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index bb05e392f4..3125bec795 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -48,10 +48,16 @@ static const TypeInfo aspeed_ast1700_info =3D { .instance_init =3D aspeed_ast1700_instance_init, }; =20 +static const TypeInfo aspeed_ast1700_ast2700_info =3D { + .name =3D TYPE_ASPEED_AST1700_AST2700, + .parent =3D TYPE_ASPEED_AST1700, +}; + =20 static void aspeed_ast1700_register_types(void) { type_register_static(&aspeed_ast1700_info); + type_register_static(&aspeed_ast1700_ast2700_info); } =20 type_init(aspeed_ast1700_register_types); --=20 2.43.0