On Wed, Oct 15, 2025 at 6:35 AM Anton Johansson via
<qemu-devel@nongnu.org> wrote:
>
> and update formatting in log.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 +-
> target/riscv/cpu_helper.c | 2 +-
> target/riscv/machine.c | 2 +-
> target/riscv/tcg/tcg-cpu.c | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4b291dbf81..25f996985b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -279,7 +279,7 @@ struct CPUArchState {
> target_ulong geilen;
> uint64_t resetvec;
>
> - target_ulong mhartid;
> + uint64_t mhartid;
> /*
> * For RV32 this is 32-bit mstatus and 32-bit mstatush.
> * For RV64 this is a 64-bit mstatus.
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 3479a62cc7..9d0683f200 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -2278,7 +2278,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> riscv_cpu_get_trap_name(cause, async));
>
> qemu_log_mask(CPU_LOG_INT,
> - "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
> + "%s: hart:%"PRIu64", async:%d, cause:"TARGET_FMT_lx", "
> "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
> __func__, env->mhartid, async, cause, env->pc, tval,
> riscv_cpu_get_trap_name(cause, async));
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index f6ca017211..ab0bc32e1f 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -450,7 +450,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.priv, RISCVCPU),
> VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
> VMSTATE_UINT64(env.resetvec, RISCVCPU),
> - VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> + VMSTATE_UINT64(env.mhartid, RISCVCPU),
> VMSTATE_UINT64(env.mstatus, RISCVCPU),
> VMSTATE_UINT64(env.mip, RISCVCPU),
> VMSTATE_UINT64(env.miclaim, RISCVCPU),
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 1150bd1469..db3cbc1625 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -487,7 +487,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> continue;
> }
> #ifndef CONFIG_USER_ONLY
> - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> + warn_report("disabling %s extension for hart 0x%" PRIx64
> " because privilege spec version does not match",
> edata->name, env->mhartid);
> #else
> --
> 2.51.0
>
>