On Wed, Oct 15, 2025 at 6:37 AM Anton Johansson via
<qemu-devel@nongnu.org> wrote:
>
> Fix these fields to 32 bits, also update corresponding priv_ver field
> in DisasContext as well as function arguments. 32 bits was chosen
> since it's large enough to fit all stored values and int/int32_t is
> used in RISCVCPUDef and a few functions.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 6 +++---
> target/riscv/machine.c | 4 ++--
> target/riscv/translate.c | 2 +-
> 3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bcf10a4c8b..6ed912cbd1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -238,8 +238,8 @@ struct CPUArchState {
>
> uint64_t guest_phys_fault_addr;
>
> - target_ulong priv_ver;
> - target_ulong vext_ver;
> + uint32_t priv_ver;
> + uint32_t vext_ver;
>
> /* RISCVMXL, but uint32_t for vmstate migration */
> uint32_t misa_mxl; /* current mxl */
> @@ -799,7 +799,7 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
> #endif
>
> static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg,
> - target_long priv_ver,
> + uint32_t priv_ver,
> uint32_t misa_ext)
> {
> /* In priv spec version 1.12 or newer, C always implies Zca */
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 27034180c4..1cf744c5f0 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -439,8 +439,8 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINT8(env.frm, RISCVCPU),
> VMSTATE_UINT64(env.badaddr, RISCVCPU),
> VMSTATE_UINT64(env.guest_phys_fault_addr, RISCVCPU),
> - VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
> - VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
> + VMSTATE_UINT32(env.priv_ver, RISCVCPU),
> + VMSTATE_UINT32(env.vext_ver, RISCVCPU),
> VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
> VMSTATE_UINT32(env.misa_ext, RISCVCPU),
> VMSTATE_UNUSED(4),
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 2770c06413..14c8f1c6a2 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -60,7 +60,7 @@ typedef struct DisasContext {
> DisasContextBase base;
> target_ulong cur_insn_len;
> target_ulong pc_save;
> - target_ulong priv_ver;
> + uint32_t priv_ver;
> RISCVMXL misa_mxl_max;
> RISCVMXL xl;
> RISCVMXL address_xl;
> --
> 2.51.0
>
>