From nobody Thu Oct 16 04:49:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1760474110; cv=none; d=zohomail.com; s=zohoarc; b=eKdvHyKDE1pMzFcyYYmZB5RWIsyYQ/xyocJUw48XRLjcFROWVtBusVQLen1sOi79O2b7JwBy4JghXxF/HQojo9Ffv5s9uW9cb/JyapE/+g/EKXsODrBRfag6U9MiIe4BCHtIxgvAcWoqIUOOKYzB307Fa45VWbrttvcfyuNtPJg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760474110; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=hr0Ny9yER4yUsNQYGUoDhbnGJYLE0rj7JMjSciiggJk=; b=h+twnEv9sPyuKCUh2RIDdtKZxA1vpsY9JM0TbPL0E/0Nnmnzo1cyiDYhn3WJBbMmBez6ms1gH7fxytHm93xT9Qfl3QuZ2X4XZ35Ax9c1HvoylGMxanX3+WRdvKdfTEzRM0wkJY7XyrGZGfL1ekUS/R3sQWNG6fDrZD9Kyt2/GaE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760474110167327.1099363915872; Tue, 14 Oct 2025 13:35:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v8li7-0000xk-10; Tue, 14 Oct 2025 16:33:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v8li5-0000ww-05 for qemu-devel@nongnu.org; Tue, 14 Oct 2025 16:33:29 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v8li2-0000SU-Qb for qemu-devel@nongnu.org; Tue, 14 Oct 2025 16:33:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=hr0Ny9yER4yUsNQYGUoDhbnGJYLE0rj7JMjSciiggJk=; b=scNwG+nyCgD8fYF VKE6cZZRbN25IsZ/OAJtOTHVecEkf5RH+kYY6/qsmp4FX5qZX9fVCGnqS76qSbA3Sec7GqKFJkSi7 mFqtKHHZ3jAbVXY6ufk9iRoyhZXidHxNOUNWDj7yrL/C2gPyy/bOBzGDWfk3enRp/9fxWlp2SLBKJ Uo=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com Subject: [PATCH v3 16/34] target/riscv: Fix size of priv_ver and vext_ver Date: Tue, 14 Oct 2025 22:34:53 +0200 Message-ID: <20251014203512.26282-17-anjo@rev.ng> In-Reply-To: <20251014203512.26282-1-anjo@rev.ng> References: <20251014203512.26282-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1760474111715158500 Content-Type: text/plain; charset="utf-8" Fix these fields to 32 bits, also update corresponding priv_ver field in DisasContext as well as function arguments. 32 bits was chosen since it's large enough to fit all stored values and int/int32_t is used in RISCVCPUDef and a few functions. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 6 +++--- target/riscv/machine.c | 4 ++-- target/riscv/translate.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bcf10a4c8b..6ed912cbd1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -238,8 +238,8 @@ struct CPUArchState { =20 uint64_t guest_phys_fault_addr; =20 - target_ulong priv_ver; - target_ulong vext_ver; + uint32_t priv_ver; + uint32_t vext_ver; =20 /* RISCVMXL, but uint32_t for vmstate migration */ uint32_t misa_mxl; /* current mxl */ @@ -799,7 +799,7 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) #endif =20 static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg, - target_long priv_ver, + uint32_t priv_ver, uint32_t misa_ext) { /* In priv spec version 1.12 or newer, C always implies Zca */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 27034180c4..1cf744c5f0 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -439,8 +439,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT8(env.frm, RISCVCPU), VMSTATE_UINT64(env.badaddr, RISCVCPU), VMSTATE_UINT64(env.guest_phys_fault_addr, RISCVCPU), - VMSTATE_UINTTL(env.priv_ver, RISCVCPU), - VMSTATE_UINTTL(env.vext_ver, RISCVCPU), + VMSTATE_UINT32(env.priv_ver, RISCVCPU), + VMSTATE_UINT32(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), VMSTATE_UINT32(env.misa_ext, RISCVCPU), VMSTATE_UNUSED(4), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2770c06413..14c8f1c6a2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -60,7 +60,7 @@ typedef struct DisasContext { DisasContextBase base; target_ulong cur_insn_len; target_ulong pc_save; - target_ulong priv_ver; + uint32_t priv_ver; RISCVMXL misa_mxl_max; RISCVMXL xl; RISCVMXL address_xl; --=20 2.51.0