From: Gustavo Romero <gustavo.romero@linaro.org>
Add a new flag, ARM_CP_NV_NO_TRAP, to indicate that a CP register, even
though it has opc1 == 4 or 5, does not trap when nested virtualization
is enabled (FEAT_NV/FEAT_NV2).
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20251006001018.219756-2-gustavo.romero@linaro.org
[PMM: tweaked comment text]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 732c07506d9..763de5e051c 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -144,6 +144,11 @@ enum {
* identically to the normal one, other than FGT trapping handling.)
*/
ARM_CP_ADD_TLBI_NXS = 1 << 21,
+ /*
+ * Flag: even though this sysreg has opc1 == 4 or 5, it
+ * should not trap to EL2 when HCR_EL2.NV is set.
+ */
+ ARM_CP_NV_NO_TRAP = 1 << 22,
};
/*
@@ -1178,12 +1183,17 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri)
* fragile to future new sysregs, but this seems the least likely
* to break.
*
- * In particular, note that the released sysreg XML defines that
- * the FEAT_MEC sysregs and instructions do not follow this FEAT_NV
- * trapping rule, so we will need to add an ARM_CP_* flag to indicate
- * "register does not trap on NV" to handle those if/when we implement
- * FEAT_MEC.
+ * In particular, note that the FEAT_MEC sysregs and instructions
+ * are exceptions to this trapping rule, so they are marked as
+ * ARM_CP_NV_NO_TRAP to indicate that they should not be trapped
+ * to EL2. (They are an exception because the FEAT_MEC sysregs UNDEF
+ * unless in Realm, and Realm is not expected to be virtualized.)
*/
+
+ if (ri->type & ARM_CP_NV_NO_TRAP) {
+ return false;
+ }
+
return ri->opc1 == 4 || ri->opc1 == 5;
}
--
2.43.0