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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426ce583316sm4221657f8f.20.2025.10.10.06.06.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Oct 2025 06:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760101611; x=1760706411; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EAmIkQfE9xLbeSqqtF2jX59gL8K6xolNz4VmTIBL0lA=; b=NEUtH23m2TuRR8JYaY/5zColV2YuRSA2+EhgbChlYxwLZzAwKrMIfJByx9ydrRTgek dLsaVlS+MLgiT8S72T+A5hxgcg9mE/BJiPhyqeZJsT1ffNGrF11ZglpQfZyxGn3k0tbu PLvXqgPcZVhngH4bwRPThRTTWTLE9nzonflAD0oMJJs8wRuxekEOTpEgGoN81guR8VSo Fos8jR7UyX8781U50WsfD6dXVYjSSpcOhL25d3CxmrBSeTm7uEyRKnqVFF5T3+EodsHy qBWv2qx5s4YwACH4HsH4ujq/pDQ/HLPd1B+3cZ+/O0jwhArNc/v1rHtMd0tzc08jxwrG vfPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760101611; x=1760706411; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EAmIkQfE9xLbeSqqtF2jX59gL8K6xolNz4VmTIBL0lA=; b=uWJtcT1c4URp1QXYDCbpbB12CA1uwRRnuIzG886cVqRQWxC/7BsCXuMk4RGzO2y3ys HXmRYeiP9LmUt/2oCe6s+5muzlur924lxcUIKPdzUqTojAJHZbhIj3nvz11JpCqgZZG9 oHJTcF9MSfncJm7zyViHk+vxZaa9y1hNMX12fqYJ6pJKjGjciruba9ntYeOvPszVHU7+ HpQpcd6a7OCa52zblzvBhASP9u4khMfhFsaNBnDmFsChuKT9TAR/J5dTe7wPQvNT1gYp lauxN7TCyHsgL/ArERTkiFAk5JP4zQrySgBb6dEsE4t/uFnq7I7Ln1h62N3yc/b2YxI8 LhSw== X-Gm-Message-State: AOJu0YykhpIp2nd9KhDl0E+cnt8ZcmSDB9dcRScS+Rp6t9wrCMB1qkpn Hmr08VswQy+V1xw1k5NbQtIiFcH9YVzJ3MfL2WFx4NhRkENGZKi5W8r5q+0jep3sjVCjFl7Dvs3 LS2Mv X-Gm-Gg: ASbGncut2tjehKiBWaakbL00COSOxh1TmGmQh+LEaHa3DWpQtzoz1TDF/PgO6Zwew8A KlY0n0oDhFZyTR/CMKuB2DZG8XH4GvWVjwaVRLIz7Z8HKja9svAIKuGZObFJcbYg9qqZkMq+8YC Tf7apwiSyp3JR8tc1SkxGU0AkvGcr3n0aOIn3cQJ6d1wSW4oGe8jD4FSpXEDWF9EaSkYmILA+8j K5/sAR+2FjM0OXkwudAA4AVFLJrAh3rF1+lTS7NpnUrJxeVCedkIQKakwukEmQN4KDnAUugQM2Q qJO/g/HOKUGduffkbCEWxdo3hGBWCAo80Z/2h1BiVNcW6P13I+qGOtN/LvMA/z5c9KpQGNsN8zr DbtgiuC1uMJ+GfTWudXxhGCa/6SGQtzDoZdtQDU0TQ8WlQ3Rbv2/TyP5FjVMBCQ== X-Google-Smtp-Source: AGHT+IE22fBCJh/a6L7VLjwWNxtWKCD7fAylnAuU34zsxApNv0RP3hNuLjMZXbMMjM4tNwgkaNvh6A== X-Received: by 2002:a05:6000:400f:b0:425:74bb:7c4d with SMTP id ffacd0b85a97d-4266e8e68a5mr8049876f8f.61.1760101610872; Fri, 10 Oct 2025 06:06:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 74/76] target/arm: Add a cpreg flag to indicate no trap in NV Date: Fri, 10 Oct 2025 14:05:25 +0100 Message-ID: <20251010130527.3921602-75-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251010130527.3921602-1-peter.maydell@linaro.org> References: <20251010130527.3921602-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760102773357158500 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Add a new flag, ARM_CP_NV_NO_TRAP, to indicate that a CP register, even though it has opc1 =3D=3D 4 or 5, does not trap when nested virtualization is enabled (FEAT_NV/FEAT_NV2). Signed-off-by: Gustavo Romero Message-id: 20251006001018.219756-2-gustavo.romero@linaro.org [PMM: tweaked comment text] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 732c07506d9..763de5e051c 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -144,6 +144,11 @@ enum { * identically to the normal one, other than FGT trapping handling.) */ ARM_CP_ADD_TLBI_NXS =3D 1 << 21, + /* + * Flag: even though this sysreg has opc1 =3D=3D 4 or 5, it + * should not trap to EL2 when HCR_EL2.NV is set. + */ + ARM_CP_NV_NO_TRAP =3D 1 << 22, }; =20 /* @@ -1178,12 +1183,17 @@ static inline bool arm_cpreg_traps_in_nv(const ARMC= PRegInfo *ri) * fragile to future new sysregs, but this seems the least likely * to break. * - * In particular, note that the released sysreg XML defines that - * the FEAT_MEC sysregs and instructions do not follow this FEAT_NV - * trapping rule, so we will need to add an ARM_CP_* flag to indicate - * "register does not trap on NV" to handle those if/when we implement - * FEAT_MEC. + * In particular, note that the FEAT_MEC sysregs and instructions + * are exceptions to this trapping rule, so they are marked as + * ARM_CP_NV_NO_TRAP to indicate that they should not be trapped + * to EL2. (They are an exception because the FEAT_MEC sysregs UNDEF + * unless in Realm, and Realm is not expected to be virtualized.) */ + + if (ri->type & ARM_CP_NV_NO_TRAP) { + return false; + } + return ri->opc1 =3D=3D 4 || ri->opc1 =3D=3D 5; } =20 --=20 2.43.0