This series adds support for all FEAT_MEC registers and cache
instructions to the Arm64 max CPU.

It includes the FEAT_MEC registers and cache maintenance instructions,
but does not modify the translation regimes to support the MECIDs, so no
encryption is supported yet. However, software stacks that rely on
FEAT_MEC should work properly at this point.


Cheers,
Gustavo

v10:
- Addressed comment from pm215 that registers with opc1 == 4 or 5 must
  actually not trap when nested virtualization is turned on. This
  resulted in one additional patch in the series:
  "Add a cpreg flag to indicate no trap in NV".

All previous versions of this series can be found in:

https://patchew.org/QEMU/20250727074202.83141-1-richard.henderson@linaro.org/

Please note that the patches related to FEAT_SCTRL2 and FEAT_TCR2, which
are prerequisites for this series, have already been merged into master.


Gustavo Romero (3):
  target/arm: Add a cpreg flag to indicate no trap in NV
  target/arm: Implement FEAT_MEC registers
  target/arm: Enable FEAT_MEC in -cpu max

 docs/system/arm/emulation.rst |   3 +
 target/arm/cpregs.h           |  11 +++-
 target/arm/cpu-features.h     |   5 ++
 target/arm/cpu.c              |   3 +
 target/arm/cpu.h              |  10 ++++
 target/arm/helper.c           | 109 ++++++++++++++++++++++++++++++++++
 target/arm/internals.h        |   3 +
 target/arm/tcg/cpu64.c        |   1 +
 8 files changed, 142 insertions(+), 3 deletions(-)

-- 
2.34.1

On Mon, 6 Oct 2025 at 01:10, Gustavo Romero <gustavo.romero@linaro.org> wrote:
>
> This series adds support for all FEAT_MEC registers and cache
> instructions to the Arm64 max CPU.
>
> It includes the FEAT_MEC registers and cache maintenance instructions,
> but does not modify the translation regimes to support the MECIDs, so no
> encryption is supported yet. However, software stacks that rely on
> FEAT_MEC should work properly at this point.

I only had minor tweaks to suggests to comments in patch 1,
so I can take this via target-arm.next and make those changes
there to save you having to do another respin. (I've just
sent out a pullreq, so this will be for the next one, some
time next week.)

thanks
-- PMM

On Tue, 7 Oct 2025 at 15:35, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Mon, 6 Oct 2025 at 01:10, Gustavo Romero <gustavo.romero@linaro.org> wrote:
> >
> > This series adds support for all FEAT_MEC registers and cache
> > instructions to the Arm64 max CPU.
> >
> > It includes the FEAT_MEC registers and cache maintenance instructions,
> > but does not modify the translation regimes to support the MECIDs, so no
> > encryption is supported yet. However, software stacks that rely on
> > FEAT_MEC should work properly at this point.
>
> I only had minor tweaks to suggests to comments in patch 1,
> so I can take this via target-arm.next and make those changes
> there to save you having to do another respin. (I've just
> sent out a pullreq, so this will be for the next one, some
> time next week.)



Applied to target-arm.next, thanks.

-- PMM