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([186.215.59.111]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-339c4a48584sm8804881a91.23.2025.10.05.17.10.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Oct 2025 17:10:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759709450; x=1760314250; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l/93bmDUusvGPtBSWOQh6Rq5pqOuM8kQWpxAeUIhgpQ=; b=YNAL57wOuuLon9xddhZb0GfqxbcCplNkV7AdrDtiJaUTmNbFFyLOPCCAENgZlBlp26 u5iSVjfsZu8RSMRsGxQ0sZebMNGfsHa5yjL1xu+TgEjjjH5Hsp3LOyDoHWWRHs3qERSK woBU0/Mm/VfJMB1xlo1tF3jiKNIxTldwEVy0e4ZdF5LP1NwK2sQdsuHbgORr9n5EGkNc IGYm4OGUQ7145p2SSXuwSiyK+v1dyWVZbhMGugDC7yGCIOp7CGYPjNKzrUtEjZzp0Erl EUBWW7y+8106pE6HFsk8VRzYejXgjhQ0d1ewnH8I4dNJZNzN81fonLXaVcfvBRvQJoCv kd3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759709450; x=1760314250; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l/93bmDUusvGPtBSWOQh6Rq5pqOuM8kQWpxAeUIhgpQ=; b=XKlViRVUqP81A5YFq1HaXv9ZcZHAq+dMhAQTls9cnm3T+STqAYVVR9Bxc4ouiJ9Uf+ 8bo+6HHKoPTy5viHVzPN6YbWKL6TOC79P5CcW5hJ31G3zDv7CzpizLUi6J4QN4UMl4wM 0HeR9Y2nS9ODZ3RJPwPCgyirwaer5wk7ulvD7Ij9sZaL7n3rSmUBlUPo6m8f/3phZR+M iIf03oUbwE09RNoo8tsakP+y1JZGKRAx83U+ePqEI3RgAQuh11bmVlk5GUjTjCChXc6T luiVl0iBj+rOFuDYLptbO0MN56IfOhARrXoOD2hhVpH+Z1C8gyKG8YZsPNQZX+W0rD/w FvAw== X-Gm-Message-State: AOJu0YwxD2+50QSRmflDzdHKtpCC9TeRnBz3ZpILLeMLzbvk2kP0zJfx aIXWqgh1k19F8E/FBAJsXDhOE9HjzNHRNRqlXJZrweSI8kOhh2aSMCx+Kso8YXJK0Mu5U5WYKxG LeSoM X-Gm-Gg: ASbGncspVUoprT4I+WhOkTjdolGCYUwU4fCuJtlBTJgG+7Vqx996eDXUSh/9as6sCEA Syfd6FMYkk0VnzNTX9inUnkbjuTOgyFgcjH1NS8mX4WaWk6qXkEKvDGm2fuU0s8PUgzuahYc3pg rXrs7HV6qqM/v0G+IWKTyjU9hfvFmrnFpWBX7KXAYttEnlsk/Kwov4kxzgxFEqEmAUf3QIOml+3 uoDyEjGrrHiI2CwHVvcCVNCvYBjDDgo8yyLcnKhuq0S75a4Gi0V2+VMeXUOIA3sThJwQlMpWpO0 XqVMGGZkRv5XP4q3R5tiBMbNgjgnT+Sanw/v96S9CQACgTeYEOcLyiK5cLgIvuQDT+M3xTBTjOJ 0kQuN2DukOb2VS0/mePEhOrEjKXyFfHSViNCkT0YfeTdITUqpG3mU//N9HAivt1oueVQ= X-Google-Smtp-Source: AGHT+IEpDFex5TWeNxkxhX6gA+0YmZOzHqrcpG0SjJiQVPmhJxlkMJHxJ4VxFIr9rgfp7qlewoSgsA== X-Received: by 2002:a17:90b:3b41:b0:32d:dffc:7ad6 with SMTP id 98e67ed59e1d1-339c27b94demr12136386a91.33.1759709450337; Sun, 05 Oct 2025 17:10:50 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, peter.maydell@linaro.org Cc: alex.bennee@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v10 1/3] target/arm: Add a cpreg flag to indicate no trap in NV Date: Mon, 6 Oct 2025 00:10:16 +0000 Message-Id: <20251006001018.219756-2-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251006001018.219756-1-gustavo.romero@linaro.org> References: <20251006001018.219756-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=gustavo.romero@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759709529734116600 Content-Type: text/plain; charset="utf-8" Add a new flag, ARM_CP_NV_NO_TRAP, to indicate that a CP register, even though it has opc1 =3D=3D 4 or 5, does not trap when nested virtualization is enabled (FEAT_NV/FEAT_NV2). Signed-off-by: Gustavo Romero --- target/arm/cpregs.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 57fde5f57a..abee72c9bf 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -136,6 +136,7 @@ enum { * identically to the normal one, other than FGT trapping handling.) */ ARM_CP_ADD_TLBI_NXS =3D 1 << 21, + ARM_CP_NV_NO_TRAP =3D 1 << 22, }; =20 /* @@ -1158,10 +1159,14 @@ static inline bool arm_cpreg_traps_in_nv(const ARMC= PRegInfo *ri) * * In particular, note that the released sysreg XML defines that * the FEAT_MEC sysregs and instructions do not follow this FEAT_NV - * trapping rule, so we will need to add an ARM_CP_* flag to indicate - * "register does not trap on NV" to handle those if/when we implement - * FEAT_MEC. + * trapping rule, so a register flagged as ARM_CP_NV_NO_TRAP indicates + * the register does not trap on NV even if opc1 =3D=3D 4 or 5. */ + + if (ri->type & ARM_CP_NV_NO_TRAP) { + return false; + } + return ri->opc1 =3D=3D 4 || ri->opc1 =3D=3D 5; } =20 --=20 2.34.1 From nobody Fri Nov 14 22:21:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1759709551; cv=none; d=zohomail.com; s=zohoarc; b=SGlEyPCFR5IYrKC+JvAlfdpN8rUT9gEKvutjDFtJYHjHjRYVp19kIoJzly0OxNxZ7dLPNekC8byQHVRY8qEwdubh+G8ZqvzN7nSZgarucYN3gTmRFAVziB0kO8ffPNVc8TVrXci25PMLBat2idifYfjr+Vu5dQEg03bKzaWCAcg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759709551; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EVN+YmNfQibnEdc6QDAq+Bm5hOFHwnqw16eCPdTiIqo=; b=fE/+gHzwrJwgaKrQjBes4tcXiACsRWR/agPFKRDW3Rf6OwyKiGUGZG/Rk8/FLA/EbwjThShurndza6tWrhQ+sfvLbpmReb5u53tTTG6FK6xl8DpMNhGFq8eKyhPCZvHbiTPCcZYNdhieO8kIl0ATiuQHpoCh0pk04VpDy3UajFQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759709551933276.349041249773; Sun, 5 Oct 2025 17:12:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v5Yot-0000Fn-19; Sun, 05 Oct 2025 20:11:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v5Yoc-0000Cs-KU for qemu-devel@nongnu.org; Sun, 05 Oct 2025 20:11:03 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v5YoY-0004EP-B2 for qemu-devel@nongnu.org; Sun, 05 Oct 2025 20:10:57 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-2698e4795ebso41391165ad.0 for ; Sun, 05 Oct 2025 17:10:53 -0700 (PDT) Received: from gromero0.. ([186.215.59.111]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-339c4a48584sm8804881a91.23.2025.10.05.17.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Oct 2025 17:10:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759709453; x=1760314253; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EVN+YmNfQibnEdc6QDAq+Bm5hOFHwnqw16eCPdTiIqo=; b=a2+d+17+vaP1ZSAyh+6e8Wu9p++Luboo9YkLUayeZtkGEoC9beA5g0fDrMb4FUD1Q4 xKIWnFe/lZTqB99/Z6QvtHZNOYKQn6Dx9YFbxuP4cy06gAJObCUOXF/KjnNFyPGp+uuV e/MapSQEDiih0N9TFUROmv+rNT998SeDxfOPdQVc0U8Fw9weN2fpD5p/1I9eUDtjHmDV WdqL4NX3FEJYleox/eBwcrBSOzTan2LOGSP+jyERT4SYNjWOzoIXMIMBIq4wut7VHJOX W6Y49mxktd5mbH/dwaj1cp33sTAEUqq6aFIVsSffEeL51lHskN5s3U9HbvPvJreHokWW uSaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759709453; x=1760314253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EVN+YmNfQibnEdc6QDAq+Bm5hOFHwnqw16eCPdTiIqo=; b=IqL/Nu9Cw9PmO7sdgAEJaJWb2AGcYjNDsuOkHNDDyX5lmyTtKEXgjsT3cRtdvue7FX fzDEkat971rI8AHatN+kUXnVhypJrByakenTZcrqZnypg7uWIhPibDiFAgJzqhsjPD3G p+CC2Fx+3DDoWYM18UP/07lh0Hacf3nTQAp1z6ASf6x5TeVcvAi341SOl4acKetLZs7d 5Tmnt2MMIz1dj7JnjbE7Qo9K9nD1V6WjaU+KWPCIEozaGdr85vbDS+dEGhsZl4GR89km 7t8vutvckp17oaqAD+s+fjWVfzQpHE/tjohkQysj6RnHO5R4wNYJsW5PLbskbMXlfgRs 1STw== X-Gm-Message-State: AOJu0YyJVqYsE9oqsROpaAIzDekxlVaRoBJT1NmBuVCExjphqfr4/Gbz q9LESxhPfAvlVy7AZOmENNM0nH+dnt5j1s6xebT47Iaoa1MCrY+KoSvuocjKQ3e3wriR6F4eAcs P4O8D X-Gm-Gg: ASbGnct+fhe5WFe7lZY1+dV3NJHQMSDrs2WY8F3M6QnJtSOALiHd5wkGS3O8/QxAHG6 dj0M07Fkmp57tabi+CJqmBBJ1aiTVn2i7JALNdm0H99IOEOdkrhiWeWrApbWOWruUVUQ/MOVm3z gl6o9fNLLtBrMcJ8GNJgP9zi3oJc/BE/CFoFvZm0C58i/5dKgvoHo/QLoDx4tJt3Een9hgB/47N EVePyLKdJ9UwAeFGqDiQ1ltF54sPcXHhsG40z5j1xLqvdWR25hYGGVDvspvLme5A2uUoymNnSsq qBUreLBxnM7sACBzTgCnzEbDb00/KCHuLmnhe8+6wsmI7xr9BuYo6cGp8DYeMBUIKRE5UegKc6M 4tLrNY4dMx0KEVke0xnrjRLmc7h/Z55aws3t7IDSXTSn581l9c/7z4TwUAYSAx3lRtLE= X-Google-Smtp-Source: AGHT+IGeEEl3TCsZdatHpH3OSHlnNhLIIBFeYyLkcKJvD+1ZWJetGFCkYmIN4kcHk8MuzU+tTE5uFQ== X-Received: by 2002:a17:903:198b:b0:269:a4ed:13c9 with SMTP id d9443c01a7336-28e9a693f79mr97822355ad.30.1759709452742; Sun, 05 Oct 2025 17:10:52 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, peter.maydell@linaro.org Cc: alex.bennee@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v10 2/3] target/arm: Implement FEAT_MEC registers Date: Mon, 6 Oct 2025 00:10:17 +0000 Message-Id: <20251006001018.219756-3-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251006001018.219756-1-gustavo.romero@linaro.org> References: <20251006001018.219756-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=gustavo.romero@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759709559716116600 Content-Type: text/plain; charset="utf-8" Add all FEAT_MEC registers. Enable access to the registers via the SCTLR2 and TCR2 control bits. Add the two new cache management instructions, which are nops in QEMU because we do not model caches. Message-ID: <20250711140828.1714666-3-gustavo.romero@linaro.org> Reviewed-by: Richard Henderson [rth: Squash 3 patches to add all registers at once.] Signed-off-by: Richard Henderson Signed-off-by: Gustavo Romero Reviewed-by: Peter Maydell --- target/arm/cpu-features.h | 5 ++ target/arm/cpu.c | 3 ++ target/arm/cpu.h | 10 ++++ target/arm/helper.c | 109 ++++++++++++++++++++++++++++++++++++++ target/arm/internals.h | 3 ++ 5 files changed, 130 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 602f6a88e5..206c807530 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1344,6 +1344,11 @@ static inline bool isar_feature_aa64_sctlr2(const AR= MISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; } =20 +static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 30e29fd315..baab2ff9b6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -641,6 +641,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_sctlr2, cpu)) { env->cp15.scr_el3 |=3D SCR_SCTLR2EN; } + if (cpu_isar_feature(aa64_mec, cpu)) { + env->cp15.scr_el3 |=3D SCR_MECEN; + } } =20 if (target_el =3D=3D 2) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2b9585dc80..6b9613a5d3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -576,6 +576,15 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + /* MEC registers */ + uint64_t mecid_p0_el2; + uint64_t mecid_a0_el2; + uint64_t mecid_p1_el2; + uint64_t mecid_a1_el2; + uint64_t mecid_rl_a_el3; + uint64_t vmecid_p_el2; + uint64_t vmecid_a_el2; } cp15; =20 struct { @@ -1721,6 +1730,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TCR2EN (1ULL << 43) #define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) +#define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) =20 /* Return the current FPSCR value. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index aa730addf2..c2c450617d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -770,6 +770,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D SCR_SCTLR2EN; } + if (cpu_isar_feature(aa64_mec, cpu)) { + valid_mask |=3D SCR_MECEN; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -4994,6 +4997,96 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, }; =20 +static CPAccessResult mecid_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 2) { + if (arm_security_space(env) !=3D ARMSS_Realm) { + return CP_ACCESS_UNDEFINED; + } + + if (!(env->cp15.scr_el3 & SCR_MECEN)) { + return CP_ACCESS_TRAP_EL3; + } + } + + return CP_ACCESS_OK; +} + +static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value =3D extract64(value, 0, MECID_WIDTH); + raw_write(env, ri, value); +} + +static CPAccessResult cipae_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + switch (arm_security_space(env)) { + case ARMSS_Root: /* EL3 */ + case ARMSS_Realm: /* Realm EL2 */ + return CP_ACCESS_OK; + default: + return CP_ACCESS_UNDEFINED; + } +} + +static const ARMCPRegInfo mec_reginfo[] =3D { + { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, + .access =3D PL2_R, .type =3D ARM_CP_CONST | ARM_CP_NV_NO_TRAP, + .resetvalue =3D MECID_WIDTH - 1 }, + { .name =3D "MECID_P0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .type =3D ARM_CP_NV_NO_TRAP, + .accessfn =3D mecid_access, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p0_el2) }, + { .name =3D "MECID_A0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .type =3D ARM_CP_NV_NO_TRAP, + .accessfn =3D mecid_access, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a0_el2) }, + { .name =3D "MECID_P1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .type =3D ARM_CP_NV_NO_TRAP, + .accessfn =3D mecid_access, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p1_el2) }, + { .name =3D "MECID_A1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .type =3D ARM_CP_NV_NO_TRAP, + .accessfn =3D mecid_access, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, + { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, + .access =3D PL3_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, + { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .type =3D ARM_CP_NV_NO_TRAP, + .accessfn =3D mecid_access, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_p_el2) }, + { .name =3D "VMECID_A_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .type =3D ARM_CP_NV_NO_TRAP, + .accessfn =3D mecid_access, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, + { .name =3D "DC_CIPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NOP | ARM_CP_NV_NO_TRAP, + .accessfn =3D cipae_access }, +}; + +static const ARMCPRegInfo mec_mte_reginfo[] =3D { + { .name =3D "DC_CIGDPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NOP | ARM_CP_NV_NO_TRAP, + .accessfn =3D cipae_access }, +}; + #ifndef CONFIG_USER_ONLY /* * We don't know until after realize whether there's a GICv3 @@ -5836,6 +5929,9 @@ static void sctlr2_el2_write(CPUARMState *env, const = ARMCPRegInfo *ri, { uint64_t valid_mask =3D 0; =20 + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -5845,6 +5941,9 @@ static void sctlr2_el3_write(CPUARMState *env, const = ARMCPRegInfo *ri, { uint64_t valid_mask =3D 0; =20 + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -5907,6 +6006,9 @@ static void tcr2_el2_write(CPUARMState *env, const AR= MCPRegInfo *ri, { uint64_t valid_mask =3D 0; =20 + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D TCR2_AMEC0 | TCR2_AMEC1; + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -7159,6 +7261,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, tcr2_reginfo); } =20 + if (cpu_isar_feature(aa64_mec, cpu)) { + define_arm_cp_regs(cpu, mec_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mec_mte_reginfo); + } + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 1d958dbf68..6bd9f8310c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -2007,4 +2007,7 @@ bool arm_pan_enabled(CPUARMState *env); /* Compare uint64_t for qsort and bsearch. */ int compare_u64(const void *a, const void *b); =20 +/* Used in FEAT_MEC to set the MECIDWidthm1 field in the MECIDR_EL2 regist= er. */ +#define MECID_WIDTH 16 + #endif --=20 2.34.1 From nobody Fri Nov 14 22:21:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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The FEAT_MEC is an extension to FEAT_RME that implements multiple Memory Encryption Contexts (MEC) so the memory in a realm can be encrypted and accessing it from the wrong encryption context is not possible. An encryption context allow the selection of a memory encryption engine. At this point, no real memory encryption is supported, but software stacks that rely on FEAT_MEC should work properly. Reviewed-by: Richard Henderson Message-ID: <20250711140828.1714666-7-gustavo.romero@linaro.org> Signed-off-by: Richard Henderson Signed-off-by: Gustavo Romero Reviewed-by: Peter Maydell --- docs/system/arm/emulation.rst | 3 +++ target/arm/tcg/cpu64.c | 1 + 2 files changed, 4 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 6b04c96c8c..0876a232c6 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -92,6 +92,9 @@ the following architecture extensions: - FEAT_LSE2 (Large System Extensions v2) - FEAT_LSE128 (128-bit Atomics) - FEAT_LVA (Large Virtual Address space) +- FEAT_MEC (Memory Encryption Contexts) + + * This is a register-only implementation without encryption. - FEAT_MixedEnd (Mixed-endian support) - FEAT_MixedEndEL0 (Mixed-endian support at EL0) - FEAT_MOPS (Standardization of memory operations) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index abef6a246e..3661f3ec83 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1252,6 +1252,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D GET_IDREG(isar, ID_AA64MMFR3); t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 --=20 2.34.1