[v1] hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5

[PATCH 0/3] hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5

Clément Chigot posted 3 patches 1 month, 2 weeks ago

Diff against v1
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250930115718.437100-1-chigot@adacore.com

Maintainers: Alistair Francis <alistair@alistair23.me>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Peter Maydell <peter.maydell@linaro.org>

hw/arm/xlnx-zynqmp.c         | 103 +++++++++++++++++++++++++++++++----
include/hw/arm/xlnx-zynqmp.h |   5 ++
2 files changed, 98 insertions(+), 10 deletions(-)

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[PATCH 0/3] hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5

Posted by Clément Chigot 1 month, 2 weeks ago

The first two patches are minor improvements before the core third
patch.

This was initially a single patch split as per review comments (see [1])

[1] https://lists.gnu.org/archive/html/qemu-devel/2025-09/msg05899.html

Clément Chigot (2):
  hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header
  hw/arm/xlnx-zynqmp: introduce helper to compute RPU number

Frederic Konrad (1):
  hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5

 hw/arm/xlnx-zynqmp.c         | 103 +++++++++++++++++++++++++++++++----
 include/hw/arm/xlnx-zynqmp.h |   5 ++
 2 files changed, 98 insertions(+), 10 deletions(-)

-- 
2.34.1

Re: [PATCH 0/3] hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5

Posted by Peter Maydell 1 month, 1 week ago

On Tue, 30 Sept 2025 at 12:57, Clément Chigot <chigot@adacore.com> wrote:
>
> The first two patches are minor improvements before the core third
> patch.
>
> This was initially a single patch split as per review comments (see [1])
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2025-09/msg05899.html
>
> Clément Chigot (2):
>   hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header
>   hw/arm/xlnx-zynqmp: introduce helper to compute RPU number
>
> Frederic Konrad (1):
>   hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5



Applied to target-arm.next, thanks.

-- PMM