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Add XLXN_ZYNQMP prefix as it's now public. Signed-off-by: Cl=C3=A9ment Chigot Reviewed-by: Edgar E. Iglesias --- hw/arm/xlnx-zynqmp.c | 11 +++++------ include/hw/arm/xlnx-zynqmp.h | 1 + 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index ec96a46eec..d7adc070f8 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -26,8 +26,6 @@ #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" =20 -#define GIC_NUM_SPI_INTR 160 - #define ARM_PHYS_TIMER_PPI 30 #define ARM_VIRT_TIMER_PPI 27 #define ARM_HYP_TIMER_PPI 26 @@ -206,7 +204,7 @@ static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_region= s[] =3D { =20 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) { - return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; + return XLNX_ZYNQMP_GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_inde= x; } =20 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, @@ -454,7 +452,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) int num_apus =3D MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); const char *boot_cpu =3D s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; ram_addr_t ddr_low_size, ddr_high_size; - qemu_irq gic_spi[GIC_NUM_SPI_INTR]; + qemu_irq gic_spi[XLNX_ZYNQMP_GIC_NUM_SPI_INTR]; Error *err =3D NULL; =20 ram_size =3D memory_region_size(s->ddr_ram); @@ -502,7 +500,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) g_free(ocm_name); } =20 - qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32= ); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", + XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secur= e); @@ -613,7 +612,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) return; } =20 - for (i =3D 0; i < GIC_NUM_SPI_INTR; i++) { + for (i =3D 0; i < XLNX_ZYNQMP_GIC_NUM_SPI_INTR; i++) { gic_spi[i] =3D qdev_get_gpio_in(DEVICE(&s->gic), i); } =20 diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c137ac59e8..6a407c2962 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -67,6 +67,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 =20 #define XLNX_ZYNQMP_GIC_REGIONS 6 +#define XLNX_ZYNQMP_GIC_NUM_SPI_INTR 160 =20 /* * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k off= sets --=20 2.34.1 From nobody Fri Nov 14 23:30:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=adacore.com ARC-Seal: i=1; a=rsa-sha256; t=1759233531; cv=none; d=zohomail.com; s=zohoarc; b=SwuPvmDkSJicKSg17Q1Aag3pBjwBmCYx0eVytMUgDopjlNqQ/ZVKmtTyXYYDSTK545kc3NursELEEhrX2vHrxnbHRb0RCDn3FJELyYdt0uQiPK5bRqtzTNwenpN4PnlMklHqD2lXP0sOGo7E++Hm+6Su38C1Jlx/qP8ojpr88dU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759233531; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OBxVX8/NLsjWLzZ2+6eEqS1I+f7z9kN4uZXMIhC5fJE=; b=NHiUeg+ufu6lPlnGEY8DxmsEnY+45fBadfuZBCveOn2KSHtTXoACU5jg8IQ4lib8dguSoGlqsQE+3bcwZJHdX49MDwWF5dFUukpkKlgUg2IAlhoiuO6h+XJtLsO6bjoav53p0mqaGS8H6SDeWDfhw2g7O21YxYvOY8rhw8v1xa0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759233531813543.9896432833939; Tue, 30 Sep 2025 04:58:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3YzH-0000VZ-1O; Tue, 30 Sep 2025 07:57:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3Yz9-0000Ud-Tw for qemu-devel@nongnu.org; Tue, 30 Sep 2025 07:57:37 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v3Yz2-0001ca-36 for qemu-devel@nongnu.org; Tue, 30 Sep 2025 07:57:35 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-3ee13baf2e1so4589854f8f.3 for ; Tue, 30 Sep 2025 04:57:26 -0700 (PDT) Received: from chigot-Dell.telnowedge.local (lmontsouris-659-1-24-67.w81-250.abo.wanadoo.fr. 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Signed-off-by: Cl=C3=A9ment Chigot Reviewed-by: Edgar E. Iglesias --- hw/arm/xlnx-zynqmp.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index d7adc070f8..3d8c46986e 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -207,14 +207,23 @@ static inline int arm_gic_ppi_index(int cpu_nr, int p= pi_index) return XLNX_ZYNQMP_GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_inde= x; } =20 +static unsigned int xlnx_zynqmp_get_rpu_number(MachineState *ms) +{ + /* + * RPUs will be created only if "-smp" is higher than the maximum + * of APUs. Round it up to 0 to avoid dealing with negative values. + */ + return MAX(0, MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), + XLNX_ZYNQMP_NUM_RPU_CPUS)); +} + static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, const char *boot_cpu, Error **errp) { int i; - int num_rpus =3D MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), - XLNX_ZYNQMP_NUM_RPU_CPUS); + int num_rpus =3D xlnx_zynqmp_get_rpu_number(ms); =20 - if (num_rpus <=3D 0) { + if (!num_rpus) { /* Don't create rpu-cluster object if there's nothing to put in it= */ return; } --=20 2.34.1 From nobody Fri Nov 14 23:30:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=adacore.com ARC-Seal: i=1; a=rsa-sha256; t=1759233543; cv=none; d=zohomail.com; s=zohoarc; b=PkFgxWE1ZY2EUqdPUI5N71RVQpbZD1e6JYu4ZBNM9PJuY7wr8fS0Tn4Ht8+EP9RjKgBGseU7Yhn7+Bz0SP52liUSkmIf/ivkkxcJ8QzWpds00fXTiDYq1qNsbPZlmLpFXA0ZVQRQVw96RHV7fzFOWIGwlyTDeRfx6HufcZ+6w5A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759233543; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OQ/Lu1tU0Qj8neKJhLVxbk1XtF5ADWgaXLTN2vtV7aE=; b=PIYVdZIXuMWQiHDCt/zec0+i7HMU/rGcmSAgY9QQ/IcfWpFgoJC0/RT3t91C9S3Vrk80STkOOjhfMUNNwseAFDYewkO5eJT1TRG7TYHF/WZ/q5t6/UKeEWITJD7hd6yFVCQj7X6ByJLyEbUPs4Ud7V9+IlW79S9Dc6K3jS0DPmQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759233543295550.0963554831075; Tue, 30 Sep 2025 04:59:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3YzL-0000XN-2A; Tue, 30 Sep 2025 07:57:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3YzJ-0000W0-2o for qemu-devel@nongnu.org; Tue, 30 Sep 2025 07:57:45 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v3Yz6-0001cl-CG for qemu-devel@nongnu.org; Tue, 30 Sep 2025 07:57:44 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-46e34052bb7so58865955e9.2 for ; Tue, 30 Sep 2025 04:57:25 -0700 (PDT) Received: from chigot-Dell.telnowedge.local (lmontsouris-659-1-24-67.w81-250.abo.wanadoo.fr. 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Signed-off-by: Cl=C3=A9ment Chigot Acked-by: Edgar E. Iglesias --- hw/arm/xlnx-zynqmp.c | 77 +++++++++++++++++++++++++++++++++++- include/hw/arm/xlnx-zynqmp.h | 4 ++ 2 files changed, 80 insertions(+), 1 deletion(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 3d8c46986e..ffed6e5126 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -384,6 +384,7 @@ static void xlnx_zynqmp_init(Object *obj) XlnxZynqMPState *s =3D XLNX_ZYNQMP(obj); int i; int num_apus =3D MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); + int num_rpus =3D xlnx_zynqmp_get_rpu_number(ms); =20 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, TYPE_CPU_CLUSTER); @@ -397,6 +398,12 @@ static void xlnx_zynqmp_init(Object *obj) =20 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); =20 + if (num_rpus) { + /* Do not create the rpu_gic if we don't have rpus */ + object_initialize_child(obj, "rpu_gic", &s->rpu_gic, + gic_class_name()); + } + for (i =3D 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GE= M); object_initialize_child(obj, "gem-irq-orgate[*]", @@ -446,6 +453,15 @@ static void xlnx_zynqmp_init(Object *obj) object_initialize_child(obj, "qspi-irq-orgate", &s->qspi_irq_orgate, TYPE_OR_IRQ); =20 + if (num_rpus) { + for (i =3D 0; i < ARRAY_SIZE(s->splitter); i++) { + g_autofree char *name =3D g_strdup_printf("irq-splitter%d", i); + object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT= _IRQ); + } + } + + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_USB; i++) { object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3); } @@ -459,6 +475,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) uint8_t i; uint64_t ram_size; int num_apus =3D MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); + int num_rpus =3D xlnx_zynqmp_get_rpu_number(ms); const char *boot_cpu =3D s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; ram_addr_t ddr_low_size, ddr_high_size; qemu_irq gic_spi[XLNX_ZYNQMP_GIC_NUM_SPI_INTR]; @@ -517,6 +534,14 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", s->virt); =20 + if (num_rpus) { + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-irq", + XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32); + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "revision", 1); + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-cpu", num_rpus); + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "first-cpu-index", 4); + } + qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); =20 /* Realize APUs before realizing the GIC. KVM requires this. */ @@ -616,13 +641,63 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) return; } =20 + if (num_rpus) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->rpu_gic), errp)) { + return; + } + + for (i =3D 0; i < num_rpus; i++) { + qemu_irq irq; + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), i + 1, + GIC_BASE_ADDR + i * 0x1000); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_FIQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus *= 2, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_VIRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus *= 3, + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), + ARM_CPU_VFIQ)); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI= )); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_PHYS, irq= ); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI= )); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_VIRT, irq= ); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)= ); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_HYP, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->rpu_gic), + arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)= ); + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_SEC, irq); + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), 0, GIC_BASE_ADDR); + } + if (!s->boot_cpu_ptr) { error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); return; } =20 for (i =3D 0; i < XLNX_ZYNQMP_GIC_NUM_SPI_INTR; i++) { - gic_spi[i] =3D qdev_get_gpio_in(DEVICE(&s->gic), i); + if (num_rpus) { + DeviceState *splitter =3D DEVICE(&s->splitter[i]); + qdev_prop_set_uint16(splitter, "num-lines", 2); + qdev_realize(splitter, NULL, &error_abort); + gic_spi[i] =3D qdev_get_gpio_in(splitter, 0); + qdev_connect_gpio_out(splitter, 0, + qdev_get_gpio_in(DEVICE(&s->gic), i)); + qdev_connect_gpio_out(splitter, 1, + qdev_get_gpio_in(DEVICE(&s->rpu_gic), i)= ); + } else { + gic_spi[i] =3D qdev_get_gpio_in(DEVICE(&s->gic), i); + } } =20 for (i =3D 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6a407c2962..a3117bd6c5 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -42,6 +42,7 @@ #include "hw/misc/xlnx-zynqmp-crf.h" #include "hw/timer/cadence_ttc.h" #include "hw/usb/hcd-dwc3.h" +#include "hw/core/split-irq.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -106,6 +107,9 @@ struct XlnxZynqMPState { GICState gic; MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; =20 + GICState rpu_gic; + SplitIRQ splitter[XLNX_ZYNQMP_GIC_NUM_SPI_INTR]; + MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; =20 MemoryRegion *ddr_ram; --=20 2.34.1