target/riscv: do not use translator_ldl in opcode_at

[PATCH] target/riscv: do not use translator_ldl in opcode_at

Posted by Vladimir Isaev 3 months ago

opcode_at is used only in semihosting checks to match opcodes with expected pattern.

This is not a translator and if we got following assert if page is not in TLB:
qemu-system-riscv64: ../accel/tcg/translator.c:363: record_save: Assertion `offset == db->record_start + db->record_len' failed.

Fixes: 1f9c4462334f ("target/riscv: Use translator_ld* for everything")
Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
---
 target/riscv/translate.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b1e41cdbf1f6..980a67ea855e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -25,6 +25,7 @@
 #include "exec/helper-gen.h"
 
 #include "exec/translator.h"
+#include "exec/cpu_ldst.h"
 #include "exec/log.h"
 #include "semihosting/semihost.h"
 
@@ -1143,7 +1144,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
     CPUState *cpu = ctx->cs;
     CPURISCVState *env = cpu_env(cpu);
 
-    return translator_ldl(env, &ctx->base, pc);
+    return cpu_ldl_code(env, pc);
 }
 
 #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE)
-- 
2.50.1

Re: [PATCH] target/riscv: do not use translator_ldl in opcode_at

Posted by Michael Tokarev 1 month, 1 week ago

On 8/15/25 17:06, Vladimir Isaev wrote:
> opcode_at is used only in semihosting checks to match opcodes with expected pattern.
> 
> This is not a translator and if we got following assert if page is not in TLB:
> qemu-system-riscv64: ../accel/tcg/translator.c:363: record_save: Assertion `offset == db->record_start + db->record_len' failed.
> 
> Fixes: 1f9c4462334f ("target/riscv: Use translator_ld* for everything")
> Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>

This seems like a qemu-stable material (for 10.0.x and 10.1.x series).
Please let me know if it is not.

Thanks,

/mjt

Re: [PATCH] target/riscv: do not use translator_ldl in opcode_at

Posted by Alistair Francis 1 month, 2 weeks ago

On Sat, Aug 16, 2025 at 12:08 AM Vladimir Isaev
<vladimir.isaev@syntacore.com> wrote:
>
> opcode_at is used only in semihosting checks to match opcodes with expected pattern.
>
> This is not a translator and if we got following assert if page is not in TLB:
> qemu-system-riscv64: ../accel/tcg/translator.c:363: record_save: Assertion `offset == db->record_start + db->record_len' failed.
>
> Fixes: 1f9c4462334f ("target/riscv: Use translator_ld* for everything")
> Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/translate.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index b1e41cdbf1f6..980a67ea855e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -25,6 +25,7 @@
>  #include "exec/helper-gen.h"
>
>  #include "exec/translator.h"
> +#include "exec/cpu_ldst.h"
>  #include "exec/log.h"
>  #include "semihosting/semihost.h"
>
> @@ -1143,7 +1144,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>      CPUState *cpu = ctx->cs;
>      CPURISCVState *env = cpu_env(cpu);
>
> -    return translator_ldl(env, &ctx->base, pc);
> +    return cpu_ldl_code(env, pc);
>  }
>
>  #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE)
> --
> 2.50.1
>
>

Re: [PATCH] target/riscv: do not use translator_ldl in opcode_at

Posted by Richard Henderson 2 months, 2 weeks ago

On 8/16/25 00:06, Vladimir Isaev wrote:
> opcode_at is used only in semihosting checks to match opcodes with expected pattern.
> 
> This is not a translator and if we got following assert if page is not in TLB:
> qemu-system-riscv64: ../accel/tcg/translator.c:363: record_save: Assertion `offset == db->record_start + db->record_len' failed.
> 
> Fixes: 1f9c4462334f ("target/riscv: Use translator_ld* for everything")
> Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
> ---
>   target/riscv/translate.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index b1e41cdbf1f6..980a67ea855e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -25,6 +25,7 @@
>   #include "exec/helper-gen.h"
>   
>   #include "exec/translator.h"
> +#include "exec/cpu_ldst.h"
>   #include "exec/log.h"
>   #include "semihosting/semihost.h"
>   
> @@ -1143,7 +1144,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>       CPUState *cpu = ctx->cs;
>       CPURISCVState *env = cpu_env(cpu);
>   
> -    return translator_ldl(env, &ctx->base, pc);
> +    return cpu_ldl_code(env, pc);
>   }
>   
>   #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~