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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.249.69.228; envelope-from=vladimir.isaev@syntacore.com; helo=m.syntacore.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) X-ZM-MESSAGEID: 1755266882227124100 Content-Type: text/plain; charset="utf-8" opcode_at is used only in semihosting checks to match opcodes with expected= pattern. This is not a translator and if we got following assert if page is not in T= LB: qemu-system-riscv64: ../accel/tcg/translator.c:363: record_save: Assertion = `offset =3D=3D db->record_start + db->record_len' failed. Fixes: 1f9c4462334f ("target/riscv: Use translator_ld* for everything") Signed-off-by: Vladimir Isaev Reviewed-by: Richard Henderson --- target/riscv/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b1e41cdbf1f6..980a67ea855e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -25,6 +25,7 @@ #include "exec/helper-gen.h" =20 #include "exec/translator.h" +#include "exec/cpu_ldst.h" #include "exec/log.h" #include "semihosting/semihost.h" =20 @@ -1143,7 +1144,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) CPUState *cpu =3D ctx->cs; CPURISCVState *env =3D cpu_env(cpu); =20 - return translator_ldl(env, &ctx->base, pc); + return cpu_ldl_code(env, pc); } =20 #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE) --=20 2.50.1