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  3. [PATCH v2 0/3] Fix some more RVV source overlap issues
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[PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions

Max Chou posted 3 patches 4 months, 3 weeks ago
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
[PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions
Posted by Max Chou 4 months, 3 weeks ago 
From: Anton Blanchard <antonb@tenstorrent.com>

Handle the overlap of source registers with different EEWs.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ec34d0d8c47..ac6f1d04c6d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3293,6 +3293,7 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) &&
            vext_check_reduction(s, a->rs2);
 }
 
@@ -3309,7 +3310,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
 static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_check(s, a) && (s->sew < MO_64) &&
-           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
+           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
+           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1, a->vm);
 }
 
 GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
-- 
2.43.0
Re: [PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions
Posted by Nutty Liu 4 months, 2 weeks ago 
On 6/27/2025 9:20 PM, Max Chou wrote:
> From: Anton Blanchard <antonb@tenstorrent.com>
>
> Handle the overlap of source registers with different EEWs.

Above description is the same as [patch v2 1/3].
They are different functions.
Maybe need to add some different description.

Otherwise,
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>

Thanks,
Nutty

>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index ec34d0d8c47..ac6f1d04c6d 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3293,6 +3293,7 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) &&
>              vext_check_reduction(s, a->rs2);
>   }
>   
> @@ -3309,7 +3310,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
>   static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
>   {
>       return reduction_check(s, a) && (s->sew < MO_64) &&
> -           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
> +           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1, a->vm);
>   }
>   
>   GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
Re: [PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions
Posted by Max Chou 4 months, 1 week ago 
Hi Nutty,

Thanks for the suggestion.
I'll provide a new version including the new description and a fix about
another EEWs issue.

Thanks,
Max


On Tue, Jul 1, 2025 at 2:43 PM Nutty Liu <liujingqi@lanxincomputing.com>
wrote:

> On 6/27/2025 9:20 PM, Max Chou wrote:
> > From: Anton Blanchard <antonb@tenstorrent.com>
> >
> > Handle the overlap of source registers with different EEWs.
>
> Above description is the same as [patch v2 1/3].
> They are different functions.
> Maybe need to add some different description.
>
> Otherwise,
> Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
>
> Thanks,
> Nutty
>
> >
> > Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> > Signed-off-by: Max Chou <max.chou@sifive.com>
> > ---
> >   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
> >   1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> > index ec34d0d8c47..ac6f1d04c6d 100644
> > --- a/target/riscv/insn_trans/trans_rvv.c.inc
> > +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> > @@ -3293,6 +3293,7 @@ static bool reduction_check(DisasContext *s,
> arg_rmrr *a)
> >   {
> >       return require_rvv(s) &&
> >              vext_check_isa_ill(s) &&
> > +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew,
> a->vm) &&
> >              vext_check_reduction(s, a->rs2);
> >   }
> >
> > @@ -3309,7 +3310,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
> >   static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
> >   {
> >       return reduction_check(s, a) && (s->sew < MO_64) &&
> > -           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
> > +           ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
> > +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1,
> a->vm);
> >   }
> >
> >   GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
>

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