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Signed-off-by: Anton Blanchard Signed-off-by: Max Chou Reviewed-by: Nutty Liu --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index ec34d0d8c47..ac6f1d04c6d 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3293,6 +3293,7 @@ static bool reduction_check(DisasContext *s, arg_rmrr= *a) { return require_rvv(s) && vext_check_isa_ill(s) && + vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) = && vext_check_reduction(s, a->rs2); } =20 @@ -3309,7 +3310,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check) static bool reduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_check(s, a) && (s->sew < MO_64) && - ((s->sew + 1) <=3D (s->cfg_ptr->elen >> 4)); + ((s->sew + 1) <=3D (s->cfg_ptr->elen >> 4)) && + vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1, a->= vm); } =20 GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) --=20 2.43.0