ntroduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.

The whole topology of irqchips in LoongArch machines looks like this if
AVECINTC is supported:

  +-----+     +-----------------------+     +-------+
  | IPI | --> |        CPUINTC        | <-- | Timer |
  +-----+     +-----------------------+     +-------+
               ^          ^          ^
               |          |          |
        +---------+ +----------+ +---------+     +-------+
        | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
        +---------+ +----------+ +---------+     +-------+
             ^            ^
             |            |
        +---------+  +---------+
        | PCH-PIC |  | PCH-MSI |
        +---------+  +---------+
          ^     ^           ^
          |     |           |
  +---------+ +---------+ +---------+
  | Devices | | PCH-LPC | | Devices |
  +---------+ +---------+ +---------+
                   ^
                   |
              +---------+
              | Devices |
              +---------+

We can see more about AVECINTC on linux driver code[1]
and loongarch msg interrupts on volI 6.2 Message-Interrupts

Tested the code using the virion-net NIC the start scripts is kernel.sh at[3]

[1]: https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loongarch-avec.c
[2]: https://github.com/loongson/LoongArch-Documentation/releases/download/2023.04.20/LoongArch-Vol1-v1.10-EN.pdf
[3]: https://github.com/gaosong715/qemu/releases/download/pull-loongarch-20250514/kernel.sh

v2:
  1: Use one irqline for avec parent_irq;
  2; Correct avec memroy area;
  3; Pch-msi not connecet to avec when avec is enabled and drop patch 7;
  4: Add misc_feature and misc_status for misc features an misc
     fetures status
  5: Define CSR_ESTAT and CSR_ECFG bit15 for msg interupt. clean patch9.
  6: Fix test demsg error.

Thanks.
Song Gao

Song Gao (9):
  hw/loongarch: move some machine define to virt.h
  loongarch: add virt feature avecintc support
  loongarch: add a advance interrupt controller device
  target/loongarch: add msg interrupt CSR registers
  hw/loongarch: AVEC controller add a MemoryRegion
  hw/loongarch: Implement avec controller imput and output pins
  hw/loongarch: Implement avec set_irq
  target/loongarch: loongarch CPU supoort avec irqs
  target/loongarch: do_interrupt support msg interrupt

 hw/intc/Kconfig                  |   3 +
 hw/intc/loongarch_avec.c         | 143 +++++++++++++++++++++++++++++++
 hw/intc/meson.build              |   1 +
 hw/loongarch/Kconfig             |   1 +
 hw/loongarch/virt.c              |  89 ++++++++++++++++++-
 include/hw/intc/loongarch_avec.h |  36 ++++++++
 include/hw/loongarch/virt.h      |  36 ++++++++
 include/hw/pci-host/ls7a.h       |   2 +
 target/loongarch/cpu-csr.h       |   6 +-
 target/loongarch/cpu.c           |  17 ++++
 target/loongarch/cpu.h           |  34 +++-----
 target/loongarch/machine.c       |   5 ++
 12 files changed, 346 insertions(+), 27 deletions(-)
 create mode 100644 hw/intc/loongarch_avec.c
 create mode 100644 include/hw/intc/loongarch_avec.h

-- 
2.34.1