From nobody Sat Nov 15 14:54:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750302239901218.71265527662604; Wed, 18 Jun 2025 20:03:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YQ-00073I-4Q; Wed, 18 Jun 2025 23:03:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS5YK-00072T-7m for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:01 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YG-00069L-J0 for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:02:59 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxqmrWfVNosI4ZAQ--.17718S3; Thu, 19 Jun 2025 11:02:46 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxrhu7fVNoIXkgAQ--.48014S3; Thu, 19 Jun 2025 11:02:38 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v2 1/9] hw/loongarch: move some machine define to virt.h Date: Thu, 19 Jun 2025 10:39:36 +0800 Message-Id: <20250619023944.1278716-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250619023944.1278716-1-gaosong@loongson.cn> References: <20250619023944.1278716-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxrhu7fVNoIXkgAQ--.48014S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750302243286116600 Content-Type: text/plain; charset="utf-8" move som machine define to virt.h and define avec feature and status bit. Use the IOCSRF_AVEC bit for avdance interrupt controller drivers avecintc_enable[1] and set the default value of the MISC_FUNC_REG bit IOCSR= M_AVEC_EN. and set the default value of the MISC_FUNC_REG bit IOCSRM_AVEC_EN. [1]:https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loong= arch-avec.c Signed-off-by: Song Gao --- hw/loongarch/virt.c | 4 ++++ include/hw/loongarch/virt.h | 20 ++++++++++++++++++++ target/loongarch/cpu.h | 21 --------------------- 3 files changed, 24 insertions(+), 21 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1b504047db..90d4643721 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -548,6 +548,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, break; case FEATURE_REG: ret =3D BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); + /*TODO: check bit IOCSRF_AVEC with virt_is_avec_enabled */ + ret |=3D BIT(IOCSRF_AVEC); if (kvm_enabled()) { ret |=3D BIT(IOCSRF_VM); } @@ -573,6 +575,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { ret |=3D BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); } + /* enable avec default */ + ret |=3D BIT_ULL(IOCSRM_AVEC_EN); break; default: g_assert_not_reached(); diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 2b7d19953f..671b47a986 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -13,6 +13,26 @@ #include "hw/block/flash.h" #include "hw/loongarch/boot.h" =20 +#define IOCSRF_TEMP 0 +#define IOCSRF_NODECNT 1 +#define IOCSRF_MSI 2 +#define IOCSRF_EXTIOI 3 +#define IOCSRF_CSRIPI 4 +#define IOCSRF_FREQCSR 5 +#define IOCSRF_FREQSCALE 6 +#define IOCSRF_DVFSV1 7 +#define IOCSRF_GMOD 9 +#define IOCSRF_VM 11 +#define IOCSRF_AVEC 15 + +#define VERSION_REG 0x0 +#define FEATURE_REG 0x8 +#define VENDOR_REG 0x10 +#define CPUNAME_REG 0x20 +#define MISC_FUNC_REG 0x420 +#define IOCSRM_EXTIOI_EN 48 +#define IOCSRM_EXTIOI_INT_ENCODE 49 +#define IOCSRM_AVEC_EN 51 #define LOONGARCH_MAX_CPUS 256 =20 #define VIRT_FWCFG_BASE 0x1e020000UL diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 262bf87f7b..1169768632 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -21,27 +21,6 @@ #include "cpu-csr.h" #include "cpu-qom.h" =20 -#define IOCSRF_TEMP 0 -#define IOCSRF_NODECNT 1 -#define IOCSRF_MSI 2 -#define IOCSRF_EXTIOI 3 -#define IOCSRF_CSRIPI 4 -#define IOCSRF_FREQCSR 5 -#define IOCSRF_FREQSCALE 6 -#define IOCSRF_DVFSV1 7 -#define IOCSRF_GMOD 9 -#define IOCSRF_VM 11 - -#define VERSION_REG 0x0 -#define FEATURE_REG 0x8 -#define VENDOR_REG 0x10 -#define CPUNAME_REG 0x20 -#define MISC_FUNC_REG 0x420 -#define IOCSRM_EXTIOI_EN 48 -#define IOCSRM_EXTIOI_INT_ENCODE 49 - -#define IOCSR_MEM_SIZE 0x428 - #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ --=20 2.34.1 From nobody Sat Nov 15 14:54:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750302310135912.3469557188644; Wed, 18 Jun 2025 20:05:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YQ-00073W-4p; Wed, 18 Jun 2025 23:03:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS5YK-00072S-7n for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:01 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YG-00069D-Go for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:02:59 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxrOLafVNos44ZAQ--.17418S3; Thu, 19 Jun 2025 11:02:50 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxrhu7fVNoIXkgAQ--.48014S4; Thu, 19 Jun 2025 11:02:46 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v2 2/9] loongarch: add virt feature avecintc support Date: Thu, 19 Jun 2025 10:39:37 +0800 Message-Id: <20250619023944.1278716-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250619023944.1278716-1-gaosong@loongson.cn> References: <20250619023944.1278716-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxrhu7fVNoIXkgAQ--.48014S4 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750302311883116600 Content-Type: text/plain; charset="utf-8" LoongArchVirtMachinState add avecintc features, and it use to check whether virt machine support advance interrupt controller and default set avecintc =3D ON_OFF_AUTO_ON. LoongArchVirtMachineState add misc_feature and misc_status for misc fetures and status. and set default avec feture bit. Signed-off-by: Song Gao --- hw/loongarch/virt.c | 43 +++++++++++++++++++++++++++++++++---- include/hw/loongarch/virt.h | 15 +++++++++++++ 2 files changed, 54 insertions(+), 4 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 90d4643721..3ad165af36 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -47,6 +47,28 @@ #include "hw/virtio/virtio-iommu.h" #include "qemu/error-report.h" =20 +static void virt_get_avecintc(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + OnOffAuto avecintc =3D lvms->avecintc; + + visit_type_OnOffAuto(v, name, &avecintc, errp); + +} +static void virt_set_avecintc(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + + if (lvms->avecintc =3D=3D ON_OFF_AUTO_OFF) { + lvms->misc_feature &=3D ~BIT(IOCSRF_AVEC); + lvms->misc_status &=3D ~BIT(IOCSRM_AVEC_EN); + } + + visit_type_OnOffAuto(v, name, &lvms->avecintc, errp); +} + static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -523,6 +545,10 @@ static MemTxResult virt_iocsr_misc_write(void *opaque,= hwaddr addr, features |=3D BIT(EXTIOI_ENABLE_INT_ENCODE); } =20 + if (val & BIT(IOCSRM_AVEC_EN)) { + lvms->misc_status |=3D BIT(IOCSRM_AVEC_EN); + } + address_space_stl(&lvms->as_iocsr, EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, features, attrs, NULL); @@ -548,8 +574,9 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, break; case FEATURE_REG: ret =3D BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); - /*TODO: check bit IOCSRF_AVEC with virt_is_avec_enabled */ - ret |=3D BIT(IOCSRF_AVEC); + if (virt_is_avecintc_enabled(lvms)) { + ret |=3D BIT(IOCSRF_AVEC); + } if (kvm_enabled()) { ret |=3D BIT(IOCSRF_VM); } @@ -575,8 +602,10 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, = hwaddr addr, if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { ret |=3D BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); } - /* enable avec default */ - ret |=3D BIT_ULL(IOCSRM_AVEC_EN); + if (virt_is_avecintc_enabled(lvms) && + (lvms->misc_status & BIT(IOCSRM_AVEC_EN))) { + ret |=3D BIT_ULL(IOCSRM_AVEC_EN); + } break; default: g_assert_not_reached(); @@ -820,6 +849,8 @@ static void virt_initfn(Object *obj) if (tcg_enabled()) { lvms->veiointc =3D ON_OFF_AUTO_OFF; } + lvms->misc_feature =3D BIT(IOCSRF_AVEC); + lvms->avecintc =3D ON_OFF_AUTO_ON; lvms->acpi =3D ON_OFF_AUTO_AUTO; lvms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); lvms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); @@ -1212,6 +1243,10 @@ static void virt_class_init(ObjectClass *oc, const v= oid *data) NULL, NULL); object_class_property_set_description(oc, "v-eiointc", "Enable Virt Extend I/O Interrupt Controller."= ); + object_class_property_add(oc, "avecintc", "OnOffAuto", + virt_get_avecintc, virt_set_avecintc, NULL, NULL); + object_class_property_set_description(oc, "avecintc", + "Enable Advance Interrupt Controller."); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); #ifdef CONFIG_TPM diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 671b47a986..c594421cd2 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -70,6 +70,7 @@ struct LoongArchVirtMachineState { Notifier powerdown_notifier; OnOffAuto acpi; OnOffAuto veiointc; + OnOffAuto avecintc; char *oem_id; char *oem_table_id; DeviceState *acpi_ged; @@ -83,6 +84,8 @@ struct LoongArchVirtMachineState { struct loongarch_boot_info bootinfo; DeviceState *ipi; DeviceState *extioi; + uint64_t misc_feature; + uint64_t misc_status; }; =20 #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") @@ -90,6 +93,18 @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchVirtMachineState, LO= ONGARCH_VIRT_MACHINE) void virt_acpi_setup(LoongArchVirtMachineState *lvms); void virt_fdt_setup(LoongArchVirtMachineState *lvms); =20 +static inline bool virt_is_avecintc_enabled(LoongArchVirtMachineState *lvm= s) +{ + if (!(lvms->misc_feature & BIT(IOCSRF_AVEC))) { + return false; + } + + if (lvms->avecintc =3D=3D ON_OFF_AUTO_OFF) { + return false; + } + return true; +} + static inline bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvm= s) { if (lvms->veiointc =3D=3D ON_OFF_AUTO_OFF) { --=20 2.34.1 From nobody Sat Nov 15 14:54:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750302257025676.0579974582156; Wed, 18 Jun 2025 20:04:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YU-00074Z-9M; Wed, 18 Jun 2025 23:03:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS5YM-000735-5q for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:02 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YI-0006AJ-UT for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:01 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxNHDcfVNoto4ZAQ--.57975S3; Thu, 19 Jun 2025 11:02:52 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxrhu7fVNoIXkgAQ--.48014S5; Thu, 19 Jun 2025 11:02:49 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v2 3/9] loongarch: add a advance interrupt controller device Date: Thu, 19 Jun 2025 10:39:38 +0800 Message-Id: <20250619023944.1278716-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250619023944.1278716-1-gaosong@loongson.cn> References: <20250619023944.1278716-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxrhu7fVNoIXkgAQ--.48014S5 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750302259285116600 Content-Type: text/plain; charset="utf-8" Add Loongarch advance interrupt controller device base Definition. Signed-off-by: Song Gao --- hw/intc/Kconfig | 3 ++ hw/intc/loongarch_avec.c | 68 ++++++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + hw/loongarch/Kconfig | 1 + include/hw/intc/loongarch_avec.h | 35 ++++++++++++++++ 5 files changed, 108 insertions(+) create mode 100644 hw/intc/loongarch_avec.c create mode 100644 include/hw/intc/loongarch_avec.h diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 7547528f2c..b9266dc269 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -109,3 +109,6 @@ config LOONGARCH_PCH_MSI =20 config LOONGARCH_EXTIOI bool + +config LOONGARCH_AVEC + bool diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c new file mode 100644 index 0000000000..5a3e7ecc03 --- /dev/null +++ b/hw/intc/loongarch_avec.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Loongson Advance interrupt controller. + * + * Copyright (C) 2025 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/intc/loongarch_pch_msi.h" +#include "hw/intc/loongarch_pch_pic.h" +#include "hw/intc/loongarch_avec.h" +#include "hw/pci/msi.h" +#include "hw/misc/unimp.h" +#include "migration/vmstate.h" +#include "trace.h" +#include "hw/qdev-properties.h" + + +static void loongarch_avec_realize(DeviceState *dev, Error **errp) +{ + LoongArchAVECClass *lac =3D LOONGARCH_AVEC_GET_CLASS(dev); + + Error *local_err =3D NULL; + lac->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + return; +} + +static void loongarch_avec_unrealize(DeviceState *dev) +{ + return; +} + +static void loongarch_avec_init(Object *obj) +{ + return; +} + +static void loongarch_avec_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + LoongArchAVECClass *lac =3D LOONGARCH_AVEC_CLASS(klass); + + dc->unrealize =3D loongarch_avec_unrealize; + device_class_set_parent_realize(dc, loongarch_avec_realize, + &lac->parent_realize); +} + +static const TypeInfo loongarch_avec_info =3D { + .name =3D TYPE_LOONGARCH_AVEC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(LoongArchAVECState), + .instance_init =3D loongarch_avec_init, + .class_init =3D loongarch_avec_class_init, +}; + +static void loongarch_avec_register_types(void) +{ + type_register_static(&loongarch_avec_info); +} + +type_init(loongarch_avec_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 602da304b0..6c7c0c6468 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -74,3 +74,4 @@ specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: fi= les('loongarch_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarc= h_pch_pic.c', 'loongarch_pic_common.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarc= h_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch= _extioi.c', 'loongarch_extioi_common.c')) +specific_ss.add(when: 'CONFIG_LOONGARCH_AVEC', if_true: files('loongarch_a= vec.c')) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index bb2838b7b5..1bf240b1e2 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -15,6 +15,7 @@ config LOONGARCH_VIRT select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI + select LOONGARCH_AVEC select LS7A_RTC select SMBIOS select ACPI_CPU_HOTPLUG diff --git a/include/hw/intc/loongarch_avec.h b/include/hw/intc/loongarch_a= vec.h new file mode 100644 index 0000000000..92e2ca9590 --- /dev/null +++ b/include/hw/intc/loongarch_avec.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch Advance interrupt controller definitions + * + * Copyright (C) 2025 Loongson Technology Corporation Limited + */ + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/loongarch/virt.h" + + +#define NR_VECTORS 256 + +#define TYPE_LOONGARCH_AVEC "loongarch_avec" +OBJECT_DECLARE_TYPE(LoongArchAVECState, LoongArchAVECClass, LOONGARCH_AVEC) + +typedef struct AVECCore { + CPUState *cpu; + qemu_irq parent_irq; + uint64_t arch_id; +} AVECCore; + +struct LoongArchAVECState { + SysBusDevice parent_obj; + AVECCore *cpu; + uint32_t num_cpu; +}; + +struct LoongArchAVECClass { + SysBusDeviceClass parent_class; + + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; +}; --=20 2.34.1 From nobody Sat Nov 15 14:54:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750302315622338.2568466183627; Wed, 18 Jun 2025 20:05:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YQ-000743-UX; Wed, 18 Jun 2025 23:03:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS5YM-000734-5g for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:02 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YJ-0006AQ-Ke for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:01 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxQK3dfVNouY4ZAQ--.41523S3; Thu, 19 Jun 2025 11:02:53 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxrhu7fVNoIXkgAQ--.48014S6; Thu, 19 Jun 2025 11:02:52 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v2 4/9] target/loongarch: add msg interrupt CSR registers Date: Thu, 19 Jun 2025 10:39:39 +0800 Message-Id: <20250619023944.1278716-5-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250619023944.1278716-1-gaosong@loongson.cn> References: <20250619023944.1278716-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxrhu7fVNoIXkgAQ--.48014S6 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750302317738116600 Content-Type: text/plain; charset="utf-8" include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE. Signed-off-by: Song Gao --- target/loongarch/cpu.c | 7 +++++++ target/loongarch/cpu.h | 10 ++++++++++ target/loongarch/machine.c | 5 +++++ 3 files changed, 22 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index abad84c054..bde9f917fc 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -523,6 +523,13 @@ static void loongarch_la464_initfn(Object *obj) env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS,= 7); env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS,= 8); =20 + env->CSR_MSGIS[0] =3D 0; + env->CSR_MSGIS[1] =3D 0; + env->CSR_MSGIS[2] =3D 0; + env->CSR_MSGIS[3] =3D 0; + env->CSR_MSGIR =3D 0; + env->CSR_MSGIE =3D 0; + loongarch_la464_init_csr(obj); loongarch_cpu_post_init(obj); } diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 1169768632..231ad5a7cb 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -233,6 +233,12 @@ FIELD(TLB_MISC, ASID, 1, 10) FIELD(TLB_MISC, VPPN, 13, 35) FIELD(TLB_MISC, PS, 48, 6) =20 +/*Msg interrupt registers */ +FIELD(CSR_MSGIS, IS, 0, 63) +FIELD(CSR_MSGIR, INTNUM, 0, 8) +FIELD(CSR_MSGIR, ACTIVE, 31, 1) +FIELD(CSR_MSGIE, PT, 0, 8) + #define LSX_LEN (128) #define LASX_LEN (256) =20 @@ -350,6 +356,10 @@ typedef struct CPUArchState { uint64_t CSR_DBG; uint64_t CSR_DERA; uint64_t CSR_DSAVE; + /* Msg interrupt registers */ + uint64_t CSR_MSGIS[4]; + uint64_t CSR_MSGIR; + uint64_t CSR_MSGIE; struct { uint64_t guest_addr; } stealtime; diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c index 4e70f5c879..7d5ee34f90 100644 --- a/target/loongarch/machine.c +++ b/target/loongarch/machine.c @@ -231,6 +231,11 @@ const VMStateDescription vmstate_loongarch_cpu =3D { VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU), VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU), =20 + /* Msg interrupt CSRs */ + VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, 4), + VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU), + VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU), + VMSTATE_UINT64(kvm_state_counter, LoongArchCPU), /* PV steal time */ VMSTATE_UINT64(env.stealtime.guest_addr, LoongArchCPU), --=20 2.34.1 From nobody Sat Nov 15 14:54:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17503022544483.9288851462970342; Wed, 18 Jun 2025 20:04:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YR-000747-9s; Wed, 18 Jun 2025 23:03:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS5YP-00073f-Cy for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:06 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YN-0006B3-AN for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:05 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Bx63HffVNovY4ZAQ--.58551S3; Thu, 19 Jun 2025 11:02:55 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxrhu7fVNoIXkgAQ--.48014S7; Thu, 19 Jun 2025 11:02:53 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v2 5/9] hw/loongarch: AVEC controller add a MemoryRegion Date: Thu, 19 Jun 2025 10:39:40 +0800 Message-Id: <20250619023944.1278716-6-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250619023944.1278716-1-gaosong@loongson.cn> References: <20250619023944.1278716-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxrhu7fVNoIXkgAQ--.48014S7 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750302255059116600 Content-Type: text/plain; charset="utf-8" the AVEC controller use [2fe00000-2ff000000) Memory. Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 25 ++++++++++++++++++++ hw/loongarch/virt.c | 39 +++++++++++++++++++++++++++++++- include/hw/intc/loongarch_avec.h | 1 + include/hw/loongarch/virt.h | 1 + include/hw/pci-host/ls7a.h | 2 ++ 5 files changed, 67 insertions(+), 1 deletion(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index 5a3e7ecc03..4bd431220a 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -17,6 +17,24 @@ #include "trace.h" #include "hw/qdev-properties.h" =20 +static uint64_t loongarch_avec_mem_read(void *opaque, + hwaddr addr, unsigned size) +{ + return 0; +} + +static void loongarch_avec_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + return; +} + + +static const MemoryRegionOps loongarch_avec_ops =3D { + .read =3D loongarch_avec_mem_read, + .write =3D loongarch_avec_mem_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; =20 static void loongarch_avec_realize(DeviceState *dev, Error **errp) { @@ -39,6 +57,13 @@ static void loongarch_avec_unrealize(DeviceState *dev) =20 static void loongarch_avec_init(Object *obj) { + LoongArchAVECState *s =3D LOONGARCH_AVEC(obj); + SysBusDevice *shd =3D SYS_BUS_DEVICE(obj); + memory_region_init_io(&s->avec_mmio, OBJECT(s), &loongarch_avec_ops, + s, TYPE_LOONGARCH_AVEC, VIRT_AVEC_MSG_OFFSET); + sysbus_init_mmio(shd, &s->avec_mmio); + msi_nonbroken =3D true; + return; } =20 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 3ad165af36..664705ce6e 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -28,6 +28,7 @@ #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" +#include "hw/intc/loongarch_avec.h" #include "hw/pci-host/ls7a.h" #include "hw/pci-host/gpex.h" #include "hw/misc/unimp.h" @@ -370,7 +371,7 @@ static void virt_cpu_irq_init(LoongArchVirtMachineState= *lvms) static void virt_irq_init(LoongArchVirtMachineState *lvms) { DeviceState *pch_pic, *pch_msi; - DeviceState *ipi, *extioi; + DeviceState *ipi, *extioi, *avec; SysBusDevice *d; int i, start, num; =20 @@ -416,6 +417,33 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) * +--------+ +---------+ +---------+ * | UARTs | | Devices | | Devices | * +--------+ +---------+ +---------+ + * + * + * Advanced Extended IRQ model + * + * +-----+ +-----------------------+ +-------+ + * | IPI | --> | CPUINTC | <-- | Timer | + * +-----+ +-----------------------+ +-------+ + * ^ ^ ^ + * | | | + * +---------+ +----------+ +---------+ +-------+ + * | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | + * +---------+ +----------+ +---------+ +-------+ + * ^ ^ + * | | + * +---------+ +---------+ + * | PCH-PIC | | PCH-MSI | + * +---------+ +---------+ + * ^ ^ ^ + * | | | + * +---------+ +---------+ +---------+ + * | Devices | | PCH-LPC | | Devices | + * +---------+ +---------+ +---------+ + * ^ + * | + * +---------+ + * | Devices | + * +---------+ */ =20 /* Create IPI device */ @@ -429,6 +457,15 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); =20 + /* Create AVEC device*/ + if (virt_is_avecintc_enabled(lvms)) { + avec =3D qdev_new(TYPE_LOONGARCH_AVEC); + lvms->avec =3D avec; + sysbus_realize_and_unref(SYS_BUS_DEVICE(avec), &error_fatal); + memory_region_add_subregion(get_system_memory(), VIRT_AVEC_BASE, + sysbus_mmio_get_region(SYS_BUS_DEVICE(avec), 0)); + } + /* Create EXTIOI device */ extioi =3D qdev_new(TYPE_LOONGARCH_EXTIOI); lvms->extioi =3D extioi; diff --git a/include/hw/intc/loongarch_avec.h b/include/hw/intc/loongarch_a= vec.h index 92e2ca9590..3e8cf7d2c1 100644 --- a/include/hw/intc/loongarch_avec.h +++ b/include/hw/intc/loongarch_avec.h @@ -23,6 +23,7 @@ typedef struct AVECCore { =20 struct LoongArchAVECState { SysBusDevice parent_obj; + MemoryRegion avec_mmio; AVECCore *cpu; uint32_t num_cpu; }; diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index c594421cd2..8811418b96 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -86,6 +86,7 @@ struct LoongArchVirtMachineState { DeviceState *extioi; uint64_t misc_feature; uint64_t misc_status; + DeviceState *avec; }; =20 #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index 79d4ea8501..17f047c188 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -24,6 +24,8 @@ #define VIRT_PCH_REG_BASE 0x10000000UL #define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE) #define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL +#define VIRT_AVEC_MSG_OFFSET 0x1000000 +#define VIRT_AVEC_BASE (VIRT_PCH_MSI_ADDR_LOW - VIRT_AVEC_MSG_OF= FSET) #define VIRT_PCH_REG_SIZE 0x400 #define VIRT_PCH_MSI_SIZE 0x8 =20 --=20 2.34.1 From nobody Sat Nov 15 14:54:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750302276845518.7729064046832; Wed, 18 Jun 2025 20:04:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YW-00075U-W6; Wed, 18 Jun 2025 23:03:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS5YV-00074t-1i for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:11 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YS-0006Be-Ug for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:10 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Bx7eLkfVNow44ZAQ--.23265S3; Thu, 19 Jun 2025 11:03:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxrhu7fVNoIXkgAQ--.48014S8; Thu, 19 Jun 2025 11:02:55 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v2 6/9] hw/loongarch: Implement avec controller imput and output pins Date: Thu, 19 Jun 2025 10:39:41 +0800 Message-Id: <20250619023944.1278716-7-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250619023944.1278716-1-gaosong@loongson.cn> References: <20250619023944.1278716-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxrhu7fVNoIXkgAQ--.48014S8 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750302277631116600 Content-Type: text/plain; charset="utf-8" the AVEC controller supports 256*256 irqs input, all the irqs connect CPU I= NT_AVEC irq Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 21 +++++++++++++++++++++ hw/loongarch/virt.c | 11 +++++++++-- target/loongarch/cpu.h | 3 ++- 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index 4bd431220a..7dd8bac696 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -38,7 +38,12 @@ static const MemoryRegionOps loongarch_avec_ops =3D { =20 static void loongarch_avec_realize(DeviceState *dev, Error **errp) { + LoongArchAVECState *s =3D LOONGARCH_AVEC(dev); LoongArchAVECClass *lac =3D LOONGARCH_AVEC_GET_CLASS(dev); + MachineState *machine =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const CPUArchIdList *id_list; + int i; =20 Error *local_err =3D NULL; lac->parent_realize(dev, &local_err); @@ -47,6 +52,22 @@ static void loongarch_avec_realize(DeviceState *dev, Err= or **errp) return; } =20 + assert(mc->possible_cpu_arch_ids); + id_list =3D mc->possible_cpu_arch_ids(machine); + s->num_cpu =3D id_list->len; + s->cpu =3D g_new(AVECCore, s->num_cpu); + if (s->cpu =3D=3D NULL) { + error_setg(errp, "Memory allocation for AVECCore fail"); + return; + } + + for (i =3D 0; i < s->num_cpu; i++) { + s->cpu[i].arch_id =3D id_list->cpus[i].arch_id; + s->cpu[i].cpu =3D CPU(id_list->cpus[i].cpu); + qdev_init_gpio_out(dev, &s->cpu[i].parent_irq, 1); + } + qdev_init_gpio_in(dev, NULL, NR_VECTORS * s->num_cpu); + return; } =20 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 664705ce6e..18ff41f2ad 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -368,7 +368,7 @@ static void virt_cpu_irq_init(LoongArchVirtMachineState= *lvms) } } =20 -static void virt_irq_init(LoongArchVirtMachineState *lvms) +static void virt_irq_init(LoongArchVirtMachineState *lvms, MachineState *m= s) { DeviceState *pch_pic, *pch_msi; DeviceState *ipi, *extioi, *avec; @@ -464,6 +464,13 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) sysbus_realize_and_unref(SYS_BUS_DEVICE(avec), &error_fatal); memory_region_add_subregion(get_system_memory(), VIRT_AVEC_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(avec), 0)); + CPUState *cpu_state; + DeviceState *cpudev; + for (int cpu =3D 0; cpu < ms->smp.cpus; cpu++) { + cpu_state =3D qemu_get_cpu(cpu); + cpudev =3D DEVICE(cpu_state); + qdev_connect_gpio_out(avec, cpu, qdev_get_gpio_in(cpudev, INT_= AVEC)); + } } =20 /* Create EXTIOI device */ @@ -809,7 +816,7 @@ static void virt_init(MachineState *machine) } =20 /* Initialize the IO interrupt subsystem */ - virt_irq_init(lvms); + virt_irq_init(lvms, machine); lvms->machine_done.notify =3D virt_done; qemu_add_machine_init_done_notifier(&lvms->machine_done); /* connect powerdown request */ diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 231ad5a7cb..d5e64c5e8e 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -217,9 +217,10 @@ FIELD(CSR_CRMD, WE, 9, 1) extern const char * const regnames[32]; extern const char * const fregnames[32]; =20 -#define N_IRQS 13 +#define N_IRQS 15 #define IRQ_TIMER 11 #define IRQ_IPI 12 +#define INT_AVEC 14 =20 #define LOONGARCH_STLB 2048 /* 2048 STLB */ #define LOONGARCH_MTLB 64 /* 64 MTLB */ --=20 2.34.1 From nobody Sat Nov 15 14:54:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750302312336738.8813290669954; Wed, 18 Jun 2025 20:05:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YX-000767-OP; Wed, 18 Jun 2025 23:03:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS5YW-00075E-Kf for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:12 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YU-0006Bk-Iv for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:12 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxPOLofVNoyY4ZAQ--.17316S3; Thu, 19 Jun 2025 11:03:04 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxrhu7fVNoIXkgAQ--.48014S9; Thu, 19 Jun 2025 11:03:00 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v2 7/9] hw/loongarch: Implement avec set irq Date: Thu, 19 Jun 2025 10:39:42 +0800 Message-Id: <20250619023944.1278716-8-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250619023944.1278716-1-gaosong@loongson.cn> References: <20250619023944.1278716-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxrhu7fVNoIXkgAQ--.48014S9 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750302313700116600 Content-Type: text/plain; charset="utf-8" Implement avec set irq and update CSR_MSIS and CSR_MSGIR. Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index 7dd8bac696..bbd1b48c7d 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -16,6 +16,12 @@ #include "migration/vmstate.h" #include "trace.h" #include "hw/qdev-properties.h" +#include "target/loongarch/cpu.h" + +/* msg addr field */ +FIELD(MSG_ADDR, IRQ_NUM, 4, 8) +FIELD(MSG_ADDR, CPU_NUM, 12, 8) +FIELD(MSG_ADDR, FIX, 28, 12) =20 static uint64_t loongarch_avec_mem_read(void *opaque, hwaddr addr, unsigned size) @@ -23,12 +29,33 @@ static uint64_t loongarch_avec_mem_read(void *opaque, return 0; } =20 +static void avec_set_irq(LoongArchAVECState *s, int cpu_num, int irq_num, = int level) +{ + MachineState *machine =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const CPUArchIdList *id_list =3D NULL; + assert(mc->possible_cpu_arch_ids(machine)); + id_list =3D mc->possible_cpu_arch_ids(machine); + CPUState *cpu =3D id_list->cpus[cpu_num].cpu; + CPULoongArchState *env =3D &LOONGARCH_CPU(cpu)->env; + + set_bit(irq_num, &env->CSR_MSGIS[irq_num / 64]); + qemu_set_irq(s->cpu[cpu_num].parent_irq, 1); + env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, INTNUM, irq_nu= m); + env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, ACTIVE, 0); +} + static void loongarch_avec_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - return; -} + int irq_num, cpu_num =3D 0; + LoongArchAVECState *s =3D LOONGARCH_AVEC(opaque); + uint64_t msg_addr =3D addr + VIRT_AVEC_BASE; =20 + cpu_num =3D FIELD_EX64(msg_addr, MSG_ADDR, IRQ_NUM); + irq_num =3D FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM); + avec_set_irq(s, cpu_num, irq_num, 1); +} =20 static const MemoryRegionOps loongarch_avec_ops =3D { .read =3D loongarch_avec_mem_read, --=20 2.34.1 From nobody Sat Nov 15 14:54:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750302239898253.31616425874927; Wed, 18 Jun 2025 20:03:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5Yc-00076i-UT; Wed, 18 Jun 2025 23:03:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS5Yb-00076Y-LX for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:17 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5YZ-0006CZ-Pc for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:17 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxbKzufVNozo4ZAQ--.58680S3; Thu, 19 Jun 2025 11:03:10 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxrhu7fVNoIXkgAQ--.48014S10; Thu, 19 Jun 2025 11:03:04 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v2 8/9] target/loongarch: CSR_ESTAT enable msg interrupts. Date: Thu, 19 Jun 2025 10:39:43 +0800 Message-Id: <20250619023944.1278716-9-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250619023944.1278716-1-gaosong@loongson.cn> References: <20250619023944.1278716-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxrhu7fVNoIXkgAQ--.48014S10 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750302243379116600 Content-Type: text/plain; charset="utf-8" when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit. Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h | 1 + target/loongarch/cpu.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 0834e91f30..83f6cb081a 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -39,6 +39,7 @@ FIELD(CSR_ECFG, VS, 16, 3) =20 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ FIELD(CSR_ESTAT, IS, 0, 13) +FIELD(CSR_ESTAT, MSGINT, 14, 1) FIELD(CSR_ESTAT, ECODE, 16, 6) FIELD(CSR_ESTAT, ESUBCODE, 22, 9) =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index bde9f917fc..28b23743f9 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -127,6 +127,15 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int = level) return; } =20 + /* do INTC_AVEC irqs */ + if (irq =3D=3D INT_AVEC) { + for (int i =3D 256; i >=3D 0; i--) { + if (test_bit(i, &(env->CSR_MSGIS[i / 64]))) { + env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, M= SGINT, 1); + } + } + } + if (kvm_enabled()) { kvm_loongarch_set_interrupt(cpu, irq, level); } else if (tcg_enabled()) { --=20 2.34.1 From nobody Sat Nov 15 14:54:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750302283313324.589214426628; Wed, 18 Jun 2025 20:04:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5Yj-00078B-JB; Wed, 18 Jun 2025 23:03:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS5Yi-00077g-9O for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:24 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS5Yg-0006Cr-4H for qemu-devel@nongnu.org; Wed, 18 Jun 2025 23:03:24 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxQK_yfVNo0o4ZAQ--.23708S3; Thu, 19 Jun 2025 11:03:14 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMCxrhu7fVNoIXkgAQ--.48014S11; Thu, 19 Jun 2025 11:03:10 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v2 9/9] target/loongarch: CSR_ECFG enable msg interrupt Date: Thu, 19 Jun 2025 10:39:44 +0800 Message-Id: <20250619023944.1278716-10-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250619023944.1278716-1-gaosong@loongson.cn> References: <20250619023944.1278716-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxrhu7fVNoIXkgAQ--.48014S11 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750302285525116600 Content-Type: text/plain; charset="utf-8" when loongarch cpu set irq is INT_AVEC, we need set CSR_ECFG MSGINT bit. Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h | 5 +++-- target/loongarch/cpu.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 83f6cb081a..b1e251a72b 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -34,11 +34,12 @@ FIELD(CSR_MISC, ALCL, 12, 4) FIELD(CSR_MISC, DWPL, 16, 3) =20 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */ -FIELD(CSR_ECFG, LIE, 0, 13) +FIELD(CSR_ECFG, LIE, 0, 15) /*bit 15 is msg interrupt enabled */ +FIELD(CSR_ECFG, MSGINT, 14, 1) FIELD(CSR_ECFG, VS, 16, 3) =20 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ -FIELD(CSR_ESTAT, IS, 0, 13) +FIELD(CSR_ESTAT, IS, 0, 15) /*bit 15 is msg interrupt enabled */ FIELD(CSR_ESTAT, MSGINT, 14, 1) FIELD(CSR_ESTAT, ECODE, 16, 6) FIELD(CSR_ESTAT, ESUBCODE, 22, 9) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 28b23743f9..c5924bb94f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -132,6 +132,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int l= evel) for (int i =3D 256; i >=3D 0; i--) { if (test_bit(i, &(env->CSR_MSGIS[i / 64]))) { env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, M= SGINT, 1); + env->CSR_ECFG =3D FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGI= NT, 1); } } } --=20 2.34.1