target/riscv: add missing named features

[qemu PATCH 3/3] target/riscv/cpu.c: do better with 'named features' doc

Posted by Daniel Henrique Barboza 5 months, 2 weeks ago

Most of the named features are added directly in isa_edata_arr[], some
of them are also added in riscv_cpu_named_features(). There is a reason
for that, and the existing docs can do better explaining it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cd0b159ed5..fdf2eb2b1c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1377,13 +1377,23 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
  * 'Named features' is the name we give to extensions that we
  * don't want to expose to users. They are either immutable
  * (always enabled/disable) or they'll vary depending on
- * the resulting CPU state. They have riscv,isa strings
- * and priv_ver like regular extensions.
+ * the resulting CPU state.
+ *
+ * Some of them are always enabled depending on priv version
+ * of the CPU and are declared directly in isa_edata_arr[].
+ * The ones listed here have special checks during finalize()
+ * time and require their own flags like regular extensions.
+ * See riscv_cpu_update_named_features() for more info.
  */
 const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
     MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
     MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
     MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
+
+    /*
+     * 'ziccrse' has its own flag because the KVM driver
+     * wants to enable/disable it on its own accord.
+     */
     MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true),
 
     { },
-- 
2.49.0

Re: [qemu PATCH 3/3] target/riscv/cpu.c: do better with 'named features' doc

Posted by Alistair Francis 5 months, 2 weeks ago

On Fri, May 30, 2025 at 6:24 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Most of the named features are added directly in isa_edata_arr[], some
> of them are also added in riscv_cpu_named_features(). There is a reason
> for that, and the existing docs can do better explaining it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cd0b159ed5..fdf2eb2b1c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1377,13 +1377,23 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
>   * 'Named features' is the name we give to extensions that we
>   * don't want to expose to users. They are either immutable
>   * (always enabled/disable) or they'll vary depending on
> - * the resulting CPU state. They have riscv,isa strings
> - * and priv_ver like regular extensions.
> + * the resulting CPU state.
> + *
> + * Some of them are always enabled depending on priv version
> + * of the CPU and are declared directly in isa_edata_arr[].
> + * The ones listed here have special checks during finalize()
> + * time and require their own flags like regular extensions.
> + * See riscv_cpu_update_named_features() for more info.
>   */
>  const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
>      MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
>      MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
>      MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
> +
> +    /*
> +     * 'ziccrse' has its own flag because the KVM driver
> +     * wants to enable/disable it on its own accord.
> +     */
>      MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true),
>
>      { },
> --
> 2.49.0
>
>

[qemu PATCH 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa
[qemu PATCH 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa
[qemu PATCH 3/3] target/riscv/cpu.c: do better with 'named features' doc