[v5] target/riscv/kvm: CSR related fixes

[PATCH v5 0/9] target/riscv/kvm: CSR related fixes

Daniel Henrique Barboza posted 9 patches 9 months, 2 weeks ago

Diff against v1 v2 v3 v4
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250429124421.223883-1-dbarboza@ventanamicro.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.h         |   1 +
target/riscv/kvm/kvm-cpu.c | 333 +++++++++++++++++++++++--------------
2 files changed, 212 insertions(+), 122 deletions(-)

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[PATCH v5 0/9] target/riscv/kvm: CSR related fixes

Posted by Daniel Henrique Barboza 9 months, 2 weeks ago

Hi,

This version has a fix on patch 8 where I did use an extra variable and
happened to set the wrong mask too.

We'll let the compiler cast the uint32_t from an uint64_t reg. A cast
was added for extra clarity when reading the code, although some picky
toolchains might require an explicit cast in this case too.

No other changes made.

Patches missing acks/reviews: patch 8.

Changes from v4:
- patch 8:
  - remove the 'reg32' variable and add an uint32_t cast when passing
    the uint64_t var 'reg' to kvm_cpu_csr_set_u32()
- v4 link: https://lore.kernel.org/qemu-riscv/20250428192323.84992-1-dbarboza@ventanamicro.com/

Daniel Henrique Barboza (9):
  target/riscv/kvm: minor fixes/tweaks
  target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
  target/riscv/kvm: turn u32/u64 reg functions into macros
  target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
  target/riscv/kvm: add kvm_csr_cfgs[]
  target/riscv/kvm: do not read unavailable CSRs
  target/riscv/kvm: add senvcfg CSR
  target/riscv/kvm: read/write KVM regs via env size
  target/riscv/kvm: add scounteren CSR

 target/riscv/cpu.h         |   1 +
 target/riscv/kvm/kvm-cpu.c | 333 +++++++++++++++++++++++--------------
 2 files changed, 212 insertions(+), 122 deletions(-)

-- 
2.49.0

Re: [PATCH v5 0/9] target/riscv/kvm: CSR related fixes

Posted by Alistair Francis 9 months, 1 week ago

On Tue, Apr 29, 2025 at 10:46 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This version has a fix on patch 8 where I did use an extra variable and
> happened to set the wrong mask too.
>
> We'll let the compiler cast the uint32_t from an uint64_t reg. A cast
> was added for extra clarity when reading the code, although some picky
> toolchains might require an explicit cast in this case too.
>
> No other changes made.
>
> Patches missing acks/reviews: patch 8.
>
> Changes from v4:
> - patch 8:
>   - remove the 'reg32' variable and add an uint32_t cast when passing
>     the uint64_t var 'reg' to kvm_cpu_csr_set_u32()
> - v4 link: https://lore.kernel.org/qemu-riscv/20250428192323.84992-1-dbarboza@ventanamicro.com/
>
> Daniel Henrique Barboza (9):
>   target/riscv/kvm: minor fixes/tweaks
>   target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
>   target/riscv/kvm: turn u32/u64 reg functions into macros
>   target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
>   target/riscv/kvm: add kvm_csr_cfgs[]
>   target/riscv/kvm: do not read unavailable CSRs
>   target/riscv/kvm: add senvcfg CSR
>   target/riscv/kvm: read/write KVM regs via env size
>   target/riscv/kvm: add scounteren CSR

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.h         |   1 +
>  target/riscv/kvm/kvm-cpu.c | 333 +++++++++++++++++++++++--------------
>  2 files changed, 212 insertions(+), 122 deletions(-)
>
> --
> 2.49.0
>
>