From nobody Sat Nov 15 22:35:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745930805; cv=none; d=zohomail.com; s=zohoarc; b=amlE42xNFPb5Is7Hp6C9OZ6NBx4nWseQf/+KGCnupjJszI6/nDygkHO1g9/jEXGlGWieADA/MScwrwrBE8BfCnkpL5sKmJwmmewWRZ7467Cjv7VXBE0bkXFJ6SjhPQK2hqetEEaX67So0U9/EihfGdvaG3WeMdFx047Zy/wQ74A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745930805; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=f6R3EUC6CKMFKAnlwhLj+btXOWn++vvQKz0yRoESdjA=; b=Ek3rOpMsSRHVB8Sejg9quooa/Y0Zg6d63YymwcivyDl8vRipy3/x4Ldo0LN205IjRaUjN1dPl2XYvCicO5Xsrqg8HucO90wrx+VOgTd9d3eaBZ7pE3YGOXjuF9LoIvOoPOqYXjVaXgQiXWGPhpEorI5Rtb5cFCAu0zrDxCSypfI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745930805429747.2128267448333; Tue, 29 Apr 2025 05:46:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kKH-00024A-Bw; Tue, 29 Apr 2025 08:44:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kKB-0001s2-S6 for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:35 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kK7-0004Kv-8e for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:34 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-22401f4d35aso71677105ad.2 for ; Tue, 29 Apr 2025 05:44:30 -0700 (PDT) Received: from grind.. ([152.234.125.33]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309ef04ba89sm11001161a91.10.2025.04.29.05.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 05:44:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745930669; x=1746535469; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f6R3EUC6CKMFKAnlwhLj+btXOWn++vvQKz0yRoESdjA=; b=X2i/1Pd6UXzyP3hFj9U0jz1yOBA4hIMM5CEaSJ2CAACKMBN2XJv0aG17FEtqiWrp+k Y9NVzXtcSJKDpf7hPNVBS7BPlbJ42tGifRw1r1xynA95b5yeWrHQW6OMj2q3eVP6awae bTprXO5ezsOI7AyB+34iVPm13T6DIG/HPEYrgub3vesYh0HfVH9w8Vra5FoPUxDm3fzh hrbM/C2RlNaCD7mS9KEyXYPDSQcEqZefQY9QPSiNxkrCzWLreuE0svS6qLYMEaHrCpiH tseJKkg/r5b1tR23QVZ6q8CHsKUk2s0/grhyEPzRPKDV8Ka8EDhBwoZysZcGC2PAjgeG 7W6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745930669; x=1746535469; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f6R3EUC6CKMFKAnlwhLj+btXOWn++vvQKz0yRoESdjA=; b=v6hjBZ2uynIptBDEDkJGZZ/IPnxt3U+EwVaIVhr2IfM4U4YD6yd3rJqhpX7FAOFwt7 K3YWSq648AfuKpD68D47uXoK8LFoFCMAKPZAvFOZcAl2D0PqWoUezYxdfRTlHmQ8A7UN w4bqGZO9R4HE8TrJG4qs9eG+PG0TGEBKplmvCbxrjBj8U5S9I1NjoL2DsNDoUPtuD9iW 54aS37iipU8cOI8t1XDFxMuZjNuv3rJmiiV4KHIFFUgOvUYijuB6TDy5MmFYASEse33M 77DXtuiSbU2ISfkgYU4SN5p5pZ0FMo1duCFePILYYHFu2qRVlvMosLnUmLNIGF+HMnog Oo1Q== X-Gm-Message-State: AOJu0Yw0ux54x6gNgs7HFLbZvJ53HavgQnww23tTOFmfBipFq/RY8dC9 DhjtFFJWY7sk7rX/iNLsA8gMcX8G9R+2iEfSAVae2c1Dbq3ApyLocyY585c6HJ7j636Y0/BIbzE t X-Gm-Gg: ASbGncse/P7g3PHBVUIluze2J8Gi+KVbBdABy9K0q3yt0biPrNNJQH88ZRYLob3i6oy dx/njH/ENisbDIzON/xzzQd5wUT3e+r+XgerxikaRk+OxEaLQ8EvJTHEDvF9YBWDPQFGQzpwkwj YN6P0XqDvo1gODvp+dxOWkE9iJK7zbNMS/1OQwJThsDE6dxFixeODKq8QXTb6wLuSZg8JomoVEF dJB4r02t4WEDGOTghRL7lZd7yVHkol+qCTMwbouAFXHZ9Fql+YCaVaZnGA7uiCD5ycVaHA7a9Wf lkhzAmDlmluCvARuDrEgBvakbFFO1Maml0YhRNOjZXw= X-Google-Smtp-Source: AGHT+IGmMhlkUUOja7G84fk0iUqVZ+TD8ZVcKKFoDQZ9WqFsELGXmOs256cY8/umL4ISSk5CqAKbJA== X-Received: by 2002:a17:90b:2750:b0:2ff:7ad4:77af with SMTP id 98e67ed59e1d1-30a23de91d4mr3386528a91.20.1745930669041; Tue, 29 Apr 2025 05:44:29 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza , Alistair Francis Subject: [PATCH v5 1/9] target/riscv/kvm: minor fixes/tweaks Date: Tue, 29 Apr 2025 09:44:13 -0300 Message-ID: <20250429124421.223883-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429124421.223883-1-dbarboza@ventanamicro.com> References: <20250429124421.223883-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745930807546019100 Content-Type: text/plain; charset="utf-8" Remove an unused 'KVMScratchCPU' pointer argument in kvm_riscv_check_sbi_dbcn_support(). Put kvm_riscv_reset_regs_csr() after kvm_riscv_put_regs_csr(). This will make a future patch diff easier to read, when changes in kvm_riscv_reset_regs_csr() and kvm_riscv_get_regs_csr() will be made. Fixes: a6b53378f5 ("target/riscv/kvm: implement SBI debug console (DBCN) ca= lls") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 9214ce490c..accad4c28e 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -613,19 +613,6 @@ static int kvm_riscv_put_regs_core(CPUState *cs) return ret; } =20 -static void kvm_riscv_reset_regs_csr(CPURISCVState *env) -{ - env->mstatus =3D 0; - env->mie =3D 0; - env->stvec =3D 0; - env->sscratch =3D 0; - env->sepc =3D 0; - env->scause =3D 0; - env->stval =3D 0; - env->mip =3D 0; - env->satp =3D 0; -} - static int kvm_riscv_get_regs_csr(CPUState *cs) { CPURISCVState *env =3D &RISCV_CPU(cs)->env; @@ -660,6 +647,19 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) return 0; } =20 +static void kvm_riscv_reset_regs_csr(CPURISCVState *env) +{ + env->mstatus =3D 0; + env->mie =3D 0; + env->stvec =3D 0; + env->sscratch =3D 0; + env->sepc =3D 0; + env->scause =3D 0; + env->stval =3D 0; + env->mip =3D 0; + env->satp =3D 0; +} + static int kvm_riscv_get_regs_fp(CPUState *cs) { int ret =3D 0; @@ -1078,7 +1078,6 @@ static int uint64_cmp(const void *a, const void *b) } =20 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, - KVMScratchCPU *kvmcpu, struct kvm_reg_list *reglist) { struct kvm_reg_list *reg_search; @@ -1197,7 +1196,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); } =20 - kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); + kvm_riscv_check_sbi_dbcn_support(cpu, reglist); } =20 static void riscv_init_kvm_registers(Object *cpu_obj) --=20 2.49.0 From nobody Sat Nov 15 22:35:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745930832; cv=none; d=zohomail.com; s=zohoarc; b=JVTNZmLWOkMNIwrLOFi4xucMt2zIk1GfYlrHAxVzrUx/dl7rRhVkM3en+QvDKy4ugUg5Ii5pWXtOkxxopnLp2/4RIeTvGqhMdvfqu43vgBRlHGmScxptkdzRdXS0ASf90Uc7LSGDMJb4wzuBAekUdflKVVXRpP1YizOEoa0/gow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745930832; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=O1/pH75J2ESZ3iYPkpvn3hHXRSZ0chs2dEX/b6rX2kE=; b=KpWSQT4q+Q2sFKSoq6EiqoujSp4f6gYnT81Tw9Up4dOeq98MkZ9RbtuOfZys4cp1gT+y7ptAZ1z4rFrZiW0NlL2MHmXHKtgy9Qd/Tjd0z77cFLp/Gs6nqCKL1Y7WrXMaflFok/MW4Jq5QCYafMkgt6akRxZcYfHDIG9wVJwnL8Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745930832344845.5094124566642; Tue, 29 Apr 2025 05:47:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kKH-00026Y-MM; Tue, 29 Apr 2025 08:44:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kKB-0001sC-U0 for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:37 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kK9-0004LG-BY for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:34 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-22c336fcdaaso69838715ad.3 for ; Tue, 29 Apr 2025 05:44:32 -0700 (PDT) Received: from grind.. ([152.234.125.33]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309ef04ba89sm11001161a91.10.2025.04.29.05.44.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 05:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745930671; x=1746535471; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O1/pH75J2ESZ3iYPkpvn3hHXRSZ0chs2dEX/b6rX2kE=; b=jitn915UQ4wKsB4pN9r+8xzXUSPD65cxD5rjIL7gJsB4HXcu5STNaqhMx8KANkRsGg Kwc2QNAJuvE1xPOdT44DgiuToVoUZYuUlYrAYyU0BsyFla0BTW84R2Wl3k0I8VJRNUxk g48mRye8fMI5qrl6WHlU4Vf+n48iI9yvsrgvZVwXn3ObR3urOJL/zhDmbbDrspirQVFv kRTb/984wGubMLHK35+hnD8Yps1jfYVmVdRGeLkcM8WpAe+mWyYsG1nO/vY+P+HmiKDt YcjcjYEr4f865zWAIEMbW+h0ZG5CEUbqLDxEjgfjOpseaeFxN+MOA4+XRSpyYhesRatc OUUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745930671; x=1746535471; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O1/pH75J2ESZ3iYPkpvn3hHXRSZ0chs2dEX/b6rX2kE=; b=W0doBaLRKHlHhg/4GIezFMR4GOtgqObfCAALDLJewdkQHJCaziuz9ADD+ERr/NMQaO 0LnizKif/i3HayUVHQsfV8AFiFeZSymfpt4tsQZ84b572c+eV+8kseMs9UTj0SpSUwSu HawLDDxgTf7ajEk8x/uuZSkd0A4OMv7Fp6j4sNF359C7hY1zaSiMBNZClq/q0mwiq5/s dnknBhWYLWmlgjZVCyDFYnq77hF/dhFv/lGo+3ys9e9sCfKVQwwdQAZcMzpSCBOzO7X4 XvKLxhAlv6SfJjlHgNY06CVL01ptLeGkNzz9e/3e7FQSuey0X1yFcIrNXSTalytTYlh9 MY9Q== X-Gm-Message-State: AOJu0YzFc5Z+jBNizKlGm1RUMKVqpkoQ9FTqM+SUIEKhmp+S6MSrSb3M VnT6DYEK0eZ1/Y6qgKRXSGdVvziz9iOUCErPqvnp0QKmvqYFN+I1nD7qULLVYhT0Z93qcS8a0Hu Z X-Gm-Gg: ASbGncsJNUV9X2j15hiTVHMG6FYgrcs+g7FRDTLWF6gdycg7+WXr52271dLg79dkAno H83BgkuvlQf5La8SndMNv+Got9uwK7VXbydJLmzAnnfEUwhQS/iGqjPTBNGdpm1RPsJoHklYkDp v/SIACzOQZTgkBCd5agCdL1KcU+TDl94ilL9kPrEZ2CxFYOIA6IpVvb03CbPGa8rToqDwAirEp+ 7kTrpA6PVA0/JMyB/jcLGicj7gjfqk1C38YYhVUbOCBPPGmL/BEdD8N7GBBdT3QaIMTDdRjI9/s gZCQmLX+PyoWvtovj4ryXEXgpqSAXPR4W6O2Zs2mgUg= X-Google-Smtp-Source: AGHT+IEJlBPnBJUYQxqdJXbCKNuXqmtaiHpuySn/Xd2ytwjGrf/8cVt/+Ho280Mw2UY5872zvB4jfw== X-Received: by 2002:a17:90b:3a44:b0:305:2d27:7ba0 with SMTP id 98e67ed59e1d1-30a21543ea5mr5020230a91.6.1745930671416; Tue, 29 Apr 2025 05:44:31 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza , Alistair Francis Subject: [PATCH v5 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg() Date: Tue, 29 Apr 2025 09:44:14 -0300 Message-ID: <20250429124421.223883-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429124421.223883-1-dbarboza@ventanamicro.com> References: <20250429124421.223883-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745930833449019000 Content-Type: text/plain; charset="utf-8" 'reglist' is being g-malloc'ed but never freed. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index accad4c28e..6ba122f360 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1119,10 +1119,10 @@ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVM= ScratchCPU *kvmcpu, =20 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmc= pu) { + g_autofree struct kvm_reg_list *reglist =3D NULL; KVMCPUConfig *multi_ext_cfg; struct kvm_one_reg reg; struct kvm_reg_list rl_struct; - struct kvm_reg_list *reglist; uint64_t val, reg_id, *reg_search; int i, ret; =20 --=20 2.49.0 From nobody Sat Nov 15 22:35:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745930758; cv=none; d=zohomail.com; s=zohoarc; b=dug1Va7F0WU4K3VrQxs+X2V7jVRX6mFQB9aXaebhtJrzqApqG6zotpX4Px4nwF5bXSckCTcLblwv03wrSjVfT2JVxd8Y10loeEb3MjLKzpWOJjagdEqmMnSh13l3p61W0C5uPWkJ9IFdvvpJc8wroqkazmSW0o1dmQzdU9z9hMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745930758; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TOeCBxmoJl3fpGbBgDl7Mncm5lacwWUBmOxyjJ4Qi9g=; b=kPB2PGwNhtWI4bE4p21YM91i/6OhWS5j5nR/4tIbovEUDrbj28hqhrQD+q2ttHrXCwGvzZHHDMWnamNF60x+lWUz1MyB5XUHgznGWtoHdkNmOfPqdezzdmuLdd41O9hg98bOJfZfFrID4o4zPrQeKqEqjzjCUfxf0HklRLxvNIU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174593075825998.85550936528296; Tue, 29 Apr 2025 05:45:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kKJ-0002BS-2X; Tue, 29 Apr 2025 08:44:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kKF-00021g-L4 for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:39 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kKB-0004Lh-Oz for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:37 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2295d78b45cso84197695ad.0 for ; Tue, 29 Apr 2025 05:44:35 -0700 (PDT) Received: from grind.. ([152.234.125.33]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309ef04ba89sm11001161a91.10.2025.04.29.05.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 05:44:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745930674; x=1746535474; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TOeCBxmoJl3fpGbBgDl7Mncm5lacwWUBmOxyjJ4Qi9g=; b=hAX9uZDuHbE1n9c7HGuhphuQuEcFp7EwqmKXIWYOx1Ao/UDOsFzqQ9J/umCOHCyDVf N0oFplVC+9/+Fp9ZIIKRdnPVCQAsDSeyP3eimKe4tjGbnSqqU8mAtY7vOSdaiv/nX/8h 0imSJY5EdiLbl1p/ViCY6eyyyorGx3w4AkzvM/dlw3rv2XZNQsTNl1H/LZLBl8RArAPB b/VIexn6wfByoNo4jiyYOKQh3x+Luy8djU3m3DzmoWTwyFAlrfRa7fruom119UQnxW8g CRHsF/xFChNmkM49pu17jDKgtlQXny4MGbk7GR2Xyf7d6IyTI3Kh4b15SUwHgNd7x97M Nydw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745930674; x=1746535474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TOeCBxmoJl3fpGbBgDl7Mncm5lacwWUBmOxyjJ4Qi9g=; b=M75iS9Y5N+GH88qlo1N4ipsFmYMVw2woTgy4VPBnTA/Zg4KtrIVgiZPgXYgbHTXKjm F9QgN3X0GbUsasifXccy2/S343GqHMYILu5kLgjSFYxtF20yiBwenOQ8f3pokolPz4lg nCRZQriq/aqtf9+Sluga+V+hIWugyUc6MC2ytzAUlwwhsBIK3PpBHtz5FGQ5otal+K2a H1jaS5OsoZAa9e+qd84z+CmvKUCVWDz/2rjDw4xjBmF6S+Ib1BZrLDfaQS+mlbbBH+vx FUQHQnhQGJFIL95XobIrJx4zjxhpf7LXkJM0y+6kMB0mvB9PlRJ1QqCfFLV6MgC70u/4 3z5w== X-Gm-Message-State: AOJu0YyS8QNJZD36XWS0aLSvfv0XDmDsfflzpJMF2RhRrS/ZFTQMsH1N KZqbDh+53BDvwcREa/KaXAWvb4e6HiHr2J5NuQX1JvcbNPNYHCz1X/TcDrjV4HVY3y1FDqQiV2q R X-Gm-Gg: ASbGncvZVsxDvZcsS1tnJEPtthkTMjxefpufHjs+dkKfhgZW2UQO55GYpwOkwxXAJeO 5K3dQvzQLZ84lq84Te/fn0Iz37e2n2NJ5zObC/V2F6ROIqULp79KCIkvfY2SFzuFk8xeDkJH/yL B3A7DDB/iHokO3F9Wnrqy13Azrz76ZctbM79PFqg+F1X474IeeeV3G/P71stwlOfrl3u3rMoe71 /sP2ZQfdLNs5uQVorVponp27g5kwnrZtqXoqIaK9NrUDqBYGZPkyOIDpsTN8Atijckc2eJf0bOV CtN31sUy1akSG4XxDoZY5KHOO+S9uBipgkpUp02qSQo= X-Google-Smtp-Source: AGHT+IG0kV+b/9mbeBsZ6EulQJW96YRtgdh0hbcUnanb8I/4a3Ck5d/RiB5XnBEm3PcRdoYrtZULOA== X-Received: by 2002:a17:902:d485:b0:224:1609:a74a with SMTP id d9443c01a7336-22dc6a6851emr189852765ad.34.1745930673749; Tue, 29 Apr 2025 05:44:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza , Alistair Francis Subject: [PATCH v5 3/9] target/riscv/kvm: turn u32/u64 reg functions into macros Date: Tue, 29 Apr 2025 09:44:15 -0300 Message-ID: <20250429124421.223883-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429124421.223883-1-dbarboza@ventanamicro.com> References: <20250429124421.223883-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745930760502019000 Content-Type: text/plain; charset="utf-8" This change is motivated by a future change w.r.t CSRs management. We want to handle them the same way as KVM extensions, i.e. a static array with KVMCPUConfig objs that will be read/write during init and so on. But to do that properly we must be able to declare a static array that hold KVM regs. C does not allow to init static arrays and use functions as initializers, e.g. we can't do: .kvm_reg_id =3D kvm_riscv_reg_id_ulong(...) When instantiating the array. We can do that with macros though, so our goal is turn kvm_riscv_reg_ulong() in a macro. It is cleaner to turn every other reg_id_*() function in macros, and ulong will end up using the macros for u32 and u64, so we'll start with them. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 6ba122f360..c91ecdfe59 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -58,6 +58,12 @@ void riscv_kvm_aplic_request(void *opaque, int irq, int = level) =20 static bool cap_has_mp_state; =20 +#define KVM_RISCV_REG_ID_U32(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U32 = | \ + type | idx) + +#define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 = | \ + type | idx) + static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, uint64_t idx) { @@ -76,16 +82,6 @@ static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *en= v, uint64_t type, return id; } =20 -static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) -{ - return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; -} - -static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) -{ - return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; -} - static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) { uint64_t size_ctz =3D __builtin_ctz(size_b); @@ -119,12 +115,12 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ KVM_REG_RISCV_CONFIG_REG(name)) =20 -#define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ +#define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ KVM_REG_RISCV_TIMER_REG(name)) =20 -#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) +#define RISCV_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx) =20 -#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) +#define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) =20 #define RISCV_VECTOR_CSR_REG(env, name) \ kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ --=20 2.49.0 From nobody Sat Nov 15 22:35:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745930831; cv=none; d=zohomail.com; s=zohoarc; b=YBkEEn0zR1PjRO43SA0soJFimL8sl4ZXm24hOy82zeunDasUkFs5euLpACsK6qKRjc1y90SCZHu4Gexp3dbhWzBS94rfSOfT7DY69iBXRJHXS7p+trt18sIM77uHHeBMhyhIGPQfj6daIiH/KJBPE02PDJO96Iet+6Ii59a5z/8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745930831; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6O9BQcppYQehYYe2pBbEGo5x9xXyQ5zE6+droa5J8xU=; b=Dpqjex7TZsRiHKt9K/54yK4/30rvvM4ottVxpa7QpfV5moeerDaxjR3lJvOiSpHB/SIwhS08IyVoTWy0zkdfWHXACeo4iiDYXRe/xi8QmtZuoamW0yGtfuHG3nK5DtqJBxVuV+/p3UNKZPSmKBqRzLaHiKi82DYgk50uKWDdTY0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745930831085919.9780558101457; Tue, 29 Apr 2025 05:47:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kKO-0002Ri-Nt; Tue, 29 Apr 2025 08:44:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kKK-0002IC-Of for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:44 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kKF-0004M9-DG for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:44 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-3081fe5987eso5594312a91.3 for ; Tue, 29 Apr 2025 05:44:37 -0700 (PDT) Received: from grind.. ([152.234.125.33]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309ef04ba89sm11001161a91.10.2025.04.29.05.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 05:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745930676; x=1746535476; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6O9BQcppYQehYYe2pBbEGo5x9xXyQ5zE6+droa5J8xU=; b=QIuf3yJxr17mmrB+eJFHmzxaiZyifrbqkTBqe41SoV9J4WtCWc44xL7DWhqoPctztl gY1cCq08a3Eb5O/OyDJLM+dfwC9lqSMGmfu6YmDHC9kJ2fD1j9eIeDgEz/yUOqp+VdX7 NOsEY7aSkaU8srElYdpCNA+Jey+xQi40xtVTraAVENFgI9NLcxRLJNxxEyVeVI75uIwy 6IMv5dz0pZUQDDNBLPjLE0YXEkY2teD8EOHGV3Hf0yw9TaKdCy43Nvg9rgpO3XnLyhqp YvJJzYFA920fBGduYRX3H1mZjpF3gRR6HTpxZM2sEN4Vr/RcagPxjAocuLH3VZO0m9u1 Mh8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745930676; x=1746535476; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6O9BQcppYQehYYe2pBbEGo5x9xXyQ5zE6+droa5J8xU=; b=ILW62/peoSvOVMIkS23bDp4t5ZvquAv/RqcvTVrgRNarc4W4jk/Y40MZzTxcV2T1CG MNMP51Df1F+4jf2MpXJRDG0RPDlpHcJ/x10tdBszExUsr15ljYaiqkmeo7r4nQiP+say KbKfbGiL9NELveDgMVgpdqU+hAEuQeK4TyWENe19t5cQZ00p+5TtLxJ3OKiqDODrz8cp 3aZtTmb/qje3VcE6UtuC/YfMVg09I8EoEUGsb2iFkTAq3vghCnyvhzPk+KUmmnJPJPyK 0MBUvVo0lv+VPnRCAABU4wvJDewzi4TYzoBhenQQMCg0uNL1EJHixahJbqcbkjkhmT0+ DesQ== X-Gm-Message-State: AOJu0YzuRZknp9xcNccqXtxeLNoOjW5e4XrRuJxbTIx+uW7p4RnkBzzH whD6SEKmEhsZ7m2udGHhGC3yvBC8EjejZn5bJBLCQGNg/OF08HrrRd3j8rhSQpRT6M/zA9eOB4d T X-Gm-Gg: ASbGncvYuHqwxJNaKzfwt5g0K77xJ103SsOw6QkXhJNUAMjRo0kGfZhTTG/Ek0ec+Yx 5m3cbAY83N2OYkW3b1gXj2im+IQmthEoMgKDL/qMuMjdvq1HjGBbsKYbMDQ1YomtVXGR/DY10Uv P8fq7b7LNxPUCvTVezaJnAX5PpEyHCS0/FdRn6ehxR+i4uBmWY/LDl6xvkNqyJLcZTwRQhcucrM O/bnbdv27qh/8roH7BG1qOWmhIg3YWPZnhRdNty3lSs+mSR99ddp6mXqdu/PwuUjR8oDCKuAGHd VKtckou02LrN/tXBU7r0519g70K8sHReQZH0g1yd9Jk= X-Google-Smtp-Source: AGHT+IFARcpM4i66wzSRF0yTPGLGk/cTMa7KqOyPEfSF/RNOBv52kd930ifx+ZzfTdKhv02pulSHAg== X-Received: by 2002:a17:90b:2f0f:b0:2ef:19d0:2261 with SMTP id 98e67ed59e1d1-30a013357bcmr21341318a91.16.1745930676143; Tue, 29 Apr 2025 05:44:36 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza , Alistair Francis Subject: [PATCH v5 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro Date: Tue, 29 Apr 2025 09:44:16 -0300 Message-ID: <20250429124421.223883-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429124421.223883-1-dbarboza@ventanamicro.com> References: <20250429124421.223883-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745930833438019000 Content-Type: text/plain; charset="utf-8" We need the reg_id_ulong() helper to be a macro to be able to create a static array of KVMCPUConfig that will hold CSR information. Despite the amount of changes all of them are tedious/trivial: - replace instances of "kvm_riscv_reg_id_ulong" with "KVM_RISCV_REG_ID_ULONG"; - RISCV_CORE_REG(), RISCV_CSR_REG(), RISCV_CONFIG_REG() and RISCV_VECTOR_CSR_REG() only receives one 'name' arg. Remove unneeded 'env' variables when applicable. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 99 ++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 58 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c91ecdfe59..fd66bc1759 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -64,23 +64,11 @@ static bool cap_has_mp_state; #define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 = | \ type | idx) =20 -static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, - uint64_t idx) -{ - uint64_t id =3D KVM_REG_RISCV | type | idx; - - switch (riscv_cpu_mxl(env)) { - case MXL_RV32: - id |=3D KVM_REG_SIZE_U32; - break; - case MXL_RV64: - id |=3D KVM_REG_SIZE_U64; - break; - default: - g_assert_not_reached(); - } - return id; -} +#if defined(TARGET_RISCV64) +#define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U64(type, idx) +#else +#define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U32(type, idx) +#endif =20 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) { @@ -103,16 +91,16 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, return kvm_encode_reg_size_id(id, size_b); } =20 -#define RISCV_CORE_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ +#define RISCV_CORE_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, \ KVM_REG_RISCV_CORE_REG(name)) =20 -#define RISCV_CSR_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ +#define RISCV_CSR_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CSR, \ KVM_REG_RISCV_CSR_REG(name)) =20 -#define RISCV_CONFIG_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ +#define RISCV_CONFIG_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, \ KVM_REG_RISCV_CONFIG_REG(name)) =20 #define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ @@ -122,13 +110,13 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, =20 #define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) =20 -#define RISCV_VECTOR_CSR_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ +#define RISCV_VECTOR_CSR_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ KVM_REG_RISCV_VECTOR_CSR_REG(name)) =20 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ do { \ - int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(csr), ®); \ if (_ret) { \ return _ret; \ } \ @@ -136,7 +124,7 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, =20 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ do { \ - int _ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(csr), ®); \ if (_ret) { \ return _ret; \ } \ @@ -244,7 +232,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu= , CPUState *cs) =20 /* If we're here we're going to disable the MISA bit */ reg =3D 0; - id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, misa_cfg->kvm_reg_id); ret =3D kvm_set_one_reg(cs, id, ®); if (ret !=3D 0) { @@ -430,7 +418,6 @@ static KVMCPUConfig kvm_sbi_dbcn =3D { =20 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) { - CPURISCVState *env =3D &cpu->env; uint64_t id, reg; int i, ret; =20 @@ -441,7 +428,7 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *= cpu, CPUState *cs) continue; } =20 - id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, multi_ext_cfg->kvm_reg_id); reg =3D kvm_cpu_cfg_get(cpu, multi_ext_cfg); ret =3D kvm_set_one_reg(cs, id, ®); @@ -566,14 +553,14 @@ static int kvm_riscv_get_regs_core(CPUState *cs) target_ulong reg; CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 - ret =3D kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); + ret =3D kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); if (ret) { return ret; } env->pc =3D reg; =20 for (i =3D 1; i < 32; i++) { - uint64_t id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); + uint64_t id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); ret =3D kvm_get_one_reg(cs, id, ®); if (ret) { return ret; @@ -592,13 +579,13 @@ static int kvm_riscv_put_regs_core(CPUState *cs) CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 reg =3D env->pc; - ret =3D kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); + ret =3D kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); if (ret) { return ret; } =20 for (i =3D 1; i < 32; i++) { - uint64_t id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); + uint64_t id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); reg =3D env->gpr[i]; ret =3D kvm_set_one_reg(cs, id, ®); if (ret) { @@ -796,26 +783,26 @@ static int kvm_riscv_get_regs_vector(CPUState *cs) return 0; } =20 - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); if (ret) { return ret; } env->vstart =3D reg; =20 - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); if (ret) { return ret; } env->vl =3D reg; =20 - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); if (ret) { return ret; } env->vtype =3D reg; =20 if (kvm_v_vlenb.supported) { - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®= ); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); if (ret) { return ret; } @@ -853,26 +840,26 @@ static int kvm_riscv_put_regs_vector(CPUState *cs) } =20 reg =3D env->vstart; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); if (ret) { return ret; } =20 reg =3D env->vl; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); if (ret) { return ret; } =20 reg =3D env->vtype; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); if (ret) { return ret; } =20 if (kvm_v_vlenb.supported) { reg =3D cpu->cfg.vlenb; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®= ); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); =20 for (int i =3D 0; i < 32; i++) { /* @@ -951,25 +938,24 @@ static void kvm_riscv_destroy_scratch_vcpu(KVMScratch= CPU *scratch) =20 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcp= u) { - CPURISCVState *env =3D &cpu->env; struct kvm_one_reg reg; int ret; =20 - reg.id =3D RISCV_CONFIG_REG(env, mvendorid); + reg.id =3D RISCV_CONFIG_REG(mvendorid); reg.addr =3D (uint64_t)&cpu->cfg.mvendorid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { error_report("Unable to retrieve mvendorid from host, error %d", r= et); } =20 - reg.id =3D RISCV_CONFIG_REG(env, marchid); + reg.id =3D RISCV_CONFIG_REG(marchid); reg.addr =3D (uint64_t)&cpu->cfg.marchid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { error_report("Unable to retrieve marchid from host, error %d", ret= ); } =20 - reg.id =3D RISCV_CONFIG_REG(env, mimpid); + reg.id =3D RISCV_CONFIG_REG(mimpid); reg.addr =3D (uint64_t)&cpu->cfg.mimpid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { @@ -984,7 +970,7 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, struct kvm_one_reg reg; int ret; =20 - reg.id =3D RISCV_CONFIG_REG(env, isa); + reg.id =3D RISCV_CONFIG_REG(isa); reg.addr =3D (uint64_t)&env->misa_ext_mask; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); =20 @@ -1001,11 +987,10 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *c= pu, static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvm= cpu, KVMCPUConfig *cbomz_cfg) { - CPURISCVState *env =3D &cpu->env; struct kvm_one_reg reg; int ret; =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, cbomz_cfg->kvm_reg_id); reg.addr =3D (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); @@ -1019,7 +1004,6 @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cp= u, KVMScratchCPU *kvmcpu, static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) { - CPURISCVState *env =3D &cpu->env; uint64_t val; int i, ret; =20 @@ -1027,7 +1011,7 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *= cpu, KVMCPUConfig *multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; struct kvm_one_reg reg; =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, multi_ext_cfg->kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); @@ -1159,7 +1143,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) =20 for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; - reg_id =3D kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, + reg_id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, multi_ext_cfg->kvm_reg_id); reg_search =3D bsearch(®_id, reglist->reg, reglist->n, sizeof(uint64_t), uint64_cmp); @@ -1338,12 +1322,11 @@ void kvm_arch_init_irq_routing(KVMState *s) =20 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) { - CPURISCVState *env =3D &cpu->env; target_ulong reg; uint64_t id; int ret; =20 - id =3D RISCV_CONFIG_REG(env, mvendorid); + id =3D RISCV_CONFIG_REG(mvendorid); /* * cfg.mvendorid is an uint32 but a target_ulong will * be written. Assign it to a target_ulong var to avoid @@ -1355,13 +1338,13 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, = CPUState *cs) return ret; } =20 - id =3D RISCV_CONFIG_REG(env, marchid); + id =3D RISCV_CONFIG_REG(marchid); ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.marchid); if (ret !=3D 0) { return ret; } =20 - id =3D RISCV_CONFIG_REG(env, mimpid); + id =3D RISCV_CONFIG_REG(mimpid); ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); =20 return ret; @@ -1911,7 +1894,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, E= rror **errp) if (cpu->cfg.ext_zicbom && riscv_cpu_option_set(kvm_cbom_blocksize.name)) { =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, kvm_cbom_blocksize.kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); @@ -1930,7 +1913,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, E= rror **errp) if (cpu->cfg.ext_zicboz && riscv_cpu_option_set(kvm_cboz_blocksize.name)) { =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, kvm_cboz_blocksize.kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); --=20 2.49.0 From nobody Sat Nov 15 22:35:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745930791; cv=none; d=zohomail.com; s=zohoarc; b=WXnNmDewMVeGT+LfPXJdquwzQajBa26g06+DcZO+FUoS+I5oUJ1Sk8sgqqR4t40QU6ZYj5xhCx68/mosIH9KhJZmsS/wNoN1k8vo2CE/jAE5MkKSjdqaWpnr35j73CTv/aErgI2b6X7xOwAb/Y1Ql7ZhZIlnAn1x3KGvoszq3aY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745930791; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nOpiOx5SFtyMw4NePdfRwxvIac5AkMf5xXQqY8g3kvc=; b=XqkPCiGMFaKBiymfj0RvXQL9Pf0TAvFqL/0CLH78ETu8hBv786ljUaTwb82dpOgoXCMfL6tGy7VRF6hb+syEf3o1dAsl0QgGRfvfv15q7H7gJESxzUdFWMd1M6X4eSTfHxPmLWfg0msFLaXlkSnso2EPGC/Y4UKp3Lx68A2gXd8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745930791702678.9604853901081; Tue, 29 Apr 2025 05:46:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kKK-0002Hz-PL; Tue, 29 Apr 2025 08:44:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kKJ-0002C3-58 for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:43 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kKG-0004MS-HU for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:42 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-301918a4e3bso6571829a91.3 for ; Tue, 29 Apr 2025 05:44:39 -0700 (PDT) Received: from grind.. ([152.234.125.33]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309ef04ba89sm11001161a91.10.2025.04.29.05.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 05:44:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745930678; x=1746535478; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nOpiOx5SFtyMw4NePdfRwxvIac5AkMf5xXQqY8g3kvc=; b=Aai25GKrQ+YOkBpf4WTByvm84Pyoopetx99UwdF8oYy+AOjRyGP6r/TTDGAU4KX9cH ip4WqJspkggDWsXTX+FeC8GVlCd8MaIXT+xvYJj9vTlYsCNeEVuOgr5gINaG5GYhY2ww UZZS4s/InOxdTgp37gq1huCuTVbEZhurMRWkYTsjCyR+VXyKLdJMxpmy2YVPsbm3ufNr Ny/fuiZzQM8kXsBuVt6e+biyh98e6j3xjAQcp4xIWlT1w8go3srpFln2BUUvBXkuG278 iQ/e3vYCRymwgPccJww0gM6L4HMhJgV2+RHcnw84I4hdJTv77snzHQszv0htAC+afu7v yZnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745930678; x=1746535478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nOpiOx5SFtyMw4NePdfRwxvIac5AkMf5xXQqY8g3kvc=; b=ajVb5nCWoBQgbrHVRpm8fDbS9/2+nge3TOzKiVzO9oZqMsjlnh6lvwTU9xLXVta3rT aiN5WMDE6JnbVUTHM14rxeqBDr1YiENX5mOBuMnoIPJzSqCKNLjmvCtUGLWaWvB7rt6j fq2krCfVzogw61d/UHxKY4UdkcEtXcfMhtL9Vt8OfYYJl80JVRmLTr919OLiN14+t0Po xJxhw0E0SRGYgqLop8SCxQvXrpQ7aYvXXo3JM3MOUyMzlM+u2AZUGA/fRfnyPVDkFwaY yXJODJV0P98AZPr/vibB1lFMJGSHtjOBi/hQMqzBkBod860S4vkWDMhUZXxN4ITtKUp7 5Jjw== X-Gm-Message-State: AOJu0Yxt1idqwSJ4H4kbG/3OmaccS1Y0sgXsiV6hEGNEzR7gar+EbB+s De9CqEOGXFEToZMwLZOfubgMdTDjVv25JPbglnoDV7ZmUTjmtXKGIPr6a3/jwZDCIXw0Yb1kjCD u X-Gm-Gg: ASbGncsfGRsXF4zeGSAKg0rmOfaGOr3MKjGrdkd8zJ85MNrBMmovzd4QjqT1KnPN29q l4giFxOWbYlJQhbCiInLE6QQnDpPy+926+mggCGChJd4XNe9DnKrMD5LSWRpH0ZbhaNzjZLE9Cg HwvpxJaeOqPuF43xXPFPglODUN1eVc3ykoxL7Na1WfZCsuab+mvO8J8FNG6nM2fy5f0k65WUiU+ OGr255Sa4yjaY8nl+vjiYWoYKQPqVn4PHP11W+0uSKa3cq6KQT8SsXph19nTM20k5JaTnSJFW8k BOEgEhSDM/KGHnyHIlSwybDMjctkHFGu6rLOiSEMzUs= X-Google-Smtp-Source: AGHT+IEvfFMfGfPleYPZOIZ4DWF5BpD5vZvaGo2grh5+/jeTqOFfjkH3Sz2Jkz92EWTDqcZ2zmpEGw== X-Received: by 2002:a17:90b:1c09:b0:2ff:64c3:3bd4 with SMTP id 98e67ed59e1d1-30a2159bd80mr4702056a91.31.1745930678556; Tue, 29 Apr 2025 05:44:38 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza , Alistair Francis Subject: [PATCH v5 5/9] target/riscv/kvm: add kvm_csr_cfgs[] Date: Tue, 29 Apr 2025 09:44:17 -0300 Message-ID: <20250429124421.223883-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429124421.223883-1-dbarboza@ventanamicro.com> References: <20250429124421.223883-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745930792386019000 Content-Type: text/plain; charset="utf-8" At this moment we're not checking if the host has support for any specific CSR before doing get/put regs. This will cause problems if the host KVM doesn't support it (see [1] as an example). We'll use the same approach done with the CPU extensions: read all known KVM CSRs during init() to check for availability, then read/write them if they are present. This will be made by either using get-reglist or by directly reading the CSRs. For now we'll just convert the CSRs to use a kvm_csr_cfg[] array, reusing the same KVMCPUConfig abstraction we use for extensions, and use the array in (get|put)_csr_regs() instead of manually listing them. A lot of boilerplate will be added but at least we'll automate the get/put procedure for CSRs, i.e. adding a new CSR in the future will be a matter of adding it in kvm_csr_regs[] and everything else will be taken care of. Despite all the code changes no behavioral change is made. [1] https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBL= bLKhfv=3D+jb0SYAw@mail.gmail.com/ Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/kvm/kvm-cpu.c | 121 ++++++++++++++++++++++++++----------- 2 files changed, 86 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 679f417336..f5a60d0c52 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -79,6 +79,7 @@ const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); =20 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) +#define ENV_CSR_OFFSET(_csr) offsetof(CPURISCVState, _csr) =20 typedef struct riscv_cpu_profile { struct riscv_cpu_profile *u_parent; diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index fd66bc1759..f881e7eb5d 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -114,22 +114,6 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ KVM_REG_RISCV_VECTOR_CSR_REG(name)) =20 -#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ - do { \ - int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(csr), ®); \ - if (_ret) { \ - return _ret; \ - } \ - } while (0) - -#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ - do { \ - int _ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(csr), ®); \ - if (_ret) { \ - return _ret; \ - } \ - } while (0) - #define KVM_RISCV_GET_TIMER(cs, name, reg) \ do { \ int ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ @@ -251,6 +235,53 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cp= u, CPUState *cs) } } =20 +#define KVM_CSR_CFG(_name, _env_prop, reg_id) \ + {.name =3D _name, .offset =3D ENV_CSR_OFFSET(_env_prop), \ + .kvm_reg_id =3D reg_id} + +static KVMCPUConfig kvm_csr_cfgs[] =3D { + KVM_CSR_CFG("sstatus", mstatus, RISCV_CSR_REG(sstatus)), + KVM_CSR_CFG("sie", mie, RISCV_CSR_REG(sie)), + KVM_CSR_CFG("stvec", stvec, RISCV_CSR_REG(stvec)), + KVM_CSR_CFG("sscratch", sscratch, RISCV_CSR_REG(sscratch)), + KVM_CSR_CFG("sepc", sepc, RISCV_CSR_REG(sepc)), + KVM_CSR_CFG("scause", scause, RISCV_CSR_REG(scause)), + KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)), + KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)), + KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)), +}; + +static void *kvmconfig_get_env_addr(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) +{ + return (void *)&cpu->env + csr_cfg->offset; +} + +static uint32_t kvm_cpu_csr_get_u32(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) +{ + uint32_t *val32 =3D kvmconfig_get_env_addr(cpu, csr_cfg); + return *val32; +} + +static uint64_t kvm_cpu_csr_get_u64(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) +{ + uint64_t *val64 =3D kvmconfig_get_env_addr(cpu, csr_cfg); + return *val64; +} + +static void kvm_cpu_csr_set_u32(RISCVCPU *cpu, KVMCPUConfig *csr_cfg, + uint32_t val) +{ + uint32_t *val32 =3D kvmconfig_get_env_addr(cpu, csr_cfg); + *val32 =3D val; +} + +static void kvm_cpu_csr_set_u64(RISCVCPU *cpu, KVMCPUConfig *csr_cfg, + uint64_t val) +{ + uint64_t *val64 =3D kvmconfig_get_env_addr(cpu, csr_cfg); + *val64 =3D val; +} + #define KVM_EXT_CFG(_name, _prop, _reg_id) \ {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .kvm_reg_id =3D _reg_id} @@ -598,34 +629,52 @@ static int kvm_riscv_put_regs_core(CPUState *cs) =20 static int kvm_riscv_get_regs_csr(CPUState *cs) { - CPURISCVState *env =3D &RISCV_CPU(cs)->env; + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint64_t reg; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; =20 - KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); - KVM_RISCV_GET_CSR(cs, env, sie, env->mie); - KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); - KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); - KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); - KVM_RISCV_GET_CSR(cs, env, scause, env->scause); - KVM_RISCV_GET_CSR(cs, env, stval, env->stval); - KVM_RISCV_GET_CSR(cs, env, sip, env->mip); - KVM_RISCV_GET_CSR(cs, env, satp, env->satp); + ret =3D kvm_get_one_reg(cs, csr_cfg->kvm_reg_id, ®); + if (ret) { + return ret; + } + + if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { + kvm_cpu_csr_set_u32(cpu, csr_cfg, reg); + } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { + kvm_cpu_csr_set_u64(cpu, csr_cfg, reg); + } else { + g_assert_not_reached(); + } + } =20 return 0; } =20 static int kvm_riscv_put_regs_csr(CPUState *cs) { - CPURISCVState *env =3D &RISCV_CPU(cs)->env; + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint64_t reg; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; + + if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { + reg =3D kvm_cpu_csr_get_u32(cpu, csr_cfg); + } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { + reg =3D kvm_cpu_csr_get_u64(cpu, csr_cfg); + } else { + g_assert_not_reached(); + } =20 - KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); - KVM_RISCV_SET_CSR(cs, env, sie, env->mie); - KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); - KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); - KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); - KVM_RISCV_SET_CSR(cs, env, scause, env->scause); - KVM_RISCV_SET_CSR(cs, env, stval, env->stval); - KVM_RISCV_SET_CSR(cs, env, sip, env->mip); - KVM_RISCV_SET_CSR(cs, env, satp, env->satp); + ret =3D kvm_set_one_reg(cs, csr_cfg->kvm_reg_id, ®); + if (ret) { + return ret; + } + } =20 return 0; } --=20 2.49.0 From nobody Sat Nov 15 22:35:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([152.234.125.33]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309ef04ba89sm11001161a91.10.2025.04.29.05.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 05:44:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745930681; x=1746535481; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R37KMDljb4CsAfrDdBRy5Wnf5bfrROiq1X3f4Wy4iUE=; b=hMkgP6tPYe/nYoZ2B03YpckCh0asnSINM0tSY8K7f265//siB2uKIqML1UU4TlkmF7 k08QbDWzsXoovsZg4ZYRSnKPSAaSBHJfZpexbX9aV8ybigkF8gpsrerZ8isH3Js1OcT5 BO3OT9rvi2z441Ejt6nLUeGv4rWvFiG7gvUFHaFyrO4DgFBAkgnrblEYKBJlsy76v7IE iUrQS0+m/ZMm7YcTLWJ/fFs6WKfk+djg+LFU5D0la2/kZggXNk7+VUs6pPyl9Tg0wfut ZTABqDSuC7Spu3V1rAV9p5++RDHYUOeoXoa99XmcJUB5l7sTbe41nymMdEbQDcHWdmbV GUmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745930681; x=1746535481; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R37KMDljb4CsAfrDdBRy5Wnf5bfrROiq1X3f4Wy4iUE=; b=OgfjC7L0O141NPecWgodLThucBROmfKL8qHFj9APXRp5swMbXo9hHCClaqqGwGLMiv +CpwiV7E12fUnAAao09olTmizPs3OlsfeXd2PHtIDkd+92JwnIDm+nfSpXw6ISQQiOAr TPX7N9d71zme5LDtv/vajGEXR3+L7e5Br47zkFjH/oNAKA9BCVWqcRdMcqJBwKPqgT3d 3G73+JOqUvLT2Zacc7MtSN1mPBKIcEBcSpUbZYjYwZinirM5gQDtI3+sIEmGiZZw+byb 44Q5bihzqZtnz1zxraXtj95HHimeCGlKaVwuxR0eI8IWUCH7HIIpumqmu7RodtBJrp4z wAkA== X-Gm-Message-State: AOJu0YwqIPu7UWNDb0+6AWkUVplH26pbypZFcEWNDqHpcDPwgtWNeE3h gL8zmhxelTwjgKLDHSF0YkthTMCcTAy8FxAcr7zKkoNyuh9uoUR81/MPEp94t6JZ7F10xMDOBMD D X-Gm-Gg: ASbGncuawJR3QXbxM2zFWL7EQ/cT8ldQ9rh90Qt26jHxJ3ODD5oGmLQpja/bjz2GD4H A1+rvY1dIVSX2UjTTWhO52JJevEH8GwHgvmttYwrz3ntQXKJXydErBoljYKi4Yovo/KRyigMeAC GTrBwGebAKdjIf4Tx1tblyGhemBTFusvJYzIOXdHDmw8wnnZYQpnpMoxZ3dylzs9jS2iTesv9Ed fwbsEImiP/Y1lGHJp73YM7m7QPFdl6WueylxsFjvkSgEsYSqiEALusAMZoejIA2ji4J7lcY9o7J TL9d/uiD2YQORqHNL2L6o2XO65qdnVMosOiZj62E3SeIUUAI2TEYCg== X-Google-Smtp-Source: AGHT+IEL7xROVk7A114uX5GJ4gtABYjYPFKjD/BY6PAVzNL2L5h33hYbGTAsByTFWNnAKDGAj1PocQ== X-Received: by 2002:a17:90b:4c09:b0:2ef:2f49:7d7f with SMTP id 98e67ed59e1d1-30a2155ece6mr6017273a91.18.1745930680952; Tue, 29 Apr 2025 05:44:40 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza , Andrea Bolognani Subject: [PATCH v5 6/9] target/riscv/kvm: do not read unavailable CSRs Date: Tue, 29 Apr 2025 09:44:18 -0300 Message-ID: <20250429124421.223883-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429124421.223883-1-dbarboza@ventanamicro.com> References: <20250429124421.223883-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745930787688019100 Content-Type: text/plain; charset="utf-8" [1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6. This happens because the kernel does not know 'senvcfg', making it unable to boot because QEMU is reading/wriiting it without any checks. After converting the CSRs to do "automated" get/put reg procedures in the previous patch we can now scan for availability. Two functions are created: - kvm_riscv_read_csr_cfg_legacy() will check if the CSR exists by brute forcing KVM_GET_ONE_REG in each one of them, interpreting an EINVAL return as indication that the CSR isn't available. This will be use in absence of KVM_GET_REG_LIST; - kvm_riscv_read_csr_cfg() will use the existing result of get_reg_list to check if the CSRs ids are present. kvm_riscv_init_multiext_cfg() is now kvm_riscv_init_cfg() to reflect that the function is also dealing with CSRs. [1] https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBL= bLKhfv=3D+jb0SYAw@mail.gmail.com/ Fixes: 4db19d5b21 ("target/riscv/kvm: add missing KVM CSRs") Reported-by: Andrea Bolognani Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 62 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 3 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index f881e7eb5d..1ce747d047 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -636,6 +636,10 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; =20 + if (!csr_cfg->supported) { + continue; + } + ret =3D kvm_get_one_reg(cs, csr_cfg->kvm_reg_id, ®); if (ret) { return ret; @@ -662,6 +666,10 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; =20 + if (!csr_cfg->supported) { + continue; + } + if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { reg =3D kvm_cpu_csr_get_u32(cpu, csr_cfg); } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { @@ -1090,6 +1098,32 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU = *cpu, } } =20 +static void kvm_riscv_read_csr_cfg_legacy(KVMScratchCPU *kvmcpu) +{ + uint64_t val; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; + struct kvm_one_reg reg; + + reg.id =3D csr_cfg->kvm_reg_id; + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + if (errno =3D=3D EINVAL) { + csr_cfg->supported =3D false; + } else { + error_report("Unable to read KVM CSR %s: %s", + csr_cfg->name, strerror(errno)); + exit(EXIT_FAILURE); + } + } else { + csr_cfg->supported =3D true; + } + } +} + static int uint64_cmp(const void *a, const void *b) { uint64_t val1 =3D *(const uint64_t *)a; @@ -1146,7 +1180,26 @@ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMS= cratchCPU *kvmcpu, } } =20 -static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmc= pu) +static void kvm_riscv_read_csr_cfg(struct kvm_reg_list *reglist) +{ + struct kvm_reg_list *reg_search; + uint64_t reg_id; + + for (int i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; + + reg_id =3D csr_cfg->kvm_reg_id; + reg_search =3D bsearch(®_id, reglist->reg, reglist->n, + sizeof(uint64_t), uint64_cmp); + if (!reg_search) { + continue; + } + + csr_cfg->supported =3D true; + } +} + +static void kvm_riscv_init_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) { g_autofree struct kvm_reg_list *reglist =3D NULL; KVMCPUConfig *multi_ext_cfg; @@ -1163,7 +1216,9 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) * (EINVAL). Use read_legacy() in this case. */ if (errno =3D=3D EINVAL) { - return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); + kvm_riscv_read_multiext_legacy(cpu, kvmcpu); + kvm_riscv_read_csr_cfg_legacy(kvmcpu); + return; } else if (errno !=3D E2BIG) { /* * E2BIG is an expected error message for the API since we @@ -1226,6 +1281,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) } =20 kvm_riscv_check_sbi_dbcn_support(cpu, reglist); + kvm_riscv_read_csr_cfg(reglist); } =20 static void riscv_init_kvm_registers(Object *cpu_obj) @@ -1239,7 +1295,7 @@ static void riscv_init_kvm_registers(Object *cpu_obj) =20 kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); - kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); + kvm_riscv_init_cfg(cpu, &kvmcpu); =20 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); } --=20 2.49.0 From nobody Sat Nov 15 22:35:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745930866; cv=none; d=zohomail.com; s=zohoarc; b=PHmn3ek2FWxJczr+MbRQJISbx/5+PGv3GJUaDR1ho3DQdV46lGHILYmlBSq/fGm1oB46uzR4JNA+w2lQjbpu5BsvdGi8wD0O8W0NNsCB1ZH+OEicCNRRtPkaAxYYual3mRfq7zBvoYjzo5RB4ySdnMQaydn5F0qMWWC6vCC0qGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745930866; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sqkSXWmlAzXCmkQApAbF+YpwERfG9A2hRBSgef/JTFs=; b=Vhvk4Z2Z0A/v9wUXKi6N+ed5x6YGaMQ/o+FaAsSXqhRA/lJLtZR+HcjDlc/i4CnxdE66DymERjUOPLyoSQZtrcPWPfm7hndK4ubzdgOP+xErgpUwULNIzYfivRoEIB31Kb6A8QUVw88OjPhEBVxJc2MaMYQpEhXWGNY11nkVBZg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174593086604768.32709018592357; Tue, 29 Apr 2025 05:47:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kKP-0002Ue-Ku; Tue, 29 Apr 2025 08:44:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kKO-0002TH-Ts for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:48 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kKL-0004N7-Iy for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:47 -0400 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-2ff6e91cff5so5471197a91.2 for ; Tue, 29 Apr 2025 05:44:45 -0700 (PDT) Received: from grind.. ([152.234.125.33]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309ef04ba89sm11001161a91.10.2025.04.29.05.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 05:44:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745930683; x=1746535483; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sqkSXWmlAzXCmkQApAbF+YpwERfG9A2hRBSgef/JTFs=; b=ZDok/Q5Cj78hcj7v68oV8h7G6ySTe+IUjExHRQR22BtwGFQE6iHl1tuQDUijJflFGv 8cPj9stRuir4JcDzGPSTvsjFi5sVCcJtIdaYPLC7EBm6mz6abDgy7RFhGgzWPJcPuQw/ ELZoG8vChgVYCGKn/moHkDh4r/QigA06KtAlNa3lkXB6vRlRFkHaSdqmqXtIhb9ZhUHa 5HOuYl6i+w34DDeOzH7wl5pIGb50Oz/dnHKmPimHMx8vEQHDu+21Miq+hFMx1KUOZHvE Pa1Q20wHErs3EOjQr0rRLiSTiGP1VeHigGIzjOskijtmbk/hsPRsPNHHG8Q0hZCLWfnp k1YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745930683; x=1746535483; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sqkSXWmlAzXCmkQApAbF+YpwERfG9A2hRBSgef/JTFs=; b=NDI/w06IPsxlI35nI35uXWUyia/v+ysN4J0MtV0rgW295UY7fdOARQUnru/kechdkK wseJ0Uf4Byp0fnVmJzmob/Xv6nRj1R9UbPmCxnXP7ESc5U/spxwfv16FJXK5hHFXbpOE bgS/C8xbYJhiy3ds+NSKQGQhG5RooTJOEvwOlZPbW1n2uZtc3uEACcfB0aUJ0GxVF3QQ V6DhjHyEJ0+0in8TlBinMwHpNC4HQGeks3lpxH2dFmMA6jormEzNKuH4Ls5MnwL6o0BA cyKTr4oqyDZTiaj+SvyTtiQEdtuMyiygf/1XWyivVBGRxhbPMa6g3z0oZOr/RNfk7IQi VaRQ== X-Gm-Message-State: AOJu0Yy1M+wyLKeVFTiUvzP5Cq+NunWk/Hq8IIqNaTpNClRFok1vuKoE bSyaMKKgOMQRa/Ukx9m0Z0LihAKTRrG6f6J8jI5LKaOS8pMKqriPe0HqL1GCB4AvxcBNXWpiZkS J X-Gm-Gg: ASbGncvnIjx0o9LKDtD9HWnooPsFA7u4b7AwZb0g+umZ8wTVLHEW0j1cbYoxxKyhfE8 h0DY+h10sRNLt/SaOPUPQS+Ew1HCn7kNHp16MKebtEy01wjDwBhjswSOLHUvvDi5CLzvlniipLi jHmtutCrFiNc1I3KEJi+qi7p7AuzczpylfS9BMw+5TZawjRJtCtboF1J3qnnXeyv+wOZGfgPaPj Uzu8yWRxxfW0TOyn7v7l7M9lNp693z2LWuw1VReFwA3LLk4N4cxlU4srjXjxaeYpDGlglmgACSR +1a4Vbl9+cm01NQhcQ/VOkagVnsbewj9UDPA6hmwCOU= X-Google-Smtp-Source: AGHT+IGRP37o9WXqP6qNkb4kWf2nc8/v/hyMZYH+atvtdw7PrOYEpLRly9pK/EhuHjgpSxrIIMrf9A== X-Received: by 2002:a17:90b:394d:b0:2ff:5357:1c7f with SMTP id 98e67ed59e1d1-30a215ac108mr4945816a91.30.1745930683201; Tue, 29 Apr 2025 05:44:43 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v5 7/9] target/riscv/kvm: add senvcfg CSR Date: Tue, 29 Apr 2025 09:44:19 -0300 Message-ID: <20250429124421.223883-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429124421.223883-1-dbarboza@ventanamicro.com> References: <20250429124421.223883-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745930867681019100 Content-Type: text/plain; charset="utf-8" We're missing the senvcfg CSRs which is already present in the KVM UAPI. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 1ce747d047..5efee8adb2 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -249,6 +249,7 @@ static KVMCPUConfig kvm_csr_cfgs[] =3D { KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)), KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)), KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)), + KVM_CSR_CFG("senvcfg", senvcfg, RISCV_CSR_REG(senvcfg)), }; =20 static void *kvmconfig_get_env_addr(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) @@ -698,6 +699,7 @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env) env->stval =3D 0; env->mip =3D 0; env->satp =3D 0; + env->senvcfg =3D 0; } =20 static int kvm_riscv_get_regs_fp(CPUState *cs) --=20 2.49.0 From nobody Sat Nov 15 22:35:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745930830; cv=none; d=zohomail.com; s=zohoarc; b=cmb2o4lCF8esfYF73XP8Lr4ii3oMXA0Edw+h7Ur3xwEyEl3D+CGEEPTpoZxcj1PJ4ESfQ8Of3gZO2RvbanAOEYcT2Y3ciZzxxQewBGl5j0zm88B0tGz2KwfwRAEijGi6GP9CI7AF3OefmL9iM9BxaGSGk8eAzQk4Pd4G89x1LGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745930830; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iLAKtSByZPkbwLOMWEWkl5uORyVUUQ5Q0ynhQjz8M4I=; b=O4KXef5W0f+XvrJyeRmAM+tOr8ZFn6aLdS3xYJjXjSrCinz2wIu7N8i8k4AMVkp+5BwWD+P/reZq8mDbJfGO/09zSwtGelj2v3FGnC90YN5Ozx0l5ZpAF1GEygdlXxWpBwBkZhlzCt8c5V2PPI/PHZsGZOBLbgS16pgizCdgeEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745930830377796.2666198004509; Tue, 29 Apr 2025 05:47:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kKZ-0002jW-Kr; Tue, 29 Apr 2025 08:44:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kKQ-0002Ya-MQ for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:51 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kKO-0004NV-Nt for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:50 -0400 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-30820167b47so5819357a91.0 for ; Tue, 29 Apr 2025 05:44:47 -0700 (PDT) Received: from grind.. ([152.234.125.33]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309ef04ba89sm11001161a91.10.2025.04.29.05.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 05:44:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745930686; x=1746535486; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iLAKtSByZPkbwLOMWEWkl5uORyVUUQ5Q0ynhQjz8M4I=; b=egbJykF1AipJY/c7bnE4N0w0UpykP0WrDbtdhjQVAzW4DyJGrjKTsJet1vDbS2gwuF eQqC9jhtBNgBeFtjQ9Vh12LLv+fRuJhMEXmWZjZ1wPBVA3goDE2skdg1m/ljoXWAy0pJ PhEaiAmeYM95P7Y/JJfSubElClvEqNkx7px4Y6h1R+zBBuwU3a+ZNJKHbID5juxARUDY XfNCM9sWcti6phyHvTpSl9kRTDReD24Fp4FcCklvqBLcH1xz9wf5ZHcT2k+f7dKQa0vA lyASI1k3VviGdJH4xM9UEGlLrtCukn6Q172RYrLwfrKv595/iVS7/X5hpj9MjDdFxtnG 0tJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745930686; x=1746535486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iLAKtSByZPkbwLOMWEWkl5uORyVUUQ5Q0ynhQjz8M4I=; b=R/uOO6un4OBu6s4Dz7QmEmb4H3C+9MgASYPXtGJC0BkwCoaGfDk3aWnCmIU+5X9cmd u8w97lkZdYiKbTyhuFYsY9ky4k3EDdz9d6c2ys6P/E8lhES2CedK9d56pgfxOblXwkih jK8LNpSDXtjY/nvjShfVKOb+Mn+EIZ5ImovtfJ5vbHREiqgvLDEBgA0VSAvWhVduI05K DEwmjGOEttv2gxM1GtP/GB84plpURUjMV4GFHtRYfjOFGZh97cKK2jPGpI9vqVrSTMhC hLqCm/CKJnyEabFVEak8FIJZihGsDK/DJ/v0/Kq4YriVIM0aRT7fCEsa7lcqdixA4494 MLCg== X-Gm-Message-State: AOJu0Yzm26OWaESyXopKYjfIWrR+lBVFyJquuXDR1+8DJEgf6jJCZ6Mz 9HAj04gLV+++cW1SLXc/eeFkSyuEAjcGVMCDFixYB4uzQZYr+cCgeddQybt45tYBZ3jpZg7QSdu J X-Gm-Gg: ASbGncsZjziqIXc/imTRZ6FH9Gss4ELfdYby6VuSlAZDznvTet56ogU2aiS564hHmgF ofQcUyjPTym9jG0q3h9KmIyg1tHY+8Acjaqtrl5f67GlTN6eg8avTngSbP9pEgNlEtMKEKgGbVo KxLYi1OaXDxJcLK1k4qP7XMjnozeL7UR2HDj84PpGkKwPe45OHYPbC1oV6I0m8wTp1/VPCFkhJE Li8lVgXJ09W31oV46rqSWSg2GA6iK1g969vSx+bkl8E2eMrP38z9JAznQR4YeAIXHq9fK8OF5CN BT+ktYBCoGo3BgAKiFFltgw3hWHC6dM6qWbz7/YiT+M= X-Google-Smtp-Source: AGHT+IFkJErRsiaXwNaEsHBdH2BCQMafFZcQ3joCdFl0WSuJtH7/E5ZMOt2zGaQHQrIAArAUq65d7Q== X-Received: by 2002:a17:90b:264b:b0:2fe:b907:5e5a with SMTP id 98e67ed59e1d1-30a22467d74mr4050029a91.10.1745930685570; Tue, 29 Apr 2025 05:44:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v5 8/9] target/riscv/kvm: read/write KVM regs via env size Date: Tue, 29 Apr 2025 09:44:20 -0300 Message-ID: <20250429124421.223883-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429124421.223883-1-dbarboza@ventanamicro.com> References: <20250429124421.223883-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745930831596019100 Content-Type: text/plain; charset="utf-8" We're going to add support for scounteren in the next patch. KVM defines as a target_ulong CSR, while QEMU defines env->scounteren as a 32 bit field. This will cause the current code to read/write a 64 bit CSR in a 32 bit field when running in a 64 bit CPU. To prevent that, change the current logic to honor the size of the QEMU storage instead of the KVM CSR reg. Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 5efee8adb2..d55361962d 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -135,6 +135,7 @@ typedef struct KVMCPUConfig { const char *description; target_ulong offset; uint64_t kvm_reg_id; + uint32_t prop_size; bool user_set; bool supported; } KVMCPUConfig; @@ -237,6 +238,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu= , CPUState *cs) =20 #define KVM_CSR_CFG(_name, _env_prop, reg_id) \ {.name =3D _name, .offset =3D ENV_CSR_OFFSET(_env_prop), \ + .prop_size =3D sizeof(((CPURISCVState *)0)->_env_prop), \ .kvm_reg_id =3D reg_id} =20 static KVMCPUConfig kvm_csr_cfgs[] =3D { @@ -646,9 +648,9 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) return ret; } =20 - if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { - kvm_cpu_csr_set_u32(cpu, csr_cfg, reg); - } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { + if (csr_cfg->prop_size =3D=3D sizeof(uint32_t)) { + kvm_cpu_csr_set_u32(cpu, csr_cfg, (uint32_t)reg); + } else if (csr_cfg->prop_size =3D=3D sizeof(uint64_t)) { kvm_cpu_csr_set_u64(cpu, csr_cfg, reg); } else { g_assert_not_reached(); @@ -671,9 +673,9 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) continue; } =20 - if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { + if (csr_cfg->prop_size =3D=3D sizeof(uint32_t)) { reg =3D kvm_cpu_csr_get_u32(cpu, csr_cfg); - } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { + } else if (csr_cfg->prop_size =3D=3D sizeof(uint64_t)) { reg =3D kvm_cpu_csr_get_u64(cpu, csr_cfg); } else { g_assert_not_reached(); --=20 2.49.0 From nobody Sat Nov 15 22:35:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745930796; cv=none; d=zohomail.com; s=zohoarc; b=jz4Sh0UZeYLEhrMaOg9jVMtNdFFHuXnO24Xv9HcukfZRI/fxeJjJJS85Zh1n3t/ghCtKj94iOvD49C2QK4CgrO/2zdUOZ6mVkJTii5UFi0EqPzaF4sk+4SO+sm4B7Ex/dOfHsU2oP+a5ArAwUGCp1uamXEW7peDxMGUiE8YDFsY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745930796; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5EPo2xWup2FzZs+fmoD03mr3dmy4Dnii+MBbbjY7Lvw=; b=mPK23ByY5DRpGnOndj3YVEQ5J1X3XfJsf3YPsUsp7/HEYxsRCHVfSdCG8la/dTCYCMwg7FCTh7kd76mrgy4pRrqnm92yfY1I03kmmL9IWjNspDeDFkchC+7Z9+4fRRb2anVBI1lKINiGeSHy2wFA/Wu7wkhZE0mXGlcJsG/iIj8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745930796082672.0194557916701; Tue, 29 Apr 2025 05:46:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kKe-0002q1-1x; Tue, 29 Apr 2025 08:45:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kKU-0002gC-IN for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:54 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kKQ-0004Nn-R8 for qemu-devel@nongnu.org; Tue, 29 Apr 2025 08:44:52 -0400 Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-3031354f134so4890327a91.3 for ; Tue, 29 Apr 2025 05:44:49 -0700 (PDT) Received: from grind.. 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Note that env->scounteren is a 32 bit and all KVM CSRs are target_ulong, so scounteren will be capped to 32 bits read/writes. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index d55361962d..ff22ad1fb6 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -251,6 +251,7 @@ static KVMCPUConfig kvm_csr_cfgs[] =3D { KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)), KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)), KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)), + KVM_CSR_CFG("scounteren", scounteren, RISCV_CSR_REG(scounteren)), KVM_CSR_CFG("senvcfg", senvcfg, RISCV_CSR_REG(senvcfg)), }; =20 @@ -701,6 +702,7 @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env) env->stval =3D 0; env->mip =3D 0; env->satp =3D 0; + env->scounteren =3D 0; env->senvcfg =3D 0; } =20 --=20 2.49.0