[v4] target/riscv/kvm: CSR related fixes

[PATCH v4 0/9] target/riscv/kvm: CSR related fixes

Daniel Henrique Barboza posted 9 patches 6 months, 3 weeks ago

Diff against v1 v2 v3 v5
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250428192323.84992-1-dbarboza@ventanamicro.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.h         |   1 +
target/riscv/kvm/kvm-cpu.c | 335 +++++++++++++++++++++++--------------
2 files changed, 214 insertions(+), 122 deletions(-)

Expand all Fold all

[PATCH v4 0/9] target/riscv/kvm: CSR related fixes

Posted by Daniel Henrique Barboza 6 months, 3 weeks ago

Hi,

In this new version a change was made in patch 8. Instead of changing
scounteren to target_ulong, change the current logic to honor the QEMU
env storage instead of the KVM reg size. 

This will make QEMU the authority when deciding how to read/write the
CSRs in the env flags instead of KVM.

We're doing this change in patch 8 but it could also be squashed into
patch 4. If the code in patch 8 is good to go I don't oppose merging it
with patch 4 if desired.

No other changes made. 

Patches missing acks/review: patch 8.

Changes from v3:
- patch 8:
  - instead of widening scounteren, use the QEMU storage size instead of
    KVM reg size when reading/writing KVM CSRs
- v3 link: https://lore.kernel.org/qemu-riscv/20250425160203.2774835-1-dbarboza@ventanamicro.com/

Daniel Henrique Barboza (9):
  target/riscv/kvm: minor fixes/tweaks
  target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
  target/riscv/kvm: turn u32/u64 reg functions into macros
  target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
  target/riscv/kvm: add kvm_csr_cfgs[]
  target/riscv/kvm: do not read unavailable CSRs
  target/riscv/kvm: add senvcfg CSR
  target/riscv/kvm: read/write KVM regs via env size
  target/riscv/kvm: add scounteren CSR

 target/riscv/cpu.h         |   1 +
 target/riscv/kvm/kvm-cpu.c | 335 +++++++++++++++++++++++--------------
 2 files changed, 214 insertions(+), 122 deletions(-)

-- 
2.49.0

Re: [PATCH v4 0/9] target/riscv/kvm: CSR related fixes

Posted by Andrew Jones 6 months, 2 weeks ago

On Mon, Apr 28, 2025 at 04:23:14PM -0300, Daniel Henrique Barboza wrote:
> Hi,
> 
> In this new version a change was made in patch 8. Instead of changing
> scounteren to target_ulong, change the current logic to honor the QEMU
> env storage instead of the KVM reg size. 
> 
> This will make QEMU the authority when deciding how to read/write the
> CSRs in the env flags instead of KVM.
> 
> We're doing this change in patch 8 but it could also be squashed into
> patch 4. If the code in patch 8 is good to go I don't oppose merging it
> with patch 4 if desired.

I think you mean patch 5, but I think I prefer it separate anyway.

Thanks,
drew

> 
> No other changes made. 
> 
> Patches missing acks/review: patch 8.
> 
> Changes from v3:
> - patch 8:
>   - instead of widening scounteren, use the QEMU storage size instead of
>     KVM reg size when reading/writing KVM CSRs
> - v3 link: https://lore.kernel.org/qemu-riscv/20250425160203.2774835-1-dbarboza@ventanamicro.com/
> 
> Daniel Henrique Barboza (9):
>   target/riscv/kvm: minor fixes/tweaks
>   target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
>   target/riscv/kvm: turn u32/u64 reg functions into macros
>   target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
>   target/riscv/kvm: add kvm_csr_cfgs[]
>   target/riscv/kvm: do not read unavailable CSRs
>   target/riscv/kvm: add senvcfg CSR
>   target/riscv/kvm: read/write KVM regs via env size
>   target/riscv/kvm: add scounteren CSR
> 
>  target/riscv/cpu.h         |   1 +
>  target/riscv/kvm/kvm-cpu.c | 335 +++++++++++++++++++++++--------------
>  2 files changed, 214 insertions(+), 122 deletions(-)
> 
> -- 
> 2.49.0
>