From nobody Sat Nov 15 23:41:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745868315; cv=none; d=zohomail.com; s=zohoarc; b=IuugOrR7GPenkpmbYlJhbXh1t4Xd5GF3k45H+Xde9RSq58jPzimU0K6HGIXAwCqEW7WTNa9q9UwW0j3B2ujuUEtbZbEAnf+4HekImEMclCNzKb7nDZh3GhqnIZrufGRT1KtwtCd9AjxUlMk3ywkT5gnvL/mWqF2M91E+3+canfc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745868315; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=f6R3EUC6CKMFKAnlwhLj+btXOWn++vvQKz0yRoESdjA=; b=mv0+j9DVK0djWxdF0MKLX3HL3QlEvIQToIQuCNPVUNsNkM3j/XkDSt3LaKj/evAuRWV5hcz36b7ZBoGRjV6bmkNWBkeLCr03b67W+2W6gUrWRNukH3g+fuiRgzWeK5isp+EqPkN+2hGvCzvrqavJH3vnc4NuutqlbZ6hSNdm5T4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745868315812352.64906651725744; Mon, 28 Apr 2025 12:25:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9U4q-0003Zp-GQ; Mon, 28 Apr 2025 15:23:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9U4o-0003ZG-MO for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:38 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9U4m-0007L2-Sf for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:38 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-227a8cdd241so71921625ad.3 for ; Mon, 28 Apr 2025 12:23:36 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4db99d3sm87300565ad.53.2025.04.28.12.23.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 12:23:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745868215; x=1746473015; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f6R3EUC6CKMFKAnlwhLj+btXOWn++vvQKz0yRoESdjA=; b=bydd+26VxDfTlpoAAdxIMyokamEXXfU3nLepQzB9puxChlucxUubQ5RrLENS/bZ/nD BnsvwHyxrgmU1xYN3yizBDY3lTt2qLQZr2ujY5/M2QfI9FQOOgbfefphhaFV9WyteCPm r33/lc4fNeYz+cc8o8mnCAqybfix/RSAKTy+6MyDqjmZASi/Qm2A5WPHYRbsmkKT5pUj Kwd35Oi26pXxhu/CeJ9BBUIcyXKkuLN5doWIbO2kDJR/FbhhkNIFZuF78ihgWX6bMOEk nicIxP1+v1UkXZtboxMT5rw43xt4FCn02/nbzDpt9AQWfaSKEEpws5m4WUhJH7DAkyWw pZFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745868215; x=1746473015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f6R3EUC6CKMFKAnlwhLj+btXOWn++vvQKz0yRoESdjA=; b=Zg0Gli3GIn46WKV+yWzqP0foU+TqF8oqQCK+MIIN+F+XB52s6D7FrdLZoB7hc+XK95 IlttfaY3mzbpyYEjg/grzRzxlIQ5YxKmvD5LeWgO1uRhMnfy0l2y2KwWFRpgtI5lB04o olq6QU6ykcDJ8l6TMje4iyIGvzTeFPSI4fKucrhQoo894Ni5LfqyrkTAgP3TX5W3u04h tKUdJYxUQgXUnVVSR/bqLZDFvScSGQPOiSekm7uhQW3udADfEvXVTSNayQzayUFiIhX+ qCdNslv5CUwMn1OoWR2Dkk19RiyySff8zg+X/+ya3BrecrNYjYsG/MMzmFMU/mNerLGI 2a2w== X-Gm-Message-State: AOJu0YzWmSZSW1pka6wVKinvcNgQesdNGoROdkeYbEMbbWIOa7Ku3Fd6 K2OYbNhlKH33fIqvbLcLpSn6ekW4ASpj+oHbi+iej7auArNLlg2/vG0JtG42J71mZsxC2VNYNLw Jv5c= X-Gm-Gg: ASbGncv8uDG/phZvLpMTSSCdC/MEJxU9wGJh3ApY2+Ei4rDLz5N6fjwFw+Cvj7A6aFR UulafWAtPWW850rCBg6LCB6YRN9CQjnfO7hRyht2+i0Ot3CLT9SdSDty8XYEjqmdDNBYBkPlrqE XyvS2LccX49RFKWh5HydEeas43XSF42gHYyXfgcoN7f+EWFU2s+hZX9Bxz1YWLbJg5xAct7YqJI zfjNgf/xBLF/Pv0z2TjznOux9S5A5XFTtv3XWgQLIdo7H7eJZ+pJpJyS3pj2Fi80fZakxqbW1tZ cPVpfhXx5hHvjThwG5e3cDNLAYMcS/QWTvNTFXXieXAM X-Google-Smtp-Source: AGHT+IFKXO5/nXj+orASD82eF4pVoLKsZzXBII/O+Jdd8Ktxb0Nn2fusoZYvHfWZrcWBlA5fMVJDyA== X-Received: by 2002:a17:903:2ec7:b0:224:b60:3ce0 with SMTP id d9443c01a7336-22de6f7e62dmr4066915ad.5.1745868215000; Mon, 28 Apr 2025 12:23:35 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v4 1/9] target/riscv/kvm: minor fixes/tweaks Date: Mon, 28 Apr 2025 16:23:15 -0300 Message-ID: <20250428192323.84992-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428192323.84992-1-dbarboza@ventanamicro.com> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745868317929019100 Content-Type: text/plain; charset="utf-8" Remove an unused 'KVMScratchCPU' pointer argument in kvm_riscv_check_sbi_dbcn_support(). Put kvm_riscv_reset_regs_csr() after kvm_riscv_put_regs_csr(). This will make a future patch diff easier to read, when changes in kvm_riscv_reset_regs_csr() and kvm_riscv_get_regs_csr() will be made. Fixes: a6b53378f5 ("target/riscv/kvm: implement SBI debug console (DBCN) ca= lls") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 9214ce490c..accad4c28e 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -613,19 +613,6 @@ static int kvm_riscv_put_regs_core(CPUState *cs) return ret; } =20 -static void kvm_riscv_reset_regs_csr(CPURISCVState *env) -{ - env->mstatus =3D 0; - env->mie =3D 0; - env->stvec =3D 0; - env->sscratch =3D 0; - env->sepc =3D 0; - env->scause =3D 0; - env->stval =3D 0; - env->mip =3D 0; - env->satp =3D 0; -} - static int kvm_riscv_get_regs_csr(CPUState *cs) { CPURISCVState *env =3D &RISCV_CPU(cs)->env; @@ -660,6 +647,19 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) return 0; } =20 +static void kvm_riscv_reset_regs_csr(CPURISCVState *env) +{ + env->mstatus =3D 0; + env->mie =3D 0; + env->stvec =3D 0; + env->sscratch =3D 0; + env->sepc =3D 0; + env->scause =3D 0; + env->stval =3D 0; + env->mip =3D 0; + env->satp =3D 0; +} + static int kvm_riscv_get_regs_fp(CPUState *cs) { int ret =3D 0; @@ -1078,7 +1078,6 @@ static int uint64_cmp(const void *a, const void *b) } =20 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, - KVMScratchCPU *kvmcpu, struct kvm_reg_list *reglist) { struct kvm_reg_list *reg_search; @@ -1197,7 +1196,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); } =20 - kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); + kvm_riscv_check_sbi_dbcn_support(cpu, reglist); } =20 static void riscv_init_kvm_registers(Object *cpu_obj) --=20 2.49.0 From nobody Sat Nov 15 23:41:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745868315; cv=none; d=zohomail.com; s=zohoarc; b=mZOZtCYEcQI+L3mNQEcmIIJmhkzgLzoKaf8LHemx6pgXKepmzNQCLLI2wgwHnUEnIpdG1oUPamPcOefFHd76wbXHC+Lfc8EnkIbeU5z5WPXpMd8RdZPFc9haeuuCXlBPLFBobfD43h7V+zh78fmhrtJmqpFK2wIGOGdYyD/IJys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745868315; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=O1/pH75J2ESZ3iYPkpvn3hHXRSZ0chs2dEX/b6rX2kE=; b=W4BbUYrdEKzRKNPJ6CCS8GnygG2qPBZmLCPBkXlOEomPsKdcytVXRCgnHvL6/52BQ/CBYVn+JpC8xDvjsmDc1syGAN/SHPMRj38ErM8y0roZnZh74CVgB7zj2sfgd0CnWzWrPHs/uU6ARzNENey3cerEuYEgHvucKOwUV5+I8so= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745868315104383.2569750894296; Mon, 28 Apr 2025 12:25:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9U4u-0003bG-F2; Mon, 28 Apr 2025 15:23:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9U4r-0003ac-ED for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:42 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9U4p-0007Lg-SN for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:41 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-227a8cdd241so71922565ad.3 for ; Mon, 28 Apr 2025 12:23:39 -0700 (PDT) Received: from grind.. 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Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index accad4c28e..6ba122f360 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1119,10 +1119,10 @@ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVM= ScratchCPU *kvmcpu, =20 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmc= pu) { + g_autofree struct kvm_reg_list *reglist =3D NULL; KVMCPUConfig *multi_ext_cfg; struct kvm_one_reg reg; struct kvm_reg_list rl_struct; - struct kvm_reg_list *reglist; uint64_t val, reg_id, *reg_search; int i, ret; =20 --=20 2.49.0 From nobody Sat Nov 15 23:41:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745868348; cv=none; d=zohomail.com; s=zohoarc; b=ay433ZwD6FWzbBdelJAlyjt8RqchADHzi6OHp4w61YdYI2O2Byd0mCeKNRtNsf61mj6jcESmhLHngKz6iZonUWUCCZfqdJos0xOm0hbIbVqKK5iVU+ufmzTr+pMYW9OgQHg1ykAM8dVzV3jgT3Nq40xe9RyFyWgm2fi/5EdFK1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745868348; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TOeCBxmoJl3fpGbBgDl7Mncm5lacwWUBmOxyjJ4Qi9g=; b=d9rk01hl0vT1r1AkEkSweBTVg/3PRvyWcTGeTEsVFXWL0rFD+3MTKgdn9LYKIjTmbvRjtoYsBmyYM+2vMg0mQZqg/5bER4vxx+QVsQMfsaGlXkn1wYKZca4yEax7LznjEYCSbnIKijt8zC5CcRsgii9XimLP4jihnNiV449Grk4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17458683481241015.4752634686737; Mon, 28 Apr 2025 12:25:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9U4y-0003ck-GW; Mon, 28 Apr 2025 15:23:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9U4w-0003c2-GK for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:46 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9U4t-0007MA-Uz for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:45 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-227a8cdd241so71923595ad.3 for ; Mon, 28 Apr 2025 12:23:43 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4db99d3sm87300565ad.53.2025.04.28.12.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 12:23:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745868221; x=1746473021; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TOeCBxmoJl3fpGbBgDl7Mncm5lacwWUBmOxyjJ4Qi9g=; b=kDD3IM+cS9wW6EtObfpQpWo8igB1mm3qbo6wSosJCwEApK3bWcH6xo4fP8lvcUtaWP cDVGZ6ii8WyRwRnvlumWlPiVIe7+E18cb0crncpgtwi9iiTju9p3e/0TcYwsvmfcU0GB QcFk5woUjWIKJdthrL1vKmaQU5dBs82gmN2ZM3bjC+RUHK+9IFnKQ1hHoESr9AeRTCch 8/JfwaEIAzg/ThtqErJUEAQSNzbqiWAjn8YVdEBsLIJLiHFjHD/yyFCQCrjac+gYQ8Gh 1tgDO1E79KyduU4pCpLzhw7LZo0MhMWhKgVHE9q5zwHgG/Z5B0illZquiyMp2HZM16LZ eyGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745868221; x=1746473021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TOeCBxmoJl3fpGbBgDl7Mncm5lacwWUBmOxyjJ4Qi9g=; b=ozL7WJfmdkruZNxZkQUo9FqayUTkDibP8B7zeY+lp8IX04DIotF6vf5EngeuMfoZoq g40dEUSHGvODOaf/10B/ZlBfR7qaSoo0NPMUWFoUYecHO2fvbobagFlV4P0R5xkhHTzU pssL8ocBVUC67g5fc8xNLbMWkIG8+8yZXHJnKt5nc6LnPrV1MhfjiQjfxB6V12IEJCdG nyoLUHs8WTjzRfmN3Dku/u2r02XPieC6Mzpmne0PAvEIQmAT5vJo8pxEW3yqfKc6Wc0R 2S+5IEI1iHEcjWA3wc7NsRDgMRpx4EwxHWn530+wsnSfoSgpC1GtMC95OET4m//8++Y6 XlBQ== X-Gm-Message-State: AOJu0Yy2BfGhOzsYx350jWcQFRcSJ7QIrd+NGu8nu/84f7PGDnHRecmE su7Q/zackrQK7e6RxcN+f/Y2423GiDnIMFCu5bJ8xc3v9Uut2yapk2fF9uYrUew7rWIJphjEzcp aUg4= X-Gm-Gg: ASbGncvNQetG4jQ4wDjMAjaJqLJqMcCrg3x0jXzA3IgfU8tLJWojPx9dEpGGL7l77K0 yWfnObsAYP8L6gptjKkXVc3nJQFKjSEV0j0lmiVJI4tqrXYJfZJmpwBO4lw71nwYxXT3dF+2Acd CkAAFscz/T5sJdNIKxb+GXtTCmKnlBThMDHZCBJD66aRRg3GHHo2t+5chEaWgQl3lJNp2CPvLnM jZKGX4djumrlFq1Q1pJdmkdY/751gETTqxoQaC8e7owruolkPwGvsSd/jbKVH1zr5lha9K7NyM2 W85PbX+lZ2IVwaUiAnlGbOBq/77RctOP4e87dD8qg0bY X-Google-Smtp-Source: AGHT+IGvGt+ZA76bXf7rA/QgT+NlkWA2ckxJ+it9GwjuYhdgSwXMR52EmKApbVF3P37+7TL3nz+Xrw== X-Received: by 2002:a17:902:da88:b0:224:5a8:ba2c with SMTP id d9443c01a7336-22de703cff0mr3185845ad.52.1745868221642; Mon, 28 Apr 2025 12:23:41 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v4 3/9] target/riscv/kvm: turn u32/u64 reg functions into macros Date: Mon, 28 Apr 2025 16:23:17 -0300 Message-ID: <20250428192323.84992-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428192323.84992-1-dbarboza@ventanamicro.com> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745868349915019100 Content-Type: text/plain; charset="utf-8" This change is motivated by a future change w.r.t CSRs management. We want to handle them the same way as KVM extensions, i.e. a static array with KVMCPUConfig objs that will be read/write during init and so on. But to do that properly we must be able to declare a static array that hold KVM regs. C does not allow to init static arrays and use functions as initializers, e.g. we can't do: .kvm_reg_id =3D kvm_riscv_reg_id_ulong(...) When instantiating the array. We can do that with macros though, so our goal is turn kvm_riscv_reg_ulong() in a macro. It is cleaner to turn every other reg_id_*() function in macros, and ulong will end up using the macros for u32 and u64, so we'll start with them. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 6ba122f360..c91ecdfe59 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -58,6 +58,12 @@ void riscv_kvm_aplic_request(void *opaque, int irq, int = level) =20 static bool cap_has_mp_state; =20 +#define KVM_RISCV_REG_ID_U32(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U32 = | \ + type | idx) + +#define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 = | \ + type | idx) + static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, uint64_t idx) { @@ -76,16 +82,6 @@ static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *en= v, uint64_t type, return id; } =20 -static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) -{ - return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; -} - -static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) -{ - return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; -} - static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) { uint64_t size_ctz =3D __builtin_ctz(size_b); @@ -119,12 +115,12 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ KVM_REG_RISCV_CONFIG_REG(name)) =20 -#define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ +#define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ KVM_REG_RISCV_TIMER_REG(name)) =20 -#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) +#define RISCV_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx) =20 -#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) +#define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) =20 #define RISCV_VECTOR_CSR_REG(env, name) \ kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ --=20 2.49.0 From nobody Sat Nov 15 23:41:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745868380; cv=none; d=zohomail.com; s=zohoarc; b=MCZaYy2uv41H5wzE7tMj/1mzYPzmTSQ+Zc/4G52JZi4pXjRvs19CQy3ZgSwP4ZuezIVBm2HrDByK9yOp9vet0LM4PIT493R6BgWlqrjwXzKsh15rrVRXW+zk7xCJr/NA/rm3gm1tmTqjzu/+4nheEBFcHVuuiP8wy/5toq1hKe8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745868380; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6O9BQcppYQehYYe2pBbEGo5x9xXyQ5zE6+droa5J8xU=; b=bYOVOBfG7MH5GoFyY2bqasCk7hTb1W/swuuNqP6ZHVaunGAknImKKeUgaz6sfOqsqegtVG9x7v10DAz0yECzCKaBEFDmLT04LNPunGujCJAuEhsrstpS262+z4hbTGkghGa+7OUJBJpUQBulHbu45TtbPUb+y7gSwYJ2R1i7p/U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174586838012998.40141709186196; Mon, 28 Apr 2025 12:26:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9U57-0003gT-00; Mon, 28 Apr 2025 15:23:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9U54-0003eh-0w for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:54 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9U4y-0007MT-Bt for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:53 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2279915e06eso59238425ad.1 for ; Mon, 28 Apr 2025 12:23:46 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4db99d3sm87300565ad.53.2025.04.28.12.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 12:23:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745868225; x=1746473025; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6O9BQcppYQehYYe2pBbEGo5x9xXyQ5zE6+droa5J8xU=; b=W0/a1H0+KDu5y6FIi3/ggyXUaQlvARdZ7CL9+zjdPHSQtsAQxnZhXRmnPbw4fKRtvM bF6nDFbWvTlZ0CrkN+yVqIflGl/2pvyFMbxWiS57bbOslt9C3rYOMIS+djt7z/hXolpT vLbo+YfM87Ga5k0IbcqicqWOmyKIsj8n/ZI97L7X6XFivCTFHx5mzzbk5BNprR0GSKAq VrXMHzMUuSNMY/ZpBVv+m3D10apoUdIqeWyka68ah++LnKJeQaixcprxu3RE1MvKfg7S Ap2RMUUe/F81h9g33xMEpS1jEn30hJeBWXp8vpmn1wIVU+nX/NDbzel1bSVX4fxQGW8f 9wHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745868225; x=1746473025; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6O9BQcppYQehYYe2pBbEGo5x9xXyQ5zE6+droa5J8xU=; b=kmQXioX3K5tQGA5GZRbYnkvvQPfZOoZxAMCe3HKhbYytteIofUg2T3O3JAOam0GtPM 0LYmcdJPQ6ftqnyx8KPwo74DDlhEZm+e3alPK6i0SEMRsQKqsjm2wSbHNHITaIvOJENu iRv+Q02fXXX8MRHuHKgrKqeM+unGuo0iLw2uiXDH0MdY/NohLiw9A+eKDORCnI0fPILr C4Ldx8nuecnPRKq0VPvUx55C8175z30zZcOuw7E+s+53RCcgb6yE5+USxnUDGjDjsZ/C SJGPUN12yp/XWjzohBaPurwhyuygDttOqR972FSdykX5KqgdcMRL2FvHORdzSlg6tnZ6 Ditw== X-Gm-Message-State: AOJu0Yz3uOZaOfBvOlf42iTYC+Lxu5icpOQGKjz5wY3T83wE5pfl7sB1 pPg7rV8G7r2FN3UjPnG6XfeFyddyZxguy97FFZHpfwUvscjRT+p1bMoOUL5eHJGJZGXsdDtwBJu NrbI= X-Gm-Gg: ASbGncvA3QXIVzwC4j11ZnX4o6AGGBHZEvBujSJyaQzrsDvs3lUTYB5yfRXsuubjdTf nXSN7IxWjATwbjBwZEhZWBmeAcLpXhs/XV0d2/pvLa87HHJZuhvR0FN/N91EYv0cN3YTmjWEoH9 v82gs08OSWOvS7LO7ysFzh8u4KqKSg5qEmxYdyVKZVrG13Sank9g+Ejfg6ljuChst+A7+q1uo15 gEdhIUleeIF0TWUpdtoty9qACk7lya6MwAi10B2Zp8n/EfQ+1SFnesbV9MZKnQqRevqg7a/+INK NKR0xNDDmEXNJrSejK0wIrFJPol5AE1Zet4KMLB+sz0s X-Google-Smtp-Source: AGHT+IGXRFDU4jt2JM6YrPkn9Yth/qyBZNi40F327kgdRNxhXObQqQhD+ycG1nwKK7B3hLIeXVvmvQ== X-Received: by 2002:a17:903:3d0e:b0:21b:d2b6:ca7f with SMTP id d9443c01a7336-22dc6a6c8b1mr159659995ad.32.1745868224732; Mon, 28 Apr 2025 12:23:44 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v4 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro Date: Mon, 28 Apr 2025 16:23:18 -0300 Message-ID: <20250428192323.84992-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428192323.84992-1-dbarboza@ventanamicro.com> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745868381208019000 Content-Type: text/plain; charset="utf-8" We need the reg_id_ulong() helper to be a macro to be able to create a static array of KVMCPUConfig that will hold CSR information. Despite the amount of changes all of them are tedious/trivial: - replace instances of "kvm_riscv_reg_id_ulong" with "KVM_RISCV_REG_ID_ULONG"; - RISCV_CORE_REG(), RISCV_CSR_REG(), RISCV_CONFIG_REG() and RISCV_VECTOR_CSR_REG() only receives one 'name' arg. Remove unneeded 'env' variables when applicable. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 99 ++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 58 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c91ecdfe59..fd66bc1759 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -64,23 +64,11 @@ static bool cap_has_mp_state; #define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 = | \ type | idx) =20 -static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, - uint64_t idx) -{ - uint64_t id =3D KVM_REG_RISCV | type | idx; - - switch (riscv_cpu_mxl(env)) { - case MXL_RV32: - id |=3D KVM_REG_SIZE_U32; - break; - case MXL_RV64: - id |=3D KVM_REG_SIZE_U64; - break; - default: - g_assert_not_reached(); - } - return id; -} +#if defined(TARGET_RISCV64) +#define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U64(type, idx) +#else +#define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U32(type, idx) +#endif =20 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) { @@ -103,16 +91,16 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, return kvm_encode_reg_size_id(id, size_b); } =20 -#define RISCV_CORE_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ +#define RISCV_CORE_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, \ KVM_REG_RISCV_CORE_REG(name)) =20 -#define RISCV_CSR_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ +#define RISCV_CSR_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CSR, \ KVM_REG_RISCV_CSR_REG(name)) =20 -#define RISCV_CONFIG_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ +#define RISCV_CONFIG_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, \ KVM_REG_RISCV_CONFIG_REG(name)) =20 #define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ @@ -122,13 +110,13 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, =20 #define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) =20 -#define RISCV_VECTOR_CSR_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ +#define RISCV_VECTOR_CSR_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ KVM_REG_RISCV_VECTOR_CSR_REG(name)) =20 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ do { \ - int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(csr), ®); \ if (_ret) { \ return _ret; \ } \ @@ -136,7 +124,7 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, =20 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ do { \ - int _ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(csr), ®); \ if (_ret) { \ return _ret; \ } \ @@ -244,7 +232,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu= , CPUState *cs) =20 /* If we're here we're going to disable the MISA bit */ reg =3D 0; - id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, misa_cfg->kvm_reg_id); ret =3D kvm_set_one_reg(cs, id, ®); if (ret !=3D 0) { @@ -430,7 +418,6 @@ static KVMCPUConfig kvm_sbi_dbcn =3D { =20 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) { - CPURISCVState *env =3D &cpu->env; uint64_t id, reg; int i, ret; =20 @@ -441,7 +428,7 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *= cpu, CPUState *cs) continue; } =20 - id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, multi_ext_cfg->kvm_reg_id); reg =3D kvm_cpu_cfg_get(cpu, multi_ext_cfg); ret =3D kvm_set_one_reg(cs, id, ®); @@ -566,14 +553,14 @@ static int kvm_riscv_get_regs_core(CPUState *cs) target_ulong reg; CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 - ret =3D kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); + ret =3D kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); if (ret) { return ret; } env->pc =3D reg; =20 for (i =3D 1; i < 32; i++) { - uint64_t id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); + uint64_t id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); ret =3D kvm_get_one_reg(cs, id, ®); if (ret) { return ret; @@ -592,13 +579,13 @@ static int kvm_riscv_put_regs_core(CPUState *cs) CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 reg =3D env->pc; - ret =3D kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); + ret =3D kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); if (ret) { return ret; } =20 for (i =3D 1; i < 32; i++) { - uint64_t id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); + uint64_t id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); reg =3D env->gpr[i]; ret =3D kvm_set_one_reg(cs, id, ®); if (ret) { @@ -796,26 +783,26 @@ static int kvm_riscv_get_regs_vector(CPUState *cs) return 0; } =20 - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); if (ret) { return ret; } env->vstart =3D reg; =20 - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); if (ret) { return ret; } env->vl =3D reg; =20 - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); if (ret) { return ret; } env->vtype =3D reg; =20 if (kvm_v_vlenb.supported) { - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®= ); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); if (ret) { return ret; } @@ -853,26 +840,26 @@ static int kvm_riscv_put_regs_vector(CPUState *cs) } =20 reg =3D env->vstart; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); if (ret) { return ret; } =20 reg =3D env->vl; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); if (ret) { return ret; } =20 reg =3D env->vtype; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); if (ret) { return ret; } =20 if (kvm_v_vlenb.supported) { reg =3D cpu->cfg.vlenb; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®= ); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); =20 for (int i =3D 0; i < 32; i++) { /* @@ -951,25 +938,24 @@ static void kvm_riscv_destroy_scratch_vcpu(KVMScratch= CPU *scratch) =20 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcp= u) { - CPURISCVState *env =3D &cpu->env; struct kvm_one_reg reg; int ret; =20 - reg.id =3D RISCV_CONFIG_REG(env, mvendorid); + reg.id =3D RISCV_CONFIG_REG(mvendorid); reg.addr =3D (uint64_t)&cpu->cfg.mvendorid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { error_report("Unable to retrieve mvendorid from host, error %d", r= et); } =20 - reg.id =3D RISCV_CONFIG_REG(env, marchid); + reg.id =3D RISCV_CONFIG_REG(marchid); reg.addr =3D (uint64_t)&cpu->cfg.marchid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { error_report("Unable to retrieve marchid from host, error %d", ret= ); } =20 - reg.id =3D RISCV_CONFIG_REG(env, mimpid); + reg.id =3D RISCV_CONFIG_REG(mimpid); reg.addr =3D (uint64_t)&cpu->cfg.mimpid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { @@ -984,7 +970,7 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, struct kvm_one_reg reg; int ret; =20 - reg.id =3D RISCV_CONFIG_REG(env, isa); + reg.id =3D RISCV_CONFIG_REG(isa); reg.addr =3D (uint64_t)&env->misa_ext_mask; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); =20 @@ -1001,11 +987,10 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *c= pu, static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvm= cpu, KVMCPUConfig *cbomz_cfg) { - CPURISCVState *env =3D &cpu->env; struct kvm_one_reg reg; int ret; =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, cbomz_cfg->kvm_reg_id); reg.addr =3D (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); @@ -1019,7 +1004,6 @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cp= u, KVMScratchCPU *kvmcpu, static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) { - CPURISCVState *env =3D &cpu->env; uint64_t val; int i, ret; =20 @@ -1027,7 +1011,7 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *= cpu, KVMCPUConfig *multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; struct kvm_one_reg reg; =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, multi_ext_cfg->kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); @@ -1159,7 +1143,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) =20 for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; - reg_id =3D kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, + reg_id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, multi_ext_cfg->kvm_reg_id); reg_search =3D bsearch(®_id, reglist->reg, reglist->n, sizeof(uint64_t), uint64_cmp); @@ -1338,12 +1322,11 @@ void kvm_arch_init_irq_routing(KVMState *s) =20 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) { - CPURISCVState *env =3D &cpu->env; target_ulong reg; uint64_t id; int ret; =20 - id =3D RISCV_CONFIG_REG(env, mvendorid); + id =3D RISCV_CONFIG_REG(mvendorid); /* * cfg.mvendorid is an uint32 but a target_ulong will * be written. Assign it to a target_ulong var to avoid @@ -1355,13 +1338,13 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, = CPUState *cs) return ret; } =20 - id =3D RISCV_CONFIG_REG(env, marchid); + id =3D RISCV_CONFIG_REG(marchid); ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.marchid); if (ret !=3D 0) { return ret; } =20 - id =3D RISCV_CONFIG_REG(env, mimpid); + id =3D RISCV_CONFIG_REG(mimpid); ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); =20 return ret; @@ -1911,7 +1894,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, E= rror **errp) if (cpu->cfg.ext_zicbom && riscv_cpu_option_set(kvm_cbom_blocksize.name)) { =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, kvm_cbom_blocksize.kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); @@ -1930,7 +1913,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, E= rror **errp) if (cpu->cfg.ext_zicboz && riscv_cpu_option_set(kvm_cboz_blocksize.name)) { =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, kvm_cboz_blocksize.kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); --=20 2.49.0 From nobody Sat Nov 15 23:41:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745868300; cv=none; d=zohomail.com; s=zohoarc; b=IFgbjx+aG85fcDbeN6gtq9UBezX00mMfaQrFi0vkKxwWe9xJsS3JonUNLDpzS08ZcgsUDFSlurNob7FrYqO1my36udtRksaj9428jltScSUS/TY5vSbkAAYWu36Mx/mJmR0eBEt7wumGoqCjvqn78lj5+D6rCcE3mqXlhHjm84Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745868300; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nOpiOx5SFtyMw4NePdfRwxvIac5AkMf5xXQqY8g3kvc=; b=TeXPGnuuIYzAPvbiHTwQ0CydcfK4Sv/qZx8EryF+D/t0Qy5iDW5OHBrN+01Rdz572Ur4VxaWQg2uO284M9zVg/X0cu19+ntRiy61D0Le18xC41obYtZOzmji4eKEH1ObSB6qqwn9WGc/7L7+Lc3WazM+j2v1otX+SarEeNICL9c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745868300579209.43253744183482; Mon, 28 Apr 2025 12:25:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9U54-0003fH-Rp; Mon, 28 Apr 2025 15:23:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9U52-0003eD-EX for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:52 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9U50-0007My-6L for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:52 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-22c3407a87aso77453435ad.3 for ; Mon, 28 Apr 2025 12:23:49 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4db99d3sm87300565ad.53.2025.04.28.12.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 12:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745868228; x=1746473028; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nOpiOx5SFtyMw4NePdfRwxvIac5AkMf5xXQqY8g3kvc=; b=kiHehYXSTIjcimuekU2xQnq924rA4Vga/SqqwZph9umie3Zsgm0x4dQHPsrA39+xhA JnPjlL/0BsFSONAkqfcjqqdhyw53b+QDPxuzOfylwrOQe1z0Ij6QAppyBNkj/Ht+whI8 Ye7no6dTNB7ILxdAbusc78TlvY57oHRQquZM/a9p8K1UpGJS0vv/aZ7w0wKMJZrg3hDa K1oG+H4xjvj5JpZjXwJtdMnSj2FBAA5XBkmkvhijhoSxlfXQGazo2jQZ2N36BcnexZVH h9eeve3NIE2kHiqjOZy5CpGyNt35zClSTZJcH+eD4mxz6ZRqsavhkF3AMGjOf3yNocVD TWkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745868228; x=1746473028; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nOpiOx5SFtyMw4NePdfRwxvIac5AkMf5xXQqY8g3kvc=; b=c2HCqA4CRYa2ZvDkyHM9wjInBPQzNSUWF20GQA/fNjCNqWM52cD2rGLm6U0PEByCUX y73mb1b+AJuJJuYa6sLEobumFtRPzRsaCLo3XAxkv0u3NL/h1yWuly/qHaQBOfN6opUW yTZXILrunaVla0zTvFGyVHm2jMJYvMBDDpd7KajITyvXH2kRmTrOrGj/kNb5rVzba5Ac faD8fyvZ3C+vsCiBbD/v3RsCYmS5ha83M8U/ILh3wLZt6mR9uNpDQBTxzuan431X1QZq G1Rmr93lstcIim428bkwj1Rj6koM9tcJvOeHq3aEDIV4U4bbd5h0WPUo3SW5fJI/2SZA uVPA== X-Gm-Message-State: AOJu0Yx8o7bqZ0QYClSHXbcdRem1QhW1H5qkFj/M4RrIR/1drWr6Xnp3 zTBUYB3wF7BXJmz7aMEUw6LXS5fAxMjm1X9jvIyaQe8bvxnvfPDfZoTV0F6EJeiPoUdlw71CztU gTnA= X-Gm-Gg: ASbGncseTQwJkZhVUj6z4vH2rmggsfykBVewstJirFS+MSLj+1KcvkY95veVSFWjU89 yVS5ErQuw4uvKo+RWWvp/pIbRgYugUR/QKwSl9Sj4hXhLRqfIH0Ji9IG7NJaZTCcoq/0aETtst9 dc4WEt+UlTyTzOxEpnTjyb9pCrImV/+dIR5HrJpq4yAU+zY/Cz1sIdu0FrH66cKsvN+G93SpZYr I/uyTaO4sjo99XX6Lxa4uX/2LGr6vyvR2TIj3fQ+09jTfCtjQ/g+HTZ1aFEvkc5Zdxgty6IeEsG iOFpvc2VXU2/oWcK6v9uoIOzZthprMsqI2GTo+pGhY3h X-Google-Smtp-Source: AGHT+IFogl2CwNMv8vz3cQPfm/MhqQG9d9JMmbeNJzzcgcL18wkEvbcNGzez6fwdWkUX9DLdVzikww== X-Received: by 2002:a17:903:3d07:b0:224:f12:3734 with SMTP id d9443c01a7336-22de5fd8d92mr9643445ad.30.1745868228027; Mon, 28 Apr 2025 12:23:48 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v4 5/9] target/riscv/kvm: add kvm_csr_cfgs[] Date: Mon, 28 Apr 2025 16:23:19 -0300 Message-ID: <20250428192323.84992-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428192323.84992-1-dbarboza@ventanamicro.com> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745868303811019100 Content-Type: text/plain; charset="utf-8" At this moment we're not checking if the host has support for any specific CSR before doing get/put regs. This will cause problems if the host KVM doesn't support it (see [1] as an example). We'll use the same approach done with the CPU extensions: read all known KVM CSRs during init() to check for availability, then read/write them if they are present. This will be made by either using get-reglist or by directly reading the CSRs. For now we'll just convert the CSRs to use a kvm_csr_cfg[] array, reusing the same KVMCPUConfig abstraction we use for extensions, and use the array in (get|put)_csr_regs() instead of manually listing them. A lot of boilerplate will be added but at least we'll automate the get/put procedure for CSRs, i.e. adding a new CSR in the future will be a matter of adding it in kvm_csr_regs[] and everything else will be taken care of. Despite all the code changes no behavioral change is made. [1] https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBL= bLKhfv=3D+jb0SYAw@mail.gmail.com/ Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/kvm/kvm-cpu.c | 121 ++++++++++++++++++++++++++----------- 2 files changed, 86 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 679f417336..f5a60d0c52 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -79,6 +79,7 @@ const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); =20 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) +#define ENV_CSR_OFFSET(_csr) offsetof(CPURISCVState, _csr) =20 typedef struct riscv_cpu_profile { struct riscv_cpu_profile *u_parent; diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index fd66bc1759..f881e7eb5d 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -114,22 +114,6 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ KVM_REG_RISCV_VECTOR_CSR_REG(name)) =20 -#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ - do { \ - int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(csr), ®); \ - if (_ret) { \ - return _ret; \ - } \ - } while (0) - -#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ - do { \ - int _ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(csr), ®); \ - if (_ret) { \ - return _ret; \ - } \ - } while (0) - #define KVM_RISCV_GET_TIMER(cs, name, reg) \ do { \ int ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ @@ -251,6 +235,53 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cp= u, CPUState *cs) } } =20 +#define KVM_CSR_CFG(_name, _env_prop, reg_id) \ + {.name =3D _name, .offset =3D ENV_CSR_OFFSET(_env_prop), \ + .kvm_reg_id =3D reg_id} + +static KVMCPUConfig kvm_csr_cfgs[] =3D { + KVM_CSR_CFG("sstatus", mstatus, RISCV_CSR_REG(sstatus)), + KVM_CSR_CFG("sie", mie, RISCV_CSR_REG(sie)), + KVM_CSR_CFG("stvec", stvec, RISCV_CSR_REG(stvec)), + KVM_CSR_CFG("sscratch", sscratch, RISCV_CSR_REG(sscratch)), + KVM_CSR_CFG("sepc", sepc, RISCV_CSR_REG(sepc)), + KVM_CSR_CFG("scause", scause, RISCV_CSR_REG(scause)), + KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)), + KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)), + KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)), +}; + +static void *kvmconfig_get_env_addr(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) +{ + return (void *)&cpu->env + csr_cfg->offset; +} + +static uint32_t kvm_cpu_csr_get_u32(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) +{ + uint32_t *val32 =3D kvmconfig_get_env_addr(cpu, csr_cfg); + return *val32; +} + +static uint64_t kvm_cpu_csr_get_u64(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) +{ + uint64_t *val64 =3D kvmconfig_get_env_addr(cpu, csr_cfg); + return *val64; +} + +static void kvm_cpu_csr_set_u32(RISCVCPU *cpu, KVMCPUConfig *csr_cfg, + uint32_t val) +{ + uint32_t *val32 =3D kvmconfig_get_env_addr(cpu, csr_cfg); + *val32 =3D val; +} + +static void kvm_cpu_csr_set_u64(RISCVCPU *cpu, KVMCPUConfig *csr_cfg, + uint64_t val) +{ + uint64_t *val64 =3D kvmconfig_get_env_addr(cpu, csr_cfg); + *val64 =3D val; +} + #define KVM_EXT_CFG(_name, _prop, _reg_id) \ {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .kvm_reg_id =3D _reg_id} @@ -598,34 +629,52 @@ static int kvm_riscv_put_regs_core(CPUState *cs) =20 static int kvm_riscv_get_regs_csr(CPUState *cs) { - CPURISCVState *env =3D &RISCV_CPU(cs)->env; + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint64_t reg; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; =20 - KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); - KVM_RISCV_GET_CSR(cs, env, sie, env->mie); - KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); - KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); - KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); - KVM_RISCV_GET_CSR(cs, env, scause, env->scause); - KVM_RISCV_GET_CSR(cs, env, stval, env->stval); - KVM_RISCV_GET_CSR(cs, env, sip, env->mip); - KVM_RISCV_GET_CSR(cs, env, satp, env->satp); + ret =3D kvm_get_one_reg(cs, csr_cfg->kvm_reg_id, ®); + if (ret) { + return ret; + } + + if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { + kvm_cpu_csr_set_u32(cpu, csr_cfg, reg); + } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { + kvm_cpu_csr_set_u64(cpu, csr_cfg, reg); + } else { + g_assert_not_reached(); + } + } =20 return 0; } =20 static int kvm_riscv_put_regs_csr(CPUState *cs) { - CPURISCVState *env =3D &RISCV_CPU(cs)->env; + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint64_t reg; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; + + if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { + reg =3D kvm_cpu_csr_get_u32(cpu, csr_cfg); + } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { + reg =3D kvm_cpu_csr_get_u64(cpu, csr_cfg); + } else { + g_assert_not_reached(); + } =20 - KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); - KVM_RISCV_SET_CSR(cs, env, sie, env->mie); - KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); - KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); - KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); - KVM_RISCV_SET_CSR(cs, env, scause, env->scause); - KVM_RISCV_SET_CSR(cs, env, stval, env->stval); - KVM_RISCV_SET_CSR(cs, env, sip, env->mip); - KVM_RISCV_SET_CSR(cs, env, satp, env->satp); + ret =3D kvm_set_one_reg(cs, csr_cfg->kvm_reg_id, ®); + if (ret) { + return ret; + } + } =20 return 0; } --=20 2.49.0 From nobody Sat Nov 15 23:41:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4db99d3sm87300565ad.53.2025.04.28.12.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 12:23:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745868231; x=1746473031; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R37KMDljb4CsAfrDdBRy5Wnf5bfrROiq1X3f4Wy4iUE=; b=IzQ59fGdE/d5oa05R0PMcREMp8mPGfA76bg0wDaFdI4ireD6iTW2M5Gn93FEaRCa5z 3850mxt7UdMHVySOZeliOn4fSFw4jHDTGYmDNaFZ/9z874QZYcIAwsNPfnDCdenAn/M2 Cb6d3SAB0lZcnKH+nDbWV2RqK742TvCOIwWs9HxHb0ssZUKrLMqqnJqAKqNzo3EZ0F3h G+pgaRiJi0bNlkZMA1eryhJUbtmmDq9KYia8p07aCD5hadC7QMkZ7PRD1hiks9Sw8fjg tuG58NjBu5A1pluN+3lD07CUNTJoa4H0ohSvAm0ewItUZyKxrZlFfcYH1mbDs5ayrdrq xVew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745868231; x=1746473031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R37KMDljb4CsAfrDdBRy5Wnf5bfrROiq1X3f4Wy4iUE=; b=YGvR6MZLSBVXdIcuT7EJejPLs2KnqV+gjuqgRlnzjVmqv4+y9O3g13OGv3nY9Ko35H mVOtdoCKcMEdLtkjOz8cwy40sVtN4I6CvLmntOeLTc3jittJ7bUwcmPZjoQ2+O+3ObGz OorC4jRQe9tss2DPdXswWHvU5kRv5q+kVRgempSJQlP4e4XmUijnqS+1KdUCj4d11qd3 d++BYdc/FIQz4cs9xHCUPtG1amwFcQk5w9PzIyFdL8ppiog3z9XdDs1zjlmVFKFTANPW nfpjm+ebCldss8SPDJU5ky8+w6RUBIP5t0zBtylEaNNG3HLjzKlXRlmV3ubKDFlk/+D+ irEw== X-Gm-Message-State: AOJu0Yx4daSI5/169PSganCYYjQ8wfCjBxSE0wePbP9tH7Kl9Rv3spa1 HiDHkMoOipVYiM+HNDgIV913F4GP2Q6fe9H2GQq1h7xeZ784Wsz8rs9zl19+mS4U8zndnfdFXIG t+/k= X-Gm-Gg: ASbGncvilUGLXqKxHw9wTz+nRSkPKD6ifFDwOSL4hSs2QhXYPO2x1qLxRnWYHVapQ3+ zsHLKflzFVbvQn4/ckCXJF6h2RVXHn1sQbevq+Hdx5hscMVUh1fjWbALZTr7Kl7Ig/bWPEZvIHp sjwmbxpO/xB12EiL2z92eml3+UeOaIcKdT9coC9PddJZfjNi9izyROncP7+iDyAf+DDwUzKM1Rd dj07iHfNgxO6jH+K8kQG3IZW+BKMFlLiI23g6mlgi5yGAgv3wptfSc0uMu1VeV7VlpaYvnoHBQA Xgr5wrbsnphQ9MvlhSXMPXO3ss6QL30YfKxjGCkR5wYc X-Google-Smtp-Source: AGHT+IFeaHEcx3TWpvR3XoC2fzWGJ6Sk3aag6oxrNz9DFxJU1pISjQzp7baIpRib4Nzf/8jZrY6rTw== X-Received: by 2002:a17:90a:c2c7:b0:309:e351:2e3d with SMTP id 98e67ed59e1d1-30a23dd992dmr15592a91.12.1745868231247; Mon, 28 Apr 2025 12:23:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza , Andrea Bolognani Subject: [PATCH v4 6/9] target/riscv/kvm: do not read unavailable CSRs Date: Mon, 28 Apr 2025 16:23:20 -0300 Message-ID: <20250428192323.84992-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428192323.84992-1-dbarboza@ventanamicro.com> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745868404072019100 Content-Type: text/plain; charset="utf-8" [1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6. This happens because the kernel does not know 'senvcfg', making it unable to boot because QEMU is reading/wriiting it without any checks. After converting the CSRs to do "automated" get/put reg procedures in the previous patch we can now scan for availability. Two functions are created: - kvm_riscv_read_csr_cfg_legacy() will check if the CSR exists by brute forcing KVM_GET_ONE_REG in each one of them, interpreting an EINVAL return as indication that the CSR isn't available. This will be use in absence of KVM_GET_REG_LIST; - kvm_riscv_read_csr_cfg() will use the existing result of get_reg_list to check if the CSRs ids are present. kvm_riscv_init_multiext_cfg() is now kvm_riscv_init_cfg() to reflect that the function is also dealing with CSRs. [1] https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBL= bLKhfv=3D+jb0SYAw@mail.gmail.com/ Fixes: 4db19d5b21 ("target/riscv/kvm: add missing KVM CSRs") Reported-by: Andrea Bolognani Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 62 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 3 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index f881e7eb5d..1ce747d047 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -636,6 +636,10 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; =20 + if (!csr_cfg->supported) { + continue; + } + ret =3D kvm_get_one_reg(cs, csr_cfg->kvm_reg_id, ®); if (ret) { return ret; @@ -662,6 +666,10 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; =20 + if (!csr_cfg->supported) { + continue; + } + if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { reg =3D kvm_cpu_csr_get_u32(cpu, csr_cfg); } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { @@ -1090,6 +1098,32 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU = *cpu, } } =20 +static void kvm_riscv_read_csr_cfg_legacy(KVMScratchCPU *kvmcpu) +{ + uint64_t val; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; + struct kvm_one_reg reg; + + reg.id =3D csr_cfg->kvm_reg_id; + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + if (errno =3D=3D EINVAL) { + csr_cfg->supported =3D false; + } else { + error_report("Unable to read KVM CSR %s: %s", + csr_cfg->name, strerror(errno)); + exit(EXIT_FAILURE); + } + } else { + csr_cfg->supported =3D true; + } + } +} + static int uint64_cmp(const void *a, const void *b) { uint64_t val1 =3D *(const uint64_t *)a; @@ -1146,7 +1180,26 @@ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMS= cratchCPU *kvmcpu, } } =20 -static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmc= pu) +static void kvm_riscv_read_csr_cfg(struct kvm_reg_list *reglist) +{ + struct kvm_reg_list *reg_search; + uint64_t reg_id; + + for (int i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; + + reg_id =3D csr_cfg->kvm_reg_id; + reg_search =3D bsearch(®_id, reglist->reg, reglist->n, + sizeof(uint64_t), uint64_cmp); + if (!reg_search) { + continue; + } + + csr_cfg->supported =3D true; + } +} + +static void kvm_riscv_init_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) { g_autofree struct kvm_reg_list *reglist =3D NULL; KVMCPUConfig *multi_ext_cfg; @@ -1163,7 +1216,9 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) * (EINVAL). Use read_legacy() in this case. */ if (errno =3D=3D EINVAL) { - return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); + kvm_riscv_read_multiext_legacy(cpu, kvmcpu); + kvm_riscv_read_csr_cfg_legacy(kvmcpu); + return; } else if (errno !=3D E2BIG) { /* * E2BIG is an expected error message for the API since we @@ -1226,6 +1281,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) } =20 kvm_riscv_check_sbi_dbcn_support(cpu, reglist); + kvm_riscv_read_csr_cfg(reglist); } =20 static void riscv_init_kvm_registers(Object *cpu_obj) @@ -1239,7 +1295,7 @@ static void riscv_init_kvm_registers(Object *cpu_obj) =20 kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); - kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); + kvm_riscv_init_cfg(cpu, &kvmcpu); =20 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); } --=20 2.49.0 From nobody Sat Nov 15 23:41:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745868380; cv=none; d=zohomail.com; s=zohoarc; b=YHNayicJSvWl/jw3y1XLSeAdIQ7slcBICZD4ZHiyXNsPINvDFy/1KqvCLslHUBLvvFErAMgnVurydw67xgVKb+9Pjtd+XKq6x0Pq5425XuU+TWVg3c9mOFcPPtrqvNwr3CYmcvkXHr+h/94ze8AI5ucDeaNkN9fB4V0SSAtQWL8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745868380; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sqkSXWmlAzXCmkQApAbF+YpwERfG9A2hRBSgef/JTFs=; b=TNqrrT2FDwsPqe2KNTkvcBujsJ/l9njpa4dW5yXP1MOv8Koc8S9Xx0E5Jm+wKP5cNMAPxL3EIG18YEz5b4SM9rSy9oi+iDhUOeii3MJbqVvc2LF3prnA4ztmxBikCtwB8azc089kPk+RJqDJ1J5rGNdsu6YQhRf3KnzTCkX+r3w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745868380165282.42201825317363; Mon, 28 Apr 2025 12:26:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9U5A-0003iG-AV; Mon, 28 Apr 2025 15:24:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9U57-0003h3-M1 for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:57 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9U56-0007OK-3C for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:23:57 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-2240b4de12bso78562505ad.2 for ; Mon, 28 Apr 2025 12:23:55 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4db99d3sm87300565ad.53.2025.04.28.12.23.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 12:23:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745868234; x=1746473034; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sqkSXWmlAzXCmkQApAbF+YpwERfG9A2hRBSgef/JTFs=; b=dtepnuWpV6gMvnvXqVOBvEN+kFGWaZQLpTcjtDCpBmvT62Gc20MLr1wpQhttaMiVs6 pQfUUPrfkLvg7PFICtU0aSjpdQnDgkOx2OTO60flKYW/a4lwsaOaUzhtoiJpX7WMA9lr kNCi9wAYtARr+yBYDB1+ivmLnnXYwUIoXtQmxKfdqjCHrRw1u0ebenqu7lQukW3eioS8 YXLuYrdSToSBR3mnbBpLwlrUVNQjXCjTTeS2PM5kxhNaVtJZBP0uD9NhTHffiJy4BV8R 1EFHgqJOncA6OEIUouZ3dAkKjVGi3y7H2L+/QjXCp4MQvLJcmxrYLeeoTbiRTExT61hP drYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745868234; x=1746473034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sqkSXWmlAzXCmkQApAbF+YpwERfG9A2hRBSgef/JTFs=; b=epYEmt0s8kvc9Ng5Q+jgtJ8BFuc2m0tT6GPuKIGeyN4hNWtRtQ6fiFnRC4D6FmDXF0 j86SXfxOLNngRGpwCmVoo3nHTqM1Kur2VoO1JSFi4A168v5gstPnJ7gesYY5RixNGRLn VlL2WMszl15I/ehp51QmJto4CMjI0kWM8bQsKj1DdK5SGsciqPBBsynV0QRJ346nUq4r WkjH1OsZlkXDmqg4Y5ka0y8U5EY7AuQtiqPFqt6AJ11y5c/B56sc8xavIQoSqN/g+ysA Y0Z/7S1qt5UiE/oDKuHSQekUxuCcr/SjF/yoz6UnvunByIAMH/EUGjBHND41yaXFNTwU 2jpw== X-Gm-Message-State: AOJu0YwlzAF7FX3bV4ImDh0QEkauCm02XF2Gf1/v+/xxDAc+kDA1dJ/C wTxskFiq6g5CxfeIin+cs6cNthVZanPaHfwe1C+KK5xYrpIWi6Oz85uLOl5hahXpIlH8KhNFcBM cBuc= X-Gm-Gg: ASbGncsGqBhVXQjAdWNoU1aCzqT0I6/Hh96HMFHuwUmIBX7if+BhWUhQMU2XjbkUeh7 EtE4hNON6mPtHQvil63hidpFt2WqGP6j3s8/+mZDlZMVHiOKeQQivPOyJWrwlz5P8zfqUkvBHV+ XkYPhzE0GFNToRJolfN5HRVF7h7LM/6ROBsCuZalW7SPVQItVahIR+lQ2qdHldrC42UYIpdDGjw JFFrjVjB1IqeXAxd3cGgtmI3aiSaLBYiQ4TgxrbJBq+7LB1LBX7O6eMpvd6bl2iUNuMB8BBMKeY /7busPEySC+/S5aPOsZ23cEAryLflHOak3CcyJnt3aIT X-Google-Smtp-Source: AGHT+IFSnTEGWjV9S2VC9mg//Sux2kfRF9Ce+hrDfGO7zzsfU18TI7NJTQpa9HQ4G4osonWqWRVzLw== X-Received: by 2002:a17:903:1209:b0:21f:7e12:5642 with SMTP id d9443c01a7336-22dc6a04770mr129720115ad.18.1745868234419; Mon, 28 Apr 2025 12:23:54 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v4 7/9] target/riscv/kvm: add senvcfg CSR Date: Mon, 28 Apr 2025 16:23:21 -0300 Message-ID: <20250428192323.84992-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428192323.84992-1-dbarboza@ventanamicro.com> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745868381174019000 Content-Type: text/plain; charset="utf-8" We're missing the senvcfg CSRs which is already present in the KVM UAPI. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 1ce747d047..5efee8adb2 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -249,6 +249,7 @@ static KVMCPUConfig kvm_csr_cfgs[] =3D { KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)), KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)), KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)), + KVM_CSR_CFG("senvcfg", senvcfg, RISCV_CSR_REG(senvcfg)), }; =20 static void *kvmconfig_get_env_addr(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) @@ -698,6 +699,7 @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env) env->stval =3D 0; env->mip =3D 0; env->satp =3D 0; + env->senvcfg =3D 0; } =20 static int kvm_riscv_get_regs_fp(CPUState *cs) --=20 2.49.0 From nobody Sat Nov 15 23:41:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745868315; cv=none; d=zohomail.com; s=zohoarc; b=HhUgiyKGDMtcthDC8wVcYldDLk7NM/GTeiwVXhj91s5GfCmAfqskd6RvmdqT+mmgGUei1fUU2qswbFIqsy78lg+MFxbP7b/HPBdeO9httw8/uikNtsY6Wi79rae9MbxPsDWOVhVsLDkuE44sSmtngF0XaPtOl/rBFualcBrD09I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745868315; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VZIvABSaT73JoHWdEqC95e5mabS4fGuob+IqY91t3yE=; b=RhiCmK51oAuy+ki0QEtas6f+UiRjEU4T67toLMNQHtgPGE3cE4adzO4OR26vKPnZyePWHFW+7Wqc+WjQeBNAyb7kDV0JNQRBwAUhGUYSqVF6tQL/DqFx1OXGvlAV3WZH2848tpoZCOPLPIGCePcPWmNGbGoIdd87g5wePywWnNU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745868315209397.98657721542895; Mon, 28 Apr 2025 12:25:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9U5D-0003iy-5B; Mon, 28 Apr 2025 15:24:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9U5B-0003iW-SR for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:24:01 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9U59-0007Ot-Ih for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:24:01 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-2260c91576aso44454545ad.3 for ; Mon, 28 Apr 2025 12:23:59 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4db99d3sm87300565ad.53.2025.04.28.12.23.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 12:23:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745868237; x=1746473037; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VZIvABSaT73JoHWdEqC95e5mabS4fGuob+IqY91t3yE=; b=deS0xEFEcqPrwb3FxBMwRf31WYltW7O1wHH1PsfMgvEHR5w4RlzD3KdJmJdDNOe7pm pu/nFHkQc1j4XSSNsG7Yjdvd8s5Cflkz04nJ+x/ZK809AIserlJlPv/6jqs0njdv/lqJ XddUtks9PNTziOCjrQ3IrE7ZXIVokuu9jCn4MzgkS+tqZSlPRY9EF7+ELCFuSk/xGPjm tavZq6K62OzjM9i23ymEqYYCi8nIzi8ZjdFw3xEOa7K9Vr44SV/Xnj6+KbCo8+2rHYN1 diMJ0dzAS7tszxVvBGSBTNLjuvLlfOtNLsZOAw5VldN56LsVPuwjD5MvI1Q08jimYkZ0 S18g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745868237; x=1746473037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VZIvABSaT73JoHWdEqC95e5mabS4fGuob+IqY91t3yE=; b=BUPeFekkllyiqfia+q18RfD2COC5bR+/PuEKuVQgQUkydy+BelkjsjzEzODseE866x 7oW9rhlmR6YpOa9/BavvjsCrBIQvDSaFNu/ZfzltRgqBfQfNvZYLis1u/Q9/Kemjpk3M TFywc51glfelnIKvHIdEyXW3BIRQZguH1z4uOXS7w8WdxaG/iwnLHS045iLbORjDCRpB NRsu75yRDrkF0u/m7XTLjEXeP/6zjdGUdM/qVeDkyuS4/5HPlzoQgLng3Xpb5LJCZF1N K0fXJ0w9Zed/8YiIYIMC9n6mQpcleYGMJia6DdHa6EjiH1cNOTzEukqxfV7WEh5UXe8T 2Aew== X-Gm-Message-State: AOJu0YwLl9oR8DiARZr5/KuZ4uY8Vg7Mh4Yas5WCfwoWf5qHaAIWFIG5 bKh2nPKEg23Bq82knQzC9dPU37Pmew60FCQI5XAwxXK9o+0MFfpMC2RkwVgcfhOBmL8JDJg//yn D5dk= X-Gm-Gg: ASbGncsPyJlBXpdt7LwueiApSWv7mVI42c0dS+esK2MzbHaJzFmIbWCA6V2bxXfh5h8 oSWyGZiaQqZ8IrdzzOWCaAFNe80DTv4D6U8PV3cDRjMpnBIWBEh4/5u0TJku3+AT9RaJpMXLAhU 0CyEefC52g5TXlATNAVME9oVV6t3dYDvp4V8WC9gPELdDtnebF/KWKLYgsaSDAbRyMw7I8tKEvK TaGR1Kp1EKGCQxa9/ADpwbLqKSjJ6j+y4LX8rRcced63OeK+i/rkB+XuKH1FXwT/CnF2w5gm54+ XBjrfeKUJOthr0wkQDDk9aU13j7p4szXhwfG2E//C2F8 X-Google-Smtp-Source: AGHT+IFiCW5aKSRjo0qafxqjcMegLspQ0FUZXgMv2FGWGNhd/N8Al89jp1+nRuK04bPpe344dISrJQ== X-Received: by 2002:a17:903:2292:b0:223:54e5:bf4b with SMTP id d9443c01a7336-22dc6a0d4d1mr150313595ad.25.1745868237391; Mon, 28 Apr 2025 12:23:57 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v4 8/9] target/riscv/kvm: read/write KVM regs via env size Date: Mon, 28 Apr 2025 16:23:22 -0300 Message-ID: <20250428192323.84992-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428192323.84992-1-dbarboza@ventanamicro.com> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745868317090019000 Content-Type: text/plain; charset="utf-8" We're going to add support for scounteren in the next patch. KVM defines as a target_ulong CSR, while QEMU defines env->scounteren as a 32 bit field. This will cause the current code to read/write a 64 bit CSR in a 32 bit field when running in a 64 bit CPU. To prevent that, change the current logic to honor the size of the QEMU storage instead of the KVM CSR reg. Signed-off-by: Daniel Henrique Barboza Suggested-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 5efee8adb2..53c34b43a2 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -135,6 +135,7 @@ typedef struct KVMCPUConfig { const char *description; target_ulong offset; uint64_t kvm_reg_id; + uint32_t prop_size; bool user_set; bool supported; } KVMCPUConfig; @@ -237,6 +238,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu= , CPUState *cs) =20 #define KVM_CSR_CFG(_name, _env_prop, reg_id) \ {.name =3D _name, .offset =3D ENV_CSR_OFFSET(_env_prop), \ + .prop_size =3D sizeof(((CPURISCVState *)0)->_env_prop), \ .kvm_reg_id =3D reg_id} =20 static KVMCPUConfig kvm_csr_cfgs[] =3D { @@ -632,6 +634,7 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); uint64_t reg; + uint32_t reg32; int i, ret; =20 for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { @@ -646,9 +649,10 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) return ret; } =20 - if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { - kvm_cpu_csr_set_u32(cpu, csr_cfg, reg); - } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { + if (csr_cfg->prop_size =3D=3D sizeof(uint32_t)) { + reg32 =3D reg & 0xFFFF; + kvm_cpu_csr_set_u32(cpu, csr_cfg, reg32); + } else if (csr_cfg->prop_size =3D=3D sizeof(uint64_t)) { kvm_cpu_csr_set_u64(cpu, csr_cfg, reg); } else { g_assert_not_reached(); @@ -671,9 +675,9 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) continue; } =20 - if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { + if (csr_cfg->prop_size =3D=3D sizeof(uint32_t)) { reg =3D kvm_cpu_csr_get_u32(cpu, csr_cfg); - } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { + } else if (csr_cfg->prop_size =3D=3D sizeof(uint64_t)) { reg =3D kvm_cpu_csr_get_u64(cpu, csr_cfg); } else { g_assert_not_reached(); --=20 2.49.0 From nobody Sat Nov 15 23:41:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745868311; cv=none; d=zohomail.com; s=zohoarc; b=jKFEJ3L636hVs+fSD3lkWg3AsdSHVxXesRpW/b3CyjwAZbHmgrYomp03tVvokedUPRi0DCYjmlcAG/nl4YfUXK0tn7sMNWjJ/aQLX9chuFqwmBJ1UhFs3UXWSRWE9hcK6PIVb+eZdBdZHhfu9qKJchyrqzcM0Yisy0UJVd1dvPE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745868311; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5nQvphfEuGeh2n9SYU8tx7Ki7baxefxZJJlRlKKLmGY=; b=Rp0l8ONt39d6HD+G33sqV3Q/ioK93aNo9S5P+5nQpZWIGhCYtEO13m+XouRyzbKlI7OgRts4TbnYminirEn93Uia5gu+ZHkNw84PPh6SDpiCs+UJyO94lcgBK4Bsaw9aFKT/lNVCJYH+969EAy7E13NiY0/l9MGA4ouTRUUhrLk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745868311213324.44523137383; Mon, 28 Apr 2025 12:25:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9U5F-0003kL-ES; Mon, 28 Apr 2025 15:24:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9U5D-0003jH-Qu for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:24:03 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9U5C-0007PB-7Y for qemu-devel@nongnu.org; Mon, 28 Apr 2025 15:24:03 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2240b4de12bso78563685ad.2 for ; Mon, 28 Apr 2025 12:24:01 -0700 (PDT) Received: from grind.. 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Note that env->scounteren is a 32 bit and all KVM CSRs are target_ulong, so scounteren will be capped to 32 bits read/writes. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 53c34b43a2..209fe769df 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -251,6 +251,7 @@ static KVMCPUConfig kvm_csr_cfgs[] =3D { KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)), KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)), KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)), + KVM_CSR_CFG("scounteren", scounteren, RISCV_CSR_REG(scounteren)), KVM_CSR_CFG("senvcfg", senvcfg, RISCV_CSR_REG(senvcfg)), }; =20 @@ -703,6 +704,7 @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env) env->stval =3D 0; env->mip =3D 0; env->satp =3D 0; + env->scounteren =3D 0; env->senvcfg =3D 0; } =20 --=20 2.49.0