[v1] target/riscv: Fix write_misa vs aligned next_pc

[PATCH 0/7] target/riscv: Fix write_misa vs aligned next_pc

Posted by Richard Henderson 6 months, 3 weeks ago

As discussed, the use of GETPC() within write_misa is wrong.
I've done just enough plumbing to get the helper return address
piped down to write_misa, so that we can make use of unwind data.

AFAIK, nothing in check-tcg or check-functional would test this.
It shouldn't be too hard to write a test akin to issue1060.S,
but I'm going to leave that to someone else.


r~


Richard Henderson (7):
  target/riscv: Pass ra to riscv_csr_write_fn
  target/riscv: Pass ra to riscv_csrrw_do64
  target/riscv: Pass ra to riscv_csrrw_do128
  target/riscv: Pass ra to riscv_csrrw
  target/riscv: Pass ra to riscv_csrrw_i128
  target/riscv: Move insn_len to internals.h
  target/riscv: Fix write_misa vs aligned next_pc

 target/riscv/cpu.h       |  15 ++-
 target/riscv/internals.h |   5 +
 hw/riscv/riscv_hart.c    |   2 +-
 target/riscv/csr.c       | 278 +++++++++++++++++++++------------------
 target/riscv/op_helper.c |  13 +-
 target/riscv/translate.c |   5 -
 6 files changed, 169 insertions(+), 149 deletions(-)

-- 
2.43.0

Re: [PATCH 0/7] target/riscv: Fix write_misa vs aligned next_pc

Posted by Daniel Henrique Barboza 6 months, 3 weeks ago


On 4/25/25 12:23 PM, Richard Henderson wrote:
> As discussed, the use of GETPC() within write_misa is wrong.
> I've done just enough plumbing to get the helper return address
> piped down to write_misa, so that we can make use of unwind data.
> 
> AFAIK, nothing in check-tcg or check-functional would test this.
> It shouldn't be too hard to write a test akin to issue1060.S,
> but I'm going to leave that to someone else.

All patches:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

> 
> 
> r~
> 
> 
> Richard Henderson (7):
>    target/riscv: Pass ra to riscv_csr_write_fn
>    target/riscv: Pass ra to riscv_csrrw_do64
>    target/riscv: Pass ra to riscv_csrrw_do128
>    target/riscv: Pass ra to riscv_csrrw
>    target/riscv: Pass ra to riscv_csrrw_i128
>    target/riscv: Move insn_len to internals.h
>    target/riscv: Fix write_misa vs aligned next_pc
> 
>   target/riscv/cpu.h       |  15 ++-
>   target/riscv/internals.h |   5 +
>   hw/riscv/riscv_hart.c    |   2 +-
>   target/riscv/csr.c       | 278 +++++++++++++++++++++------------------
>   target/riscv/op_helper.c |  13 +-
>   target/riscv/translate.c |   5 -
>   6 files changed, 169 insertions(+), 149 deletions(-)
>

Re: [PATCH 0/7] target/riscv: Fix write_misa vs aligned next_pc

Posted by Alistair Francis 6 months, 2 weeks ago

On Sat, Apr 26, 2025 at 1:25 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> As discussed, the use of GETPC() within write_misa is wrong.
> I've done just enough plumbing to get the helper return address
> piped down to write_misa, so that we can make use of unwind data.

Thanks Richard!

>
> AFAIK, nothing in check-tcg or check-functional would test this.
> It shouldn't be too hard to write a test akin to issue1060.S,
> but I'm going to leave that to someone else.
>
>
> r~
>
>
> Richard Henderson (7):
>   target/riscv: Pass ra to riscv_csr_write_fn
>   target/riscv: Pass ra to riscv_csrrw_do64
>   target/riscv: Pass ra to riscv_csrrw_do128
>   target/riscv: Pass ra to riscv_csrrw
>   target/riscv: Pass ra to riscv_csrrw_i128
>   target/riscv: Move insn_len to internals.h
>   target/riscv: Fix write_misa vs aligned next_pc

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.h       |  15 ++-
>  target/riscv/internals.h |   5 +
>  hw/riscv/riscv_hart.c    |   2 +-
>  target/riscv/csr.c       | 278 +++++++++++++++++++++------------------
>  target/riscv/op_helper.c |  13 +-
>  target/riscv/translate.c |   5 -
>  6 files changed, 169 insertions(+), 149 deletions(-)
>
> --
> 2.43.0
>
>