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Fri, 25 Apr 2025 08:23:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 1/7] target/riscv: Pass ra to riscv_csr_write_fn Date: Fri, 25 Apr 2025 08:23:05 -0700 Message-ID: <20250425152311.804338-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250425152311.804338-1-richard.henderson@linaro.org> References: <20250425152311.804338-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745594703639019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 3 +- target/riscv/csr.c | 226 +++++++++++++++++++++++---------------------- 2 files changed, 118 insertions(+), 111 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 167909c89b..4d41a66d72 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -841,7 +841,8 @@ typedef RISCVException (*riscv_csr_predicate_fn)(CPURIS= CVState *env, typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, target_ulong *ret_value); typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, - target_ulong new_value); + target_ulong new_value, + uintptr_t ra); typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c52c87faae..6f1f69eba6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -830,13 +830,15 @@ static RISCVException seed(CPURISCVState *env, int cs= rno) } =20 /* zicfiss CSR_SSP read and write */ -static int read_ssp(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_ssp(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->ssp; return RISCV_EXCP_NONE; } =20 -static int write_ssp(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_ssp(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) { env->ssp =3D val; return RISCV_EXCP_NONE; @@ -851,7 +853,7 @@ static RISCVException read_fflags(CPURISCVState *env, i= nt csrno, } =20 static RISCVException write_fflags(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVF)) { @@ -870,7 +872,7 @@ static RISCVException read_frm(CPURISCVState *env, int = csrno, } =20 static RISCVException write_frm(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVF)) { @@ -890,7 +892,7 @@ static RISCVException read_fcsr(CPURISCVState *env, int= csrno, } =20 static RISCVException write_fcsr(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVF)) { @@ -942,7 +944,7 @@ static RISCVException read_vxrm(CPURISCVState *env, int= csrno, } =20 static RISCVException write_vxrm(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { #if !defined(CONFIG_USER_ONLY) env->mstatus |=3D MSTATUS_VS; @@ -959,7 +961,7 @@ static RISCVException read_vxsat(CPURISCVState *env, in= t csrno, } =20 static RISCVException write_vxsat(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { #if !defined(CONFIG_USER_ONLY) env->mstatus |=3D MSTATUS_VS; @@ -976,7 +978,7 @@ static RISCVException read_vstart(CPURISCVState *env, i= nt csrno, } =20 static RISCVException write_vstart(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { #if !defined(CONFIG_USER_ONLY) env->mstatus |=3D MSTATUS_VS; @@ -997,7 +999,7 @@ static RISCVException read_vcsr(CPURISCVState *env, int= csrno, } =20 static RISCVException write_vcsr(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { #if !defined(CONFIG_USER_ONLY) env->mstatus |=3D MSTATUS_VS; @@ -1055,7 +1057,7 @@ static RISCVException read_mcyclecfg(CPURISCVState *e= nv, int csrno, } =20 static RISCVException write_mcyclecfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint64_t inh_avail_mask; =20 @@ -1084,7 +1086,7 @@ static RISCVException read_mcyclecfgh(CPURISCVState *= env, int csrno, } =20 static RISCVException write_mcyclecfgh(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { target_ulong inh_avail_mask =3D (target_ulong)(~MHPMEVENTH_FILTER_MASK= | MCYCLECFGH_BIT_MINH); @@ -1109,7 +1111,7 @@ static RISCVException read_minstretcfg(CPURISCVState = *env, int csrno, } =20 static RISCVException write_minstretcfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint64_t inh_avail_mask; =20 @@ -1136,7 +1138,7 @@ static RISCVException read_minstretcfgh(CPURISCVState= *env, int csrno, } =20 static RISCVException write_minstretcfgh(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { target_ulong inh_avail_mask =3D (target_ulong)(~MHPMEVENTH_FILTER_MASK= | MINSTRETCFGH_BIT_MINH); @@ -1163,7 +1165,7 @@ static RISCVException read_mhpmevent(CPURISCVState *e= nv, int csrno, } =20 static RISCVException write_mhpmevent(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { int evt_index =3D csrno - CSR_MCOUNTINHIBIT; uint64_t mhpmevt_val =3D val; @@ -1201,7 +1203,7 @@ static RISCVException read_mhpmeventh(CPURISCVState *= env, int csrno, } =20 static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; uint64_t mhpmevth_val; @@ -1343,14 +1345,16 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCV= State *env, target_ulong val, return RISCV_EXCP_NONE; } =20 -static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) +static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) { int ctr_idx =3D csrno - CSR_MCYCLE; =20 return riscv_pmu_write_ctr(env, val, ctr_idx); } =20 -static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) +static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) { int ctr_idx =3D csrno - CSR_MCYCLEH; =20 @@ -1661,7 +1665,7 @@ static RISCVException read_vstimecmph(CPURISCVState *= env, int csrno, } =20 static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { env->vstimecmp =3D deposit64(env->vstimecmp, 0, 32, (uint64_t)val); @@ -1676,7 +1680,7 @@ static RISCVException write_vstimecmp(CPURISCVState *= env, int csrno, } =20 static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->vstimecmp =3D deposit64(env->vstimecmp, 32, 32, (uint64_t)val); riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, @@ -1710,13 +1714,13 @@ static RISCVException read_stimecmph(CPURISCVState = *env, int csrno, } =20 static RISCVException write_stimecmp(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } - return write_vstimecmp(env, csrno, val); + return write_vstimecmp(env, csrno, val, ra); } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { @@ -1731,13 +1735,13 @@ static RISCVException write_stimecmp(CPURISCVState = *env, int csrno, } =20 static RISCVException write_stimecmph(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } - return write_vstimecmph(env, csrno, val); + return write_vstimecmph(env, csrno, val, ra); } =20 env->stimecmp =3D deposit64(env->stimecmp, 32, 32, (uint64_t)val); @@ -1842,7 +1846,7 @@ static RISCVException read_zero(CPURISCVState *env, i= nt csrno, } =20 static RISCVException write_ignore(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { return RISCV_EXCP_NONE; } @@ -1963,7 +1967,7 @@ static target_ulong legalize_mpp(CPURISCVState *env, = target_ulong old_mpp, } =20 static RISCVException write_mstatus(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint64_t mstatus =3D env->mstatus; uint64_t mask =3D 0; @@ -2042,7 +2046,7 @@ static RISCVException read_mstatush(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_mstatush(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint64_t valh =3D (uint64_t)val << 32; uint64_t mask =3D riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA = : 0; @@ -2096,7 +2100,7 @@ static RISCVException read_misa(CPURISCVState *env, i= nt csrno, } =20 static RISCVException write_misa(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { RISCVCPU *cpu =3D env_archcpu(env); uint32_t orig_misa_ext =3D env->misa_ext; @@ -2160,7 +2164,7 @@ static RISCVException read_medeleg(CPURISCVState *env= , int csrno, } =20 static RISCVException write_medeleg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->medeleg =3D (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_= EXCPS); return RISCV_EXCP_NONE; @@ -2955,7 +2959,7 @@ static RISCVException read_mtvec(CPURISCVState *env, = int csrno, } =20 static RISCVException write_mtvec(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ if ((val & 3) < 2) { @@ -2974,7 +2978,7 @@ static RISCVException read_mcountinhibit(CPURISCVStat= e *env, int csrno, } =20 static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { int cidx; PMUCTRState *counter; @@ -3049,10 +3053,9 @@ static RISCVException read_scountinhibit(CPURISCVSta= te *env, int csrno, } =20 static RISCVException write_scountinhibit(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { - write_mcountinhibit(env, csrno, val & env->mcounteren); - return RISCV_EXCP_NONE; + return write_mcountinhibit(env, csrno, val & env->mcounteren, ra); } =20 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, @@ -3063,7 +3066,7 @@ static RISCVException read_mcounteren(CPURISCVState *= env, int csrno, } =20 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { RISCVCPU *cpu =3D env_archcpu(env); =20 @@ -3097,7 +3100,7 @@ static RISCVException read_mscratch(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_mscratch(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->mscratch =3D val; return RISCV_EXCP_NONE; @@ -3111,7 +3114,7 @@ static RISCVException read_mepc(CPURISCVState *env, i= nt csrno, } =20 static RISCVException write_mepc(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->mepc =3D val; return RISCV_EXCP_NONE; @@ -3125,7 +3128,7 @@ static RISCVException read_mcause(CPURISCVState *env,= int csrno, } =20 static RISCVException write_mcause(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->mcause =3D val; return RISCV_EXCP_NONE; @@ -3139,7 +3142,7 @@ static RISCVException read_mtval(CPURISCVState *env, = int csrno, } =20 static RISCVException write_mtval(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->mtval =3D val; return RISCV_EXCP_NONE; @@ -3154,9 +3157,9 @@ static RISCVException read_menvcfg(CPURISCVState *env= , int csrno, } =20 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, - target_ulong val); + target_ulong val, uintptr_t ra); static RISCVException write_menvcfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | @@ -3188,9 +3191,7 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, } } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); - write_henvcfg(env, CSR_HENVCFG, env->henvcfg); - - return RISCV_EXCP_NONE; + return write_henvcfg(env, CSR_HENVCFG, env->henvcfg, ra); } =20 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, @@ -3201,9 +3202,9 @@ static RISCVException read_menvcfgh(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, - target_ulong val); + target_ulong val, uintptr_t ra); static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | @@ -3218,9 +3219,7 @@ static RISCVException write_menvcfgh(CPURISCVState *e= nv, int csrno, } =20 env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); - write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32); - - return RISCV_EXCP_NONE; + return write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32, ra); } =20 static RISCVException read_senvcfg(CPURISCVState *env, int csrno, @@ -3238,7 +3237,7 @@ static RISCVException read_senvcfg(CPURISCVState *env= , int csrno, } =20 static RISCVException write_senvcfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; RISCVException ret; @@ -3295,7 +3294,7 @@ static RISCVException read_henvcfg(CPURISCVState *env= , int csrno, } =20 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; RISCVException ret; @@ -3350,7 +3349,7 @@ static RISCVException read_henvcfgh(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint64_t mask =3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | HENVCFG_DTE); @@ -3388,7 +3387,7 @@ static RISCVException write_mstateen(CPURISCVState *e= nv, int csrno, } =20 static RISCVException write_mstateen0(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t ra) { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; if (!riscv_has_ext(env, RVF)) { @@ -3420,7 +3419,7 @@ static RISCVException write_mstateen0(CPURISCVState *= env, int csrno, } =20 static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t r= a) { return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); } @@ -3447,7 +3446,7 @@ static RISCVException write_mstateenh(CPURISCVState *= env, int csrno, } =20 static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t ra) { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 @@ -3463,7 +3462,7 @@ static RISCVException write_mstateen0h(CPURISCVState = *env, int csrno, } =20 static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t = ra) { return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); } @@ -3492,7 +3491,7 @@ static RISCVException write_hstateen(CPURISCVState *e= nv, int csrno, } =20 static RISCVException write_hstateen0(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t ra) { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 @@ -3521,7 +3520,7 @@ static RISCVException write_hstateen0(CPURISCVState *= env, int csrno, } =20 static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t r= a) { return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); } @@ -3552,7 +3551,7 @@ static RISCVException write_hstateenh(CPURISCVState *= env, int csrno, } =20 static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t ra) { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 @@ -3564,7 +3563,7 @@ static RISCVException write_hstateen0h(CPURISCVState = *env, int csrno, } =20 static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t = ra) { return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); } @@ -3603,7 +3602,7 @@ static RISCVException write_sstateen(CPURISCVState *e= nv, int csrno, } =20 static RISCVException write_sstateen0(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t ra) { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 @@ -3615,7 +3614,7 @@ static RISCVException write_sstateen0(CPURISCVState *= env, int csrno, } =20 static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno, - target_ulong new_val) + target_ulong new_val, uintptr_t r= a) { return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); } @@ -3866,7 +3865,7 @@ static RISCVException read_sstatus(CPURISCVState *env= , int csrno, } =20 static RISCVException write_sstatus(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { target_ulong mask =3D (sstatus_v1_10_mask); =20 @@ -3883,7 +3882,7 @@ static RISCVException write_sstatus(CPURISCVState *en= v, int csrno, mask |=3D SSTATUS_SDT; } target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); - return write_mstatus(env, CSR_MSTATUS, newval); + return write_mstatus(env, CSR_MSTATUS, newval, ra); } =20 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, @@ -4035,7 +4034,7 @@ static RISCVException read_stvec(CPURISCVState *env, = int csrno, } =20 static RISCVException write_stvec(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ if ((val & 3) < 2) { @@ -4054,7 +4053,7 @@ static RISCVException read_scounteren(CPURISCVState *= env, int csrno, } =20 static RISCVException write_scounteren(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { RISCVCPU *cpu =3D env_archcpu(env); =20 @@ -4088,7 +4087,7 @@ static RISCVException read_sscratch(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_sscratch(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->sscratch =3D val; return RISCV_EXCP_NONE; @@ -4102,7 +4101,7 @@ static RISCVException read_sepc(CPURISCVState *env, i= nt csrno, } =20 static RISCVException write_sepc(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->sepc =3D val; return RISCV_EXCP_NONE; @@ -4116,7 +4115,7 @@ static RISCVException read_scause(CPURISCVState *env,= int csrno, } =20 static RISCVException write_scause(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->scause =3D val; return RISCV_EXCP_NONE; @@ -4130,7 +4129,7 @@ static RISCVException read_stval(CPURISCVState *env, = int csrno, } =20 static RISCVException write_stval(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->stval =3D val; return RISCV_EXCP_NONE; @@ -4270,7 +4269,7 @@ static RISCVException read_satp(CPURISCVState *env, i= nt csrno, } =20 static RISCVException write_satp(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { if (!riscv_cpu_cfg(env)->mmu) { return RISCV_EXCP_NONE; @@ -4492,7 +4491,7 @@ static RISCVException read_hstatus(CPURISCVState *env= , int csrno, } =20 static RISCVException write_hstatus(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint64_t mask =3D (target_ulong)-1; if (!env_archcpu(env)->cfg.ext_svukte) { @@ -4524,7 +4523,7 @@ static RISCVException read_hedeleg(CPURISCVState *env= , int csrno, } =20 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->hedeleg =3D val & vs_delegable_excps; return RISCV_EXCP_NONE; @@ -4545,7 +4544,7 @@ static RISCVException read_hedelegh(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_hedelegh(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { RISCVException ret; ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); @@ -4808,7 +4807,7 @@ static RISCVException read_hcounteren(CPURISCVState *= env, int csrno, } =20 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { RISCVCPU *cpu =3D env_archcpu(env); =20 @@ -4828,7 +4827,7 @@ static RISCVException read_hgeie(CPURISCVState *env, = int csrno, } =20 static RISCVException write_hgeie(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ val &=3D ((((target_ulong)1) << env->geilen) - 1) << 1; @@ -4847,7 +4846,7 @@ static RISCVException read_htval(CPURISCVState *env, = int csrno, } =20 static RISCVException write_htval(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->htval =3D val; return RISCV_EXCP_NONE; @@ -4861,7 +4860,7 @@ static RISCVException read_htinst(CPURISCVState *env,= int csrno, } =20 static RISCVException write_htinst(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { return RISCV_EXCP_NONE; } @@ -4883,7 +4882,7 @@ static RISCVException read_hgatp(CPURISCVState *env, = int csrno, } =20 static RISCVException write_hgatp(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->hgatp =3D legalize_xatp(env, env->hgatp, val); return RISCV_EXCP_NONE; @@ -4901,7 +4900,7 @@ static RISCVException read_htimedelta(CPURISCVState *= env, int csrno, } =20 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -4933,7 +4932,7 @@ static RISCVException read_htimedeltah(CPURISCVState = *env, int csrno, } =20 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -4957,7 +4956,7 @@ static RISCVException read_hvictl(CPURISCVState *env,= int csrno, } =20 static RISCVException write_hvictl(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->hvictl =3D val & HVICTL_VALID_MASK; return RISCV_EXCP_NONE; @@ -5022,7 +5021,7 @@ static RISCVException read_hviprio1(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_hviprio1(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { return write_hvipriox(env, 0, env->hviprio, val); } @@ -5034,7 +5033,7 @@ static RISCVException read_hviprio1h(CPURISCVState *e= nv, int csrno, } =20 static RISCVException write_hviprio1h(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { return write_hvipriox(env, 4, env->hviprio, val); } @@ -5046,7 +5045,7 @@ static RISCVException read_hviprio2(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_hviprio2(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { return write_hvipriox(env, 8, env->hviprio, val); } @@ -5058,7 +5057,7 @@ static RISCVException read_hviprio2h(CPURISCVState *e= nv, int csrno, } =20 static RISCVException write_hviprio2h(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { return write_hvipriox(env, 12, env->hviprio, val); } @@ -5072,7 +5071,7 @@ static RISCVException read_vsstatus(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint64_t mask =3D (target_ulong)-1; if ((val & VSSTATUS64_UXL) =3D=3D 0) { @@ -5097,7 +5096,7 @@ static RISCVException read_vstvec(CPURISCVState *env,= int csrno, } =20 static RISCVException write_vstvec(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ if ((val & 3) < 2) { @@ -5116,7 +5115,7 @@ static RISCVException read_vsscratch(CPURISCVState *e= nv, int csrno, } =20 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->vsscratch =3D val; return RISCV_EXCP_NONE; @@ -5130,7 +5129,7 @@ static RISCVException read_vsepc(CPURISCVState *env, = int csrno, } =20 static RISCVException write_vsepc(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->vsepc =3D val; return RISCV_EXCP_NONE; @@ -5144,7 +5143,7 @@ static RISCVException read_vscause(CPURISCVState *env= , int csrno, } =20 static RISCVException write_vscause(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->vscause =3D val; return RISCV_EXCP_NONE; @@ -5158,7 +5157,7 @@ static RISCVException read_vstval(CPURISCVState *env,= int csrno, } =20 static RISCVException write_vstval(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->vstval =3D val; return RISCV_EXCP_NONE; @@ -5172,7 +5171,7 @@ static RISCVException read_vsatp(CPURISCVState *env, = int csrno, } =20 static RISCVException write_vsatp(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->vsatp =3D legalize_xatp(env, env->vsatp, val); return RISCV_EXCP_NONE; @@ -5186,7 +5185,7 @@ static RISCVException read_mtval2(CPURISCVState *env,= int csrno, } =20 static RISCVException write_mtval2(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->mtval2 =3D val; return RISCV_EXCP_NONE; @@ -5200,7 +5199,7 @@ static RISCVException read_mtinst(CPURISCVState *env,= int csrno, } =20 static RISCVException write_mtinst(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->mtinst =3D val; return RISCV_EXCP_NONE; @@ -5215,7 +5214,7 @@ static RISCVException read_mseccfg(CPURISCVState *env= , int csrno, } =20 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { mseccfg_csr_write(env, val); return RISCV_EXCP_NONE; @@ -5231,7 +5230,7 @@ static RISCVException read_pmpcfg(CPURISCVState *env,= int csrno, } =20 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { uint32_t reg_index =3D csrno - CSR_PMPCFG0; =20 @@ -5247,7 +5246,7 @@ static RISCVException read_pmpaddr(CPURISCVState *env= , int csrno, } =20 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); return RISCV_EXCP_NONE; @@ -5261,7 +5260,7 @@ static RISCVException read_tselect(CPURISCVState *env= , int csrno, } =20 static RISCVException write_tselect(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { tselect_csr_write(env, val); return RISCV_EXCP_NONE; @@ -5285,7 +5284,7 @@ static RISCVException read_tdata(CPURISCVState *env, = int csrno, } =20 static RISCVException write_tdata(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { if (!tdata_available(env, csrno - CSR_TDATA1)) { return RISCV_EXCP_ILLEGAL_INST; @@ -5310,7 +5309,7 @@ static RISCVException read_mcontext(CPURISCVState *en= v, int csrno, } =20 static RISCVException write_mcontext(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; int32_t mask; @@ -5334,43 +5333,50 @@ static RISCVException read_mnscratch(CPURISCVState = *env, int csrno, return RISCV_EXCP_NONE; } =20 -static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mnscratch(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) { env->mnscratch =3D val; return RISCV_EXCP_NONE; } =20 -static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mnepc(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mnepc; return RISCV_EXCP_NONE; } =20 -static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mnepc(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) { env->mnepc =3D val; return RISCV_EXCP_NONE; } =20 -static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mncause(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mncause; return RISCV_EXCP_NONE; } =20 -static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mncause(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) { env->mncause =3D val; return RISCV_EXCP_NONE; } =20 -static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mnstatus(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mnstatus; return RISCV_EXCP_NONE; } =20 -static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mnstatus(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) { target_ulong mask =3D (MNSTATUS_NMIE | MNSTATUS_MNPP); =20 @@ -5540,7 +5546,7 @@ static RISCVException riscv_csrrw_do64(CPURISCVState = *env, int csrno, if (write_mask) { new_value =3D (old_value & ~write_mask) | (new_value & write_mask); if (csr_ops[csrno].write) { - ret =3D csr_ops[csrno].write(env, csrno, new_value); + ret =3D csr_ops[csrno].write(env, csrno, new_value, 0); if (ret !=3D RISCV_EXCP_NONE) { return ret; } @@ -5603,7 +5609,7 @@ static RISCVException riscv_csrrw_do128(CPURISCVState= *env, int csrno, } } else if (csr_ops[csrno].write) { /* avoids having to write wrappers for all registers */ - ret =3D csr_ops[csrno].write(env, csrno, int128_getlo(new_valu= e)); + ret =3D csr_ops[csrno].write(env, csrno, int128_getlo(new_valu= e), 0); if (ret !=3D RISCV_EXCP_NONE) { return ret; } @@ -5714,7 +5720,7 @@ static RISCVException read_jvt(CPURISCVState *env, in= t csrno, } =20 static RISCVException write_jvt(CPURISCVState *env, int csrno, - target_ulong val) + target_ulong val, uintptr_t ra) { env->jvt =3D val; return RISCV_EXCP_NONE; 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Fri, 25 Apr 2025 08:23:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64 Date: Fri, 25 Apr 2025 08:23:06 -0700 Message-ID: <20250425152311.804338-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250425152311.804338-1-richard.henderson@linaro.org> References: <20250425152311.804338-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745594670673019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/csr.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6f1f69eba6..e9c2f95b6e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5516,7 +5516,8 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, - target_ulong write_mask) + target_ulong write_mask, + uintptr_t ra) { RISCVException ret; target_ulong old_value =3D 0; @@ -5546,7 +5547,7 @@ static RISCVException riscv_csrrw_do64(CPURISCVState = *env, int csrno, if (write_mask) { new_value =3D (old_value & ~write_mask) | (new_value & write_mask); if (csr_ops[csrno].write) { - ret =3D csr_ops[csrno].write(env, csrno, new_value, 0); + ret =3D csr_ops[csrno].write(env, csrno, new_value, ra); if (ret !=3D RISCV_EXCP_NONE) { return ret; } @@ -5569,7 +5570,7 @@ RISCVException riscv_csrr(CPURISCVState *env, int csr= no, return ret; } =20 - return riscv_csrrw_do64(env, csrno, ret_value, 0, 0); + return riscv_csrrw_do64(env, csrno, ret_value, 0, 0, 0); } =20 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, @@ -5581,7 +5582,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int cs= rno, return ret; } =20 - return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); + return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, = 0); } =20 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, @@ -5647,9 +5648,7 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, in= t csrno, * accesses */ target_ulong old_value; - ret =3D riscv_csrrw_do64(env, csrno, &old_value, - (target_ulong)0, - (target_ulong)0); + ret =3D riscv_csrrw_do64(env, csrno, &old_value, 0, 0, 0); if (ret =3D=3D RISCV_EXCP_NONE && ret_value) { *ret_value =3D int128_make64(old_value); } @@ -5681,7 +5680,7 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, i= nt csrno, target_ulong old_value; ret =3D riscv_csrrw_do64(env, csrno, &old_value, int128_getlo(new_value), - int128_getlo(write_mask)); + int128_getlo(write_mask), 0); if (ret =3D=3D RISCV_EXCP_NONE && ret_value) { *ret_value =3D int128_make64(old_value); } --=20 2.43.0 From nobody Sat Nov 15 23:37:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745594738; cv=none; d=zohomail.com; s=zohoarc; b=jcBjYJiX5vDvqxoYNx5xaGSHmSONocQF17CqzxRkA2zz1u64g1GQUSEQle3ybDT+JA+2n1XMV0F8OVQnGyICaap/wWRAYpLA7rIb4krLfP0QuZdVeyjBQ72O7eDlW90tk4oQajvuw1suf/gkzY+JRB6p15ylTgvDY4mUqL+jqGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Fri, 25 Apr 2025 08:23:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 3/7] target/riscv: Pass ra to riscv_csrrw_do128 Date: Fri, 25 Apr 2025 08:23:07 -0700 Message-ID: <20250425152311.804338-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250425152311.804338-1-richard.henderson@linaro.org> References: <20250425152311.804338-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745594740648019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/csr.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e9c2f95b6e..d62d1aaaee 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5588,7 +5588,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int cs= rno, static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, Int128 *ret_value, Int128 new_value, - Int128 write_mask) + Int128 write_mask, uintptr_t ra) { RISCVException ret; Int128 old_value; @@ -5610,7 +5610,7 @@ static RISCVException riscv_csrrw_do128(CPURISCVState= *env, int csrno, } } else if (csr_ops[csrno].write) { /* avoids having to write wrappers for all registers */ - ret =3D csr_ops[csrno].write(env, csrno, int128_getlo(new_valu= e), 0); + ret =3D csr_ops[csrno].write(env, csrno, int128_getlo(new_valu= e), ra); if (ret !=3D RISCV_EXCP_NONE) { return ret; } @@ -5637,7 +5637,7 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, in= t csrno, =20 if (csr_ops[csrno].read128) { return riscv_csrrw_do128(env, csrno, ret_value, - int128_zero(), int128_zero()); + int128_zero(), int128_zero(), 0); } =20 /* @@ -5667,7 +5667,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, i= nt csrno, } =20 if (csr_ops[csrno].read128) { - return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_m= ask); + return riscv_csrrw_do128(env, csrno, ret_value, + new_value, write_mask, 0); } =20 /* --=20 2.43.0 From nobody Sat Nov 15 23:37:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745594702; cv=none; d=zohomail.com; s=zohoarc; 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Fri, 25 Apr 2025 08:23:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 4/7] target/riscv: Pass ra to riscv_csrrw Date: Fri, 25 Apr 2025 08:23:08 -0700 Message-ID: <20250425152311.804338-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250425152311.804338-1-richard.henderson@linaro.org> References: <20250425152311.804338-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745594704504019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 8 ++++---- hw/riscv/riscv_hart.c | 2 +- target/riscv/csr.c | 8 ++++---- target/riscv/op_helper.c | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d41a66d72..2c0524d0be 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -816,8 +816,8 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno, target_ulong *ret_value); =20 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask= ); + target_ulong *ret_value, target_ulong new_value, + target_ulong write_mask, uintptr_t ra); RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, @@ -826,13 +826,13 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, = int csrno, static inline void riscv_csr_write(CPURISCVState *env, int csrno, target_ulong val) { - riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS= )); + riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS= ), 0); } =20 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) { target_ulong val =3D 0; - riscv_csrrw(env, csrno, &val, 0, 0); + riscv_csrrw(env, csrno, &val, 0, 0, 0); return val; } =20 diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index a55d156668..2ebbf41b18 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -72,7 +72,7 @@ static void csr_call(char *cmd, uint64_t cpu_num, int csr= no, uint64_t *val) ret =3D riscv_csrr(env, csrno, (target_ulong *)val); } else if (strcmp(cmd, "set_csr") =3D=3D 0) { ret =3D riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, - MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); + MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); } =20 g_assert(ret =3D=3D RISCV_EXCP_NONE); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d62d1aaaee..097640e25d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5574,15 +5574,15 @@ RISCVException riscv_csrr(CPURISCVState *env, int c= srno, } =20 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) + target_ulong *ret_value, target_ulong new_value, + target_ulong write_mask, uintptr_t ra) { RISCVException ret =3D riscv_csrrw_check(env, csrno, true); if (ret !=3D RISCV_EXCP_NONE) { return ret; } =20 - return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, = 0); + return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, = ra); } =20 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, @@ -5704,7 +5704,7 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, = int csrno, if (!write_mask) { ret =3D riscv_csrr(env, csrno, ret_value); } else { - ret =3D riscv_csrrw(env, csrno, ret_value, new_value, write_mask); + ret =3D riscv_csrrw(env, csrno, ret_value, new_value, write_mask, = 0); } #if !defined(CONFIG_USER_ONLY) env->debugger =3D false; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5b0db2c45a..aee16e2e3a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -71,7 +71,7 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) void helper_csrw(CPURISCVState *env, int csr, target_ulong src) { target_ulong mask =3D env->xl =3D=3D MXL_RV32 ? UINT32_MAX : (target_u= long)-1; - RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, mask); + RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, mask, GETPC()); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); @@ -82,7 +82,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, target_ulong src, target_ulong write_mask) { target_ulong val =3D 0; - RISCVException ret =3D riscv_csrrw(env, csr, &val, src, write_mask); + RISCVException ret =3D riscv_csrrw(env, csr, &val, src, write_mask, GE= TPC()); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); --=20 2.43.0 From nobody Sat Nov 15 23:37:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745594727; cv=none; d=zohomail.com; s=zohoarc; b=H/jU/HUcKX/ranqfWVnRYw5oRmAKPTL6oNnC15bRZ0WE2uD5A41HMckUM23MiAfk/Ouc3jp9OMkCSdxogFXTiQ49u6pIa+nckhOTFa0OdtS/SkPoHEQ4uR4ufw3eTKJGdISlwDHEIjijRBNyNoV4ubY4LlleAnQ7DPKn9zKb3hA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745594727; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xNi29cUmvbhQyUeV6Au09yg4HVFM1Boo5sSDPMUFN5U=; b=U8f0JC8pb3qrIE4fpUIBe0nSDuvTD4JoIeJSBqKsBrH0K83cPdO1tUkEZbaTvbhe6C/ANeHG5sybNFU+VpBfXaIurOSwXiQrJ6TjILh5v3bmt+K4b+zXJ7I08xKOxnPmXeesLc+6ozYGrh4Gr4323xHnfGxtxYFhhLioKtY61wA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174559472705745.412658754650806; Fri, 25 Apr 2025 08:25:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u8Kth-0001hX-Sw; Fri, 25 Apr 2025 11:23:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u8Kte-0001ea-25 for qemu-devel@nongnu.org; Fri, 25 Apr 2025 11:23:22 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u8Kta-0002pg-9w for qemu-devel@nongnu.org; Fri, 25 Apr 2025 11:23:21 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-7376e311086so3238026b3a.3 for ; Fri, 25 Apr 2025 08:23:17 -0700 (PDT) Received: from stoup.. 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Fri, 25 Apr 2025 08:23:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 5/7] target/riscv: Pass ra to riscv_csrrw_i128 Date: Fri, 25 Apr 2025 08:23:09 -0700 Message-ID: <20250425152311.804338-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250425152311.804338-1-richard.henderson@linaro.org> References: <20250425152311.804338-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745594729122019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 4 ++-- target/riscv/csr.c | 8 ++++---- target/riscv/op_helper.c | 9 +++++---- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2c0524d0be..8b84793b15 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -851,8 +851,8 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState= *env, int csrno, RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, Int128 *ret_value); RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, - Int128 *ret_value, - Int128 new_value, Int128 write_mask); + Int128 *ret_value, Int128 new_value, + Int128 write_mask, uintptr_t ra); =20 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csr= no, Int128 *ret_value); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 097640e25d..a663f527a4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5656,8 +5656,8 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, in= t csrno, } =20 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, - Int128 *ret_value, - Int128 new_value, Int128 write_mask) + Int128 *ret_value, Int128 new_value, + Int128 write_mask, uintptr_t ra) { RISCVException ret; =20 @@ -5668,7 +5668,7 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, i= nt csrno, =20 if (csr_ops[csrno].read128) { return riscv_csrrw_do128(env, csrno, ret_value, - new_value, write_mask, 0); + new_value, write_mask, ra); } =20 /* @@ -5681,7 +5681,7 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, i= nt csrno, target_ulong old_value; ret =3D riscv_csrrw_do64(env, csrno, &old_value, int128_getlo(new_value), - int128_getlo(write_mask), 0); + int128_getlo(write_mask), ra); if (ret =3D=3D RISCV_EXCP_NONE && ret_value) { *ret_value =3D int128_make64(old_value); } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index aee16e2e3a..e3770a2655 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -108,7 +108,7 @@ void helper_csrw_i128(CPURISCVState *env, int csr, { RISCVException ret =3D riscv_csrrw_i128(env, csr, NULL, int128_make128(srcl, srch), - UINT128_MAX); + UINT128_MAX, GETPC()); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); @@ -116,13 +116,14 @@ void helper_csrw_i128(CPURISCVState *env, int csr, } =20 target_ulong helper_csrrw_i128(CPURISCVState *env, int csr, - target_ulong srcl, target_ulong srch, - target_ulong maskl, target_ulong maskh) + target_ulong srcl, target_ulong srch, + target_ulong maskl, target_ulong maskh) { Int128 rv =3D int128_zero(); RISCVException ret =3D riscv_csrrw_i128(env, csr, &rv, int128_make128(srcl, srch), - int128_make128(maskl, maskh)); + int128_make128(maskl, maskh), + GETPC()); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); --=20 2.43.0 From nobody Sat Nov 15 23:37:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745594702; cv=none; d=zohomail.com; s=zohoarc; b=ngrnjvdxQoFDCyw6O6xRBJckoS1aSKCRLbgt1J5Bh5l2O0+kGVWHvoe28J/GQtqJW2ES22HVLp0YU0nCiJ+w/Ms39myrZPmTWLucGABeQzlHmO3WVu7XfTpAT329wVgnVHrYI2D56JEdK+gfQp+iPjfJNRKwvr4qHl9/AJc0JkA= ARC-Message-Signature: i=1; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25a6a49esm3390466b3a.106.2025.04.25.08.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 08:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745594597; x=1746199397; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dwV8Ejbv3c17F+/2R9Q76cf7TrkhsGo+NtylDvgP+1E=; b=y4T1WAKaY5FQDggR/Yg3D5BwRLn+HBbnlLQcgjwlQz4/nyheUxjpV5HyzBHEVFZS/r HAyfLmbj56xnGl2uiZXll3kpRlvACjHIAoXhSQf4D4H49AzUF1Rp+v59FoRuH6l13am5 r579Vg2roKaYyTkpzNJIaou5Rl83hux8E7ntFAU2Wz37g6etc5jDPlslJ4HHIf9lELvi 11ybf7555lsAC+0bf5Ojnqm1LnIpttVp379pE4nUOXbVRVNSVLPFeMhDVQvFfKsOijpe xJSGHXQY3CzzhBCkiV3fe1qyqG53QMj1eRqTwolun5d3nDaxVw5K78VCD//cIJI6IerK 50pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745594597; x=1746199397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dwV8Ejbv3c17F+/2R9Q76cf7TrkhsGo+NtylDvgP+1E=; b=AK6LSOR33NoMJVxiD4+DBDljzVG8W+zude16G5stvJIvOlpQPIy+DJQoovimVWtvFk TOvXv+GmzsmNwIC5ObD0MlYcv5Ipj52sM53BBZcr8WVPXIANLON5McTRHGxnYGv+IXki VrxkoeUuhuShZFMt0Gwr6CW3brE71mR10qoVZxdjVbANoyBkKn3A5mOdwbGVdqpqViDs 6ykPJWh7aYZlqvsB7/RlGtNhgWMyW6WUaYLrKUlLKoYMM5j3blt/420zYqOQHCZGB8ge PKG5Ims+CTK3ojrIK2lJbs7fPlYglZc4hrw2CcwWBSLzVoNorfzOZZ6wO3HFb9/2HCqg OhqQ== X-Gm-Message-State: AOJu0YwcEP1JwU5P0bS77OuU0jEjwNmU081X88n9P5dOme5lN9qTLwcU pH4RggT2KEts7vSOZQI3BkNHESIaU0qLGAbOE11elMgXh8zm/j1wUw9MZs32o0RxrhU8elMkDd3 q X-Gm-Gg: ASbGnctFqApKPDKmf1HkYDj3mKWz55nfhIeNSEnCqyNR6ZrSVRERF1i/9fX16qQuccN rmA0JjgUCXY8mJMOakKCrJ6C1eJQ6H9oTnfQkpPK0XKQL63EjnNDpj4gXhfVurf47TR6DPxk/VL 9g/r58w38HpuB0AY2C8ie1aq0+TW5SXet48POzsvftddnVnpK73n4f84DYu4XZQaAIuaCtCrbQ5 nHAMoclIG8qraJcSq1SNJWTDTEYVt43yS5ALmUpDLX0AY1zI+W3Nht/R9MhggCv1N33Jq7LStNA +fPuU4r3F4ZVKllXyQ4Ow3yX9XFTctVqdqNzwuLrdgYpTJADYNlJueGO+p4Eoxoe5sPM17S76y4 = X-Google-Smtp-Source: AGHT+IE1ljSVGBswwJliWXa0YG8VO7kjEowpQi1dd/OABKviFszBcA03rv2tTtrGNrpOb53un5yt3w== X-Received: by 2002:a05:6a21:3401:b0:203:9660:9e4a with SMTP id adf61e73a8af0-2045b9fa3f7mr3856001637.41.1745594597634; Fri, 25 Apr 2025 08:23:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 6/7] target/riscv: Move insn_len to internals.h Date: Fri, 25 Apr 2025 08:23:10 -0700 Message-ID: <20250425152311.804338-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250425152311.804338-1-richard.henderson@linaro.org> References: <20250425152311.804338-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745594704497019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/internals.h | 5 +++++ target/riscv/translate.c | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 213aff31d8..4570bd50be 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -201,4 +201,9 @@ static inline target_ulong adjust_addr_virt(CPURISCVSta= te *env, return adjust_addr_body(env, addr, true); } =20 +static inline int insn_len(uint16_t first_word) +{ + return (first_word & 3) =3D=3D 3 ? 4 : 2; +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index cef61b5b29..9836ab8c20 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1210,11 +1210,6 @@ static uint32_t opcode_at(DisasContextBase *dcbase, = target_ulong pc) /* The specification allows for longer insns, but not supported by qemu. */ #define MAX_INSN_LEN 4 =20 -static inline int insn_len(uint16_t first_word) -{ - return (first_word & 3) =3D=3D 3 ? 4 : 2; -} - const RISCVDecoder decoder_table[] =3D { { always_true_p, decode_insn32 }, { has_xthead_p, decode_xthead}, --=20 2.43.0 From nobody Sat Nov 15 23:37:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745594728; cv=none; d=zohomail.com; s=zohoarc; b=mZJK8wKBFeb8Mpca0dzPNaH2j9WwZasYzmRNc8oYH4TRwyq1L6xkBphSxJg2AG4U7IolxW1U0IKIweuZvwQMQ6G3clKfbUIzif9Rh4cWHNxFGImaI24Hp47C5sx5A5IV20nzKR/souzGPaHgfggmgaD7DO/4+obUnP6QpUDGjCs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745594728; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Gj1TznuRCvGs0CqAqeiTcoQslN5U+5zXVdqj/kfvErI=; b=LjTKVha8NEpYYlJMg3w1qfpMpoA28AjYErFQoEhXTT39Z7x5ipfSKrHh2f1QWzlJqOSAaw0Geya7LGID3a0y1lqiwkv8nF9+QY1naP7ll1Uk1XUFTCXugmlr5Fq6YNKPt9VDRX7+Xj2AY2JQo5snr9dVjoH7b00MuZoLpU8/6Vs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745594728665463.59904821988516; Fri, 25 Apr 2025 08:25:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u8Kth-0001h0-B4; Fri, 25 Apr 2025 11:23:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u8Ktf-0001fT-Cr for qemu-devel@nongnu.org; Fri, 25 Apr 2025 11:23:23 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u8Ktc-0002qS-6r for qemu-devel@nongnu.org; Fri, 25 Apr 2025 11:23:23 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-7398d65476eso2015966b3a.1 for ; Fri, 25 Apr 2025 08:23:19 -0700 (PDT) Received: from stoup.. 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Fixes: f18637cd611 ("RISC-V: Add misa runtime write support") Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/csr.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a663f527a4..85f9b4c3d2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -30,6 +30,8 @@ #include "exec/icount.h" #include "qemu/guest-random.h" #include "qapi/error.h" +#include "tcg/insn-start-words.h" +#include "internals.h" #include =20 /* CSR function table public API */ @@ -2099,6 +2101,19 @@ static RISCVException read_misa(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 +static target_ulong get_next_pc(CPURISCVState *env, uintptr_t ra) +{ + uint64_t data[TARGET_INSN_START_WORDS]; + + /* Outside of a running cpu, env contains the next pc. */ + if (ra =3D=3D 0 || !cpu_unwind_state_data(env_cpu(env), ra, data)) { + return env->pc; + } + + /* Within unwind data, [0] is pc and [1] is the opcode. */ + return data[0] + insn_len(data[1]); +} + static RISCVException write_misa(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { @@ -2114,11 +2129,8 @@ static RISCVException write_misa(CPURISCVState *env,= int csrno, /* Mask extensions that are not supported by this hart */ val &=3D env->misa_ext_mask; =20 - /* - * Suppress 'C' if next instruction is not aligned - * TODO: this should check next_pc - */ - if ((val & RVC) && (GETPC() & ~3) !=3D 0) { + /* Suppress 'C' if next instruction is not aligned. */ + if ((val & RVC) && (get_next_pc(env, ra) & ~3) !=3D 0) { val &=3D ~RVC; } =20 --=20 2.43.0