From: Nikita Shubin <n.shubin@yadro.com>

Add STM32 DMA support for stm32f100 SoC.

Signals from periphery to DMA are not connected, as no STM32 periphery
currently supports DMA.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
---
 hw/arm/Kconfig                 |  1 +
 hw/arm/stm32f100_soc.c         | 51 ++++++++++++++++++++++++++++++++++
 include/hw/arm/stm32f100_soc.h |  3 ++
 3 files changed, 55 insertions(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 15200a2d7e..a51a8b8b9a 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -383,6 +383,7 @@ config STM32F100_SOC
     select ARM_V7M
     select STM32F2XX_USART
     select STM32F2XX_SPI
+    select STM32_DMA
 
 config STM32F205_SOC
     bool
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
index 53b5636452..dc864ef403 100644
--- a/hw/arm/stm32f100_soc.c
+++ b/hw/arm/stm32f100_soc.c
@@ -39,9 +39,29 @@
 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
     0x40004800 };
 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
+static const uint32_t dma_addr[STM_NUM_DMA] = { 0x40020000, 0x40020400 };
 
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
 static const int spi_irq[STM_NUM_SPIS] = {35, 36};
+static const uint8_t dma1_irq[] = {
+    11, /* DMA1 channel0 global interrupt */
+    12, /* DMA1 channel1 global interrupt */
+    13, /* DMA1 channel2 global interrupt */
+    14, /* DMA1 channel3 global interrupt */
+    15, /* DMA1 channel4 global interrupt */
+    16, /* DMA1 channel5 global interrupt */
+    17, /* DMA1 channel6 global interrupt */
+};
+
+static const uint8_t dma2_irq[] = {
+    56, /* DMA2 channel0 global interrupt */
+    57, /* DMA2 channel1 global interrupt */
+    58, /* DMA2 channel2 global interrupt */
+    59, /* DMA2 channel3 global interrupt */
+    59, /* DMA2 channel4/5 global interrupt */
+};
+
+static const uint8_t dma_chan_num[STM_NUM_DMA] = { 7, 6 };
 
 static void stm32f100_soc_initfn(Object *obj)
 {
@@ -59,6 +79,10 @@ static void stm32f100_soc_initfn(Object *obj)
         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
     }
 
+    for (i = 0; i < STM_NUM_DMA; i++) {
+        object_initialize_child(obj, "dma[*]", &s->dma[i], TYPE_STM32_DMA);
+    }
+
     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
     s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
 }
@@ -126,6 +150,33 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
         return;
     }
 
+    /* DMA 1 */
+    dev = DEVICE(&(s->dma[0]));
+    qdev_prop_set_uint8(dev, "nchans", dma_chan_num[0]);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma[0]), errp)) {
+        return;
+    }
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, dma_addr[0]);
+    for (i = 0; i < ARRAY_SIZE(dma1_irq); i++) {
+        sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, dma1_irq[i]));
+    }
+
+    /* DMA 2 */
+    dev = DEVICE(&(s->dma[1]));
+    qdev_prop_set_uint8(dev, "nchans", dma_chan_num[1]);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma[1]), errp)) {
+        return;
+    }
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, dma_addr[1]);
+    for (i = 0; i < ARRAY_SIZE(dma2_irq); i++) {
+        sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, dma2_irq[i]));
+    }
+
+    /* DMA channel 4 and 5 have shared irq */
+    sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, dma2_irq[i - 1]));
+
     /* Attach UART (uses USART registers) and USART controllers */
     for (i = 0; i < STM_NUM_USARTS; i++) {
         dev = DEVICE(&(s->usart[i]));
diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
index a74d7b369c..0ee02e157c 100644
--- a/include/hw/arm/stm32f100_soc.h
+++ b/include/hw/arm/stm32f100_soc.h
@@ -26,6 +26,7 @@
 #define HW_ARM_STM32F100_SOC_H
 
 #include "hw/char/stm32f2xx_usart.h"
+#include "hw/dma/stm32_dma.h"
 #include "hw/ssi/stm32f2xx_spi.h"
 #include "hw/arm/armv7m.h"
 #include "qom/object.h"
@@ -36,6 +37,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
 
 #define STM_NUM_USARTS 3
 #define STM_NUM_SPIS 2
+#define STM_NUM_DMA 2
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (128 * 1024)
@@ -49,6 +51,7 @@ struct STM32F100State {
 
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXSPIState spi[STM_NUM_SPIS];
+    STM32DmaState dma[STM_NUM_DMA];
 
     MemoryRegion sram;
     MemoryRegion flash;
-- 
2.48.1