From nobody Wed Apr 2 14:22:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742810752; cv=none; d=zohomail.com; s=zohoarc; b=GjFk5TCI5srkqz9UpmlDzlTw0dtH+oDLOycIesZEvOjDsfY58rkrGobqa6rtLE7JOg4AYBaLik+UTrZ6T4IBjyxjOozS7vwjVdWdItsl70VKNgkXtKPiNBg7HFWQkloV4NQMKeG8fZvqhKfHh0uAPjkIzff7lu3NmJ/vT4XH004= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742810752; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1wwVqIBAWpMO8Fgyh4dVKtbSrboBqVcDA7QCQp5Kcts=; b=MOaozSLrYyn/ManWuJ18yy+Cjtl0ea9vteFkZF3xwNh3k3NWrNI3EcY8UiENLYTY4DYI7LRwsZAa20QqHPhTkGW/klEk9t8zR8Ld1m9A3kbutA1sx44E2ydTnIEWdsqOcfiRtsDX5tj0pxtcee3XfDZ9JNP4tujo3Gvnewon9cc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742810752550990.9544348725669; Mon, 24 Mar 2025 03:05:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twegf-00068V-V8; Mon, 24 Mar 2025 06:05:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twegR-0005z1-H0; Mon, 24 Mar 2025 06:05:28 -0400 Received: from forward502d.mail.yandex.net ([178.154.239.210]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twegO-000524-8U; Mon, 24 Mar 2025 06:05:27 -0400 Received: from mail-nwsmtp-smtp-production-main-80.klg.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-80.klg.yp-c.yandex.net [IPv6:2a02:6b8:c42:2347:0:640:6ae5:0]) by forward502d.mail.yandex.net (Yandex) with ESMTPS id 98774610E9; Mon, 24 Mar 2025 13:05:16 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-80.klg.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id D5L6Pk2LeW20-qoyq0kPG; Mon, 24 Mar 2025 13:05:16 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1742810716; bh=1wwVqIBAWpMO8Fgyh4dVKtbSrboBqVcDA7QCQp5Kcts=; h=Message-ID:Date:In-Reply-To:Cc:Subject:References:To:From; b=Cfc5fK8wNcJplJXq8pHvm2XXo/q94nLWC8RN8DtYsarMZUqpy7Hp1FUrBTtvB6JyZ LZADGPRGKtXNbOIv4hgMDkjKyJMqNYtYUof/ldrS+sT7tNFBH/AQ+KRYUGKNhTfYWr HJ0SahhqPeYIwCsMCSTYs/Z0TQ+VizBFpmNCvEq8= Authentication-Results: mail-nwsmtp-smtp-production-main-80.klg.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: qemu-devel@nongnu.org Cc: Nikita Shubin , Paolo Bonzini , Peter Maydell , Alexandre Iooss , Alistair Francis , qemu-arm@nongnu.org Subject: [PATCH 2/3] hw/arm/stm32f100: Add DMA support for stm32f100 Date: Mon, 24 Mar 2025 13:05:07 +0300 Message-ID: <20250324100508.2176-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250324100508.2176-1-nikita.shubin@maquefel.me> References: <20250324100508.2176-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.154.239.210; envelope-from=nikita.shubin@maquefel.me; helo=forward502d.mail.yandex.net X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @maquefel.me) X-ZM-MESSAGEID: 1742810755711116600 Content-Type: text/plain; charset="utf-8" From: Nikita Shubin Add STM32 DMA support for stm32f100 SoC. Signals from periphery to DMA are not connected, as no STM32 periphery currently supports DMA. Signed-off-by: Nikita Shubin --- hw/arm/Kconfig | 1 + hw/arm/stm32f100_soc.c | 51 ++++++++++++++++++++++++++++++++++ include/hw/arm/stm32f100_soc.h | 3 ++ 3 files changed, 55 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 15200a2d7e..a51a8b8b9a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -383,6 +383,7 @@ config STM32F100_SOC select ARM_V7M select STM32F2XX_USART select STM32F2XX_SPI + select STM32_DMA =20 config STM32F205_SOC bool diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index 53b5636452..dc864ef403 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -39,9 +39,29 @@ static const uint32_t usart_addr[STM_NUM_USARTS] =3D { 0x40013800, 0x40004= 400, 0x40004800 }; static const uint32_t spi_addr[STM_NUM_SPIS] =3D { 0x40013000, 0x40003800 = }; +static const uint32_t dma_addr[STM_NUM_DMA] =3D { 0x40020000, 0x40020400 }; =20 static const int usart_irq[STM_NUM_USARTS] =3D {37, 38, 39}; static const int spi_irq[STM_NUM_SPIS] =3D {35, 36}; +static const uint8_t dma1_irq[] =3D { + 11, /* DMA1 channel0 global interrupt */ + 12, /* DMA1 channel1 global interrupt */ + 13, /* DMA1 channel2 global interrupt */ + 14, /* DMA1 channel3 global interrupt */ + 15, /* DMA1 channel4 global interrupt */ + 16, /* DMA1 channel5 global interrupt */ + 17, /* DMA1 channel6 global interrupt */ +}; + +static const uint8_t dma2_irq[] =3D { + 56, /* DMA2 channel0 global interrupt */ + 57, /* DMA2 channel1 global interrupt */ + 58, /* DMA2 channel2 global interrupt */ + 59, /* DMA2 channel3 global interrupt */ + 59, /* DMA2 channel4/5 global interrupt */ +}; + +static const uint8_t dma_chan_num[STM_NUM_DMA] =3D { 7, 6 }; =20 static void stm32f100_soc_initfn(Object *obj) { @@ -59,6 +79,10 @@ static void stm32f100_soc_initfn(Object *obj) object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_= SPI); } =20 + for (i =3D 0; i < STM_NUM_DMA; i++) { + object_initialize_child(obj, "dma[*]", &s->dma[i], TYPE_STM32_DMA); + } + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); s->refclk =3D qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); } @@ -126,6 +150,33 @@ static void stm32f100_soc_realize(DeviceState *dev_soc= , Error **errp) return; } =20 + /* DMA 1 */ + dev =3D DEVICE(&(s->dma[0])); + qdev_prop_set_uint8(dev, "nchans", dma_chan_num[0]); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma[0]), errp)) { + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, dma_addr[0]); + for (i =3D 0; i < ARRAY_SIZE(dma1_irq); i++) { + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, dma1_irq[i]= )); + } + + /* DMA 2 */ + dev =3D DEVICE(&(s->dma[1])); + qdev_prop_set_uint8(dev, "nchans", dma_chan_num[1]); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma[1]), errp)) { + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, dma_addr[1]); + for (i =3D 0; i < ARRAY_SIZE(dma2_irq); i++) { + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, dma2_irq[i]= )); + } + + /* DMA channel 4 and 5 have shared irq */ + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, dma2_irq[i - 1]= )); + /* Attach UART (uses USART registers) and USART controllers */ for (i =3D 0; i < STM_NUM_USARTS; i++) { dev =3D DEVICE(&(s->usart[i])); diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index a74d7b369c..0ee02e157c 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -26,6 +26,7 @@ #define HW_ARM_STM32F100_SOC_H =20 #include "hw/char/stm32f2xx_usart.h" +#include "hw/dma/stm32_dma.h" #include "hw/ssi/stm32f2xx_spi.h" #include "hw/arm/armv7m.h" #include "qom/object.h" @@ -36,6 +37,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) =20 #define STM_NUM_USARTS 3 #define STM_NUM_SPIS 2 +#define STM_NUM_DMA 2 =20 #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_SIZE (128 * 1024) @@ -49,6 +51,7 @@ struct STM32F100State { =20 STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; + STM32DmaState dma[STM_NUM_DMA]; =20 MemoryRegion sram; MemoryRegion flash; --=20 2.48.1