The following changes since commit 1dae461a913f9da88df05de6e2020d3134356f2e:

  Update version for v10.0.0-rc0 release (2025-03-18 10:18:14 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250319

for you to fetch changes up to ffe4db11f8aed79c7ec7d3ebd92674a1cfab4fe7:

  target/riscv: Add check for 16-bit aligned PC for different priv versions. (2025-03-19 17:11:46 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for 10.0

* Fix broken emulation link
* Optimize the memory probing for vector fault-only-first loads
* Fix access permission checks for CSR_SSP
* Fixes a bug against `ssamoswap` behavior in M-mode
* Fix IOMMU process directory table walk
* Fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()
* Enhance VSTART and VL checks for vector instructions
* Fix handling of cpu mask in riscv_hwprobe syscall
* Add check for 16-bit aligned PC for different priv versions

----------------------------------------------------------------
Chao Liu (2):
      target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter
      target/riscv: fix handling of nop for vstart >= vl in some vector instruction

Daniel Henrique Barboza (1):
      target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()

Deepak Gupta (2):
      target/riscv: fix access permission checks for CSR_SSP
      target/riscv: fixes a bug against `ssamoswap` behavior in M-mode

Jason Chien (1):
      hw/riscv/riscv-iommu: Fix process directory table walk

Paolo Savini (1):
      optimize the memory probing for vector fault-only-first loads.

Richard Henderson (1):
      linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall

Santiago Monserrat Campanello (1):
      docs/about/emulation: Fix broken link

Yu-Ming Chang (1):
      target/riscv: Add check for 16-bit aligned PC for different priv versions.

 docs/about/emulation.rst                      |   2 +-
 hw/riscv/riscv-iommu-bits.h                   |   6 +-
 target/riscv/cpu.h                            |  12 ++
 target/riscv/vector_internals.h               |  12 +-
 hw/riscv/riscv-iommu.c                        |   4 +-
 linux-user/syscall.c                          |  55 ++++----
 target/riscv/csr.c                            |   7 +-
 target/riscv/op_helper.c                      |   8 +-
 target/riscv/translate.c                      |   4 +-
 target/riscv/vcrypto_helper.c                 |  32 ++---
 target/riscv/vector_helper.c                  | 186 ++++++++++++++------------
 target/riscv/vector_internals.c               |   4 +-
 target/riscv/insn_trans/trans_rvi.c.inc       |   8 +-
 target/riscv/insn_trans/trans_rvzicfiss.c.inc |  17 +++
 14 files changed, 214 insertions(+), 143 deletions(-)