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Wed, 19 Mar 2025 01:03:19 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Santiago Monserrat Campanello , Alistair Francis , Thomas Huth Subject: [PULL 01/10] docs/about/emulation: Fix broken link Date: Wed, 19 Mar 2025 18:02:59 +1000 Message-ID: <20250319080308.609520-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250319080308.609520-1-alistair.francis@wdc.com> References: <20250319080308.609520-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1742371445565019000 Content-Type: text/plain; charset="utf-8" From: Santiago Monserrat Campanello semihosting link to risc-v changed Signed-off-by: Santiago Monserrat Campanello Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717 Reviewed-by: Alistair Francis Reviewed-by: Thomas Huth Message-ID: <20250305102632.91376-1-santimonserr@gmail.com> Signed-off-by: Alistair Francis --- docs/about/emulation.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst index 3bc3579434..a72591ee4d 100644 --- a/docs/about/emulation.rst +++ b/docs/about/emulation.rst @@ -171,7 +171,7 @@ for that architecture. - Unified Hosting Interface (MD01069) * - RISC-V - System and User-mode - - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semi= hosting-spec.adoc + - https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-s= emihosting.adoc * - Xtensa - System - Tensilica ISS SIMCALL --=20 2.48.1 From nobody Thu Apr 3 10:11:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-225c6ba6c8dsm107725255ad.156.2025.03.19.01.03.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Mar 2025 01:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742371403; x=1742976203; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=woS5shbhb+81BaLCop8v0D00aFw49LjawXYA3y+JHPY=; b=UqkoN2B2qv35BCr25S1VDkmGA0OJO89y6PeixV840amIWQt7EsRMMSGR/+dLhSBQPi ko3G/WQW/mmqLKuhMg+KC/VWnWQdXXGoQxzekGdVsN0f22kDk78w1HoIb+t6I3r8hf0f r77/Fckux1oVAzoSfbgw5z28haZFMMhRJ15g3ysYzeIQw0AO20VJN09rORtaS8VGkw+b 2Hp0Ue14t8z7Z2eXsEZUCREpsg1Q6wjzg5Z+Redj0hH0HNBxSshf7mJ2eNTsFDyhL/h5 E09JUa6C6g/GPl29bDnHPfrMC5/Aq+d0Q9XXIZcb4X4jw0siNQt7wjevArsjTgFdbH3s KbOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742371403; x=1742976203; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=woS5shbhb+81BaLCop8v0D00aFw49LjawXYA3y+JHPY=; b=anC5PARaEROOsw9enHGiCSV1osp02CsIebMMyyppyaXa7EG1hlYpmaY59BDfICrd6l UguYY2WgRM9xUVHRDqWsubNOQJmfsQ+xCHcIGVlfkhhpzlTa7nkyb7WhwV7/4zYekyI8 YZJGxki/gGEYqR0eoFWF1P+JsqQQ77LS3OxDPYLzC8h6cloMJT7ariCs2bcvOSCSX5wH xw4D0os7zisnBuZWq/Ka4oGleODII+maPKxmihQSZ9Cr3rwCvCujK46ouCiyPXzqtPxD cdAKxbzLicceC3VVFCxJJivb+7vRuAYVFeA9dkSMsMrZH/m+yxg0NPPkiU1dDR05f8MO tLqA== X-Gm-Message-State: AOJu0YzAyyBYnavSrJr7hS7yrzGf9PYH+bxUPNAjFJn335wXnvwhZXal E7E+lnIYg/8ko62a2yOO8+0Q2/43xjLiih8UjdRmh3mGLzkCQf03jqeSHw== X-Gm-Gg: ASbGncuif2vgrVLLjP0s0RbIbyAJD5H8O6ymWPLo1TG1dIPa5UZKTz48Wo03hP2wotY hFF5QlFwn99abhmeqqyHkfWaZ09wM1MN4Dc/mgvWsaaMRf7Uc7OAKq9IOwgQvyHkAZE3YxzAY67 VcFLLbOD055N7Hvs8J2JM9ssAHxi7sasWcp9/XClWrSR+Yw90HorcUYnMUqFBcZqlxREnkj9YVS 77SdYw5nZysPmqev3mx04PTUH9Oki6Ls3cg0s/bpFB4y4U7EdEGdrNlxGwjnV0mb0p/3LVugcC4 M0o3SPj+Pn3Qc7LJPOHXr8n+rfRRLFlcFbgEn8GT0VoU4STJjsCThcnFY+u7qJQ9CXgm+FQqHFt Uyo+x/OFJfkCgCNtPG2+XCCjRqKa2LG3ERf8g1KFhc6W5VRdc X-Google-Smtp-Source: AGHT+IFWrlOzBsrKezCIgsKRr5rtUp42EBhYULlSvO1ntd0HyC8w8Xkasi7WEwqlog5NQrRZfnoKoA== X-Received: by 2002:a17:902:da8c:b0:224:1074:63a0 with SMTP id d9443c01a7336-22649a80c34mr24066465ad.34.1742371403166; Wed, 19 Mar 2025 01:03:23 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Paolo Savini , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 02/10] optimize the memory probing for vector fault-only-first loads. Date: Wed, 19 Mar 2025 18:03:00 +1000 Message-ID: <20250319080308.609520-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250319080308.609520-1-alistair.francis@wdc.com> References: <20250319080308.609520-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1742374316414019100 Content-Type: text/plain; charset="utf-8" From: Paolo Savini Fault-only-first loads in the RISC-V vector extension need to update the vl with the element index that causes an exception. In order to ensure this the emulation of this instruction used to probe the memory covered by the load operation with a loop that iterated over each el= ement so that when a flag was raised it was possible to set the vl to the corresponding element index. This loop was executed every time whether an exception happened or not. This commit removes the per element memory probing from the main execution = path and adds a broad memory probing first. If this probing raises any flag that= is not a watchpoint flag (that per standard is allowed by this instruction) we proceed with the per element probing to find the index of the element causi= ng the exception and set vl to such index. Signed-off-by: Paolo Savini Reviewed-by: Daniel Henrique Barboza Message-ID: <20250221155320.59159-2-paolo.savini@embecosm.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 103 ++++++++++++++++++++--------------- 1 file changed, 58 insertions(+), 45 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7773df6a7c..71b823d5d4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -633,47 +633,69 @@ vext_ldff(void *vd, void *v0, target_ulong base, CPUR= ISCVState *env, uint32_t esz =3D 1 << log2_esz; uint32_t msize =3D nf * esz; uint32_t vma =3D vext_vma(desc); - target_ulong addr, offset, remain, page_split, elems; + target_ulong addr, addr_probe, addr_i, offset, remain, page_split, ele= ms; int mmu_index =3D riscv_env_mmu_index(env, false); + int flags; + void *host; =20 VSTART_CHECK_EARLY_EXIT(env); =20 - /* probe every access */ - for (i =3D env->vstart; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - continue; - } - addr =3D adjust_addr(env, base + i * (nf << log2_esz)); - if (i =3D=3D 0) { - /* Allow fault on first element. */ - probe_pages(env, addr, nf << log2_esz, ra, MMU_DATA_LOAD); - } else { - remain =3D nf << log2_esz; - while (remain > 0) { - void *host; - int flags; - - offset =3D -(addr | TARGET_PAGE_MASK); - - /* Probe nonfault on subsequent elements. */ - flags =3D probe_access_flags(env, addr, offset, MMU_DATA_L= OAD, - mmu_index, true, &host, 0); - - /* - * Stop if invalid (unmapped) or mmio (transaction may fai= l). - * Do not stop if watchpoint, as the spec says that - * first-fault should continue to access the same - * elements regardless of any watchpoint. - */ - if (flags & ~TLB_WATCHPOINT) { - vl =3D i; - goto ProbeSuccess; - } - if (remain <=3D offset) { - break; + addr =3D base + ((env->vstart * nf) << log2_esz); + page_split =3D -(addr | TARGET_PAGE_MASK); + /* Get number of elements */ + elems =3D page_split / msize; + if (unlikely(env->vstart + elems >=3D env->vl)) { + elems =3D env->vl - env->vstart; + } + + /* Check page permission/pmp/watchpoint/etc. */ + flags =3D probe_access_flags(env, adjust_addr(env, addr), elems * msiz= e, + MMU_DATA_LOAD, mmu_index, true, &host, ra); + + /* If we are crossing a page check also the second page. */ + if (env->vl > elems) { + addr_probe =3D addr + (elems << log2_esz); + flags |=3D probe_access_flags(env, adjust_addr(env, addr_probe), + elems * msize, MMU_DATA_LOAD, mmu_inde= x, + true, &host, ra); + } + + if (flags & ~TLB_WATCHPOINT) { + /* probe every access */ + for (i =3D env->vstart; i < env->vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + continue; + } + addr_i =3D adjust_addr(env, base + i * (nf << log2_esz)); + if (i =3D=3D 0) { + /* Allow fault on first element. */ + probe_pages(env, addr_i, nf << log2_esz, ra, MMU_DATA_LOAD= ); + } else { + remain =3D nf << log2_esz; + while (remain > 0) { + offset =3D -(addr_i | TARGET_PAGE_MASK); + + /* Probe nonfault on subsequent elements. */ + flags =3D probe_access_flags(env, addr_i, offset, + MMU_DATA_LOAD, mmu_index, t= rue, + &host, 0); + + /* + * Stop if invalid (unmapped) or mmio (transaction may + * fail). Do not stop if watchpoint, as the spec says = that + * first-fault should continue to access the same + * elements regardless of any watchpoint. + */ + if (flags & ~TLB_WATCHPOINT) { + vl =3D i; + goto ProbeSuccess; + } + if (remain <=3D offset) { + break; + } + remain -=3D offset; + addr_i =3D adjust_addr(env, addr_i + offset); } - remain -=3D offset; - addr =3D adjust_addr(env, addr + offset); } } } @@ -685,15 +707,6 @@ ProbeSuccess: =20 if (env->vstart < env->vl) { if (vm) { - /* Calculate the page range of first page */ - addr =3D base + ((env->vstart * nf) << log2_esz); - page_split =3D -(addr | TARGET_PAGE_MASK); - /* Get number of elements */ - elems =3D page_split / msize; - if (unlikely(env->vstart + elems >=3D env->vl)) { - elems =3D env->vl - env->vstart; - } - /* Load/store elements in the first page */ if (likely(elems)) { vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, --=20 2.48.1 From nobody Thu Apr 3 10:11:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1742371445; cv=none; d=zohomail.com; s=zohoarc; b=RCLMrU/E4UCQkx0fXNuEHwtJeosQdCkQx1FaM0sjn1J/D2/Mp9qI2T2TMYGjOuvnPT/AZIiYeYnRNPYuk+NsIKlETZogKB15V5zzF68uhrtBVSUyQJJd8ucnRGRMUv5PJEJanc7VUGp+fRBvtHC3wwbu/8HrOZ9XrZHl9ygSMHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742371445; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rknrmfA7CmFKA8NZIq2TcdDuCQaG1etacbJiGQO7Y4w=; b=h1qpjmg+LrgsCOvt01czL0AHTZd3jravbsd/7rv7/gWINOh9N3ynLdCy3ch+UmU97t935W/5S56tTp+jcHGeyznyhuFtiKQO9MTqeed6ZlKcVnQXA+/Wagd1JtuGo+e57t20zM9VnrLDicrjrQopT+Jf9eLtzM0EkY/TFeMqzUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17423714450672.162164324250739; Wed, 19 Mar 2025 01:04:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuoOv-00081K-CU; Wed, 19 Mar 2025 04:03:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuoOg-0007zp-Gr for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:31 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuoOe-0004PA-OW for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:30 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-2241053582dso29945645ad.1 for ; Wed, 19 Mar 2025 01:03:27 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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Gated to CSR_SSP is not gated via `xSSE`. But rather rules clearly specified in section "22.2.1. Shadow Stack Pointer (ssp) CSR access contr" in the priv spec. Fixes: 8205bc127a83 ("target/riscv: introduce ssp and enabling controls for zicfiss". Thanks to Adam Zabrocki for bringing this to attention. Reported-by: Adam Zabrocki Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis Message-ID: <20250306064636.452396-1-debug@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 49566d3c08..8225e9bb4b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -192,6 +192,11 @@ static RISCVException cfi_ss(CPURISCVState *env, int c= srno) return RISCV_EXCP_ILLEGAL_INST; } =20 + /* If ext implemented, M-mode always have access to SSP CSR */ + if (env->priv =3D=3D PRV_M) { + return RISCV_EXCP_NONE; + } + /* if bcfi not active for current env, access to csr is illegal */ if (!cpu_get_bcfien(env)) { #if !defined(CONFIG_USER_ONLY) --=20 2.48.1 From nobody Thu Apr 3 10:11:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1742371607; cv=none; d=zohomail.com; s=zohoarc; b=RnQYC8z54oNXVU6NXFoSp+5rkhTfSIDfaW/YV0rXI++lji19EbV+aGfd3+FGW0Y8dWtAJwzXfjOdWu7adJkLQ9wr/CoLbhlS+0u0JVkoptVeQlHWTh2no0b7kDsmC1gy0XaWZ6aOBB10uqqebZUZnLUoaHyubkTJ1q2DAL6Fy0s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742371607; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D41W4Q8+joe9dO5MBm79suNRGDyG9oLnqdd8A4ljE2s=; b=jaKm0v4yW01jl9akH+ysnM8GTHwPOkUWFkn2bqDOZD/B2r1Prf1APRHdAZahjrmBDaA1JDLZSIe7GZQO+c5agUz3MLhYNV1LBuDGKBNVI/DFcyaw7gzimfBAgV7sF49pp1w+VZu5jXYRiYX7jNh6uVCXC/TG8nkcUUhzvXh7R5I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742371607054765.3065902651022; Wed, 19 Mar 2025 01:06:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuoPZ-0008Vw-GE; Wed, 19 Mar 2025 04:04:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuoOk-00080w-2S for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:34 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuoOi-0004Q6-0m for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:33 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2260c91576aso55807885ad.3 for ; Wed, 19 Mar 2025 01:03:31 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-225c6ba6c8dsm107725255ad.156.2025.03.19.01.03.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Mar 2025 01:03:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742371410; x=1742976210; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D41W4Q8+joe9dO5MBm79suNRGDyG9oLnqdd8A4ljE2s=; b=OqVfxSFExO++3Cj3FCYp6KZjfLcAT4Dvy0QRQHWaKC+AZF7NG1Me0pWZKTH6G+87dB FbK+HsiMiYBQyq91p3xBU7CrYe3jLlDa55r4DGGTOYZBfh72rh1hbFO8DnD6KAyphHWY jxIhtj4ajOEDauTcdRB101mZb69huDxffFEM6xsz01PC1YK2/qBM98XkvFH+YW7jy/At DUEXHV4Ws2QzofdXy9Eh3CFcqp9sn3FRrUkjy8lJ/V+L4fE25EqM4w5I/oCZrO6tv+X/ HSN6y+SwSLZVl24zNvdSCmo69sASDkRK27BOHdvxpesdLMWfUk0Kixt2S8QBycJxT8xa WQAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742371410; x=1742976210; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D41W4Q8+joe9dO5MBm79suNRGDyG9oLnqdd8A4ljE2s=; b=MAOv36Gl69+FwmP+PFovEMjEW17GfAEjdYbuRYCJaJ3LGryLe5QVVMneVGQryAPrCy ZWX7rr+OyCVzmR0nlBkNahIRI3vp0F8Tz5XHObhWWqs0kaK/vs/ecO1gHjcUJumPNCnC miWW63E3TERTRrAsyw0vO8AvCJ8LADNJsAcMTUQmAfhIoWp7xysyFnUi4uH/BB7VPELV f/S8khMyp/3Ty+RcB9i+oaHiZJozCkszKYX598kz5uKwm0q2k7KR8XPVkJNY1vuqu5IO a+bz8XbA4SAFW0YS51mllht37H2ElqeW2uvkeVpa95+6mKmISoLIQ3hrsaIFxWuaeSx5 TaHw== X-Gm-Message-State: AOJu0YxWgylmszddEjh7hMWp7pSbTo26GeDExYFxO09Br/lEbLkZ4dXo 4p3eTY7sqvyU28EuXmERotdxwE/b8d4wsTlBBwS0DkeUnFTE3lpc6/EqyQ== X-Gm-Gg: ASbGncutdxq7y7z8fQZxno8Y4B/0kOxjmug3uAlvOYbnCjOwfkesV8k2h2O9fTCdgyE jF2N+NGiurhgsfWz1mL/V8oQcHn7zkfl8WkGzXW/MiO8c5ZU3qwZAw03yS+SBzKeH72i/XfBxOG M/R1lsyveoKRWlv5p3mrawLprkXp642yL/e0FOcGgBFkSwQ9//5grTw9bdHnsDkV+3kQGYOg99E mHc7iuEooxmT4it1jd28QPH/R6Zk2OxEmDi7VxUacc4G3vEMWXP37AZBZU+rziswezzB/g0DuyB g4aEAvj6SYqfsm/wLg9Q3WSur8w02J6YuvWq+VEk3pvYSuJK4bdS0uaKHjmlyTRGgzWPL9qVZKD zWCTACExlwmMFyABH++4utEgaqmXURLs+vMfoMFyMnEBVWLwQ X-Google-Smtp-Source: AGHT+IESFOJd/uy3NCSaU1KtHRzUNvfsJy493/9GQK0XHTUe/3TRiKWV3RYRTKkhKgZbg44zWEQptg== X-Received: by 2002:a17:902:e846:b0:223:37ec:63d3 with SMTP id d9443c01a7336-22649a2f067mr23379685ad.18.1742371410383; Wed, 19 Mar 2025 01:03:30 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Deepak Gupta , Ved Shanbhogue , Alistair Francis Subject: [PULL 04/10] target/riscv: fixes a bug against `ssamoswap` behavior in M-mode Date: Wed, 19 Mar 2025 18:03:02 +1000 Message-ID: <20250319080308.609520-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250319080308.609520-1-alistair.francis@wdc.com> References: <20250319080308.609520-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1742371607739019000 Content-Type: text/plain; charset="utf-8" From: Deepak Gupta Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds `ssamoswap` instruction. `ssamoswap` takes the code-point from existing reserved encoding (and not a zimop like other shadow stack instructions). If shadow stack is not enabled (via xenvcfg.SSE) and effective priv is less than M then `ssamoswap` must result in an illegal instruction exception. However if effective priv is M, then `ssamoswap` results in store/AMO access fault. See Section "22.2.3. Shadow Stack Memory Protection" of priv spec. Fixes: f06bfe3dc38c ("target/riscv: implement zicfiss instructions") Reported-by: Ved Shanbhogue Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis Message-ID: <20250306064636.452396-2-debug@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index e3ebc4977c..b0096adcd0 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -15,6 +15,13 @@ * You should have received a copy of the GNU General Public License along= with * this program. If not, see . */ + +#define REQUIRE_ZICFISS(ctx) do { \ + if (!ctx->cfg_ptr->ext_zicfiss) { \ + return false; \ + } \ +} while (0) + static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a) { if (!ctx->bcfi_enabled) { @@ -77,6 +84,11 @@ static bool trans_ssrdp(DisasContext *ctx, arg_ssrdp *a) static bool trans_ssamoswap_w(DisasContext *ctx, arg_amoswap_w *a) { REQUIRE_A_OR_ZAAMO(ctx); + REQUIRE_ZICFISS(ctx); + if (ctx->priv =3D=3D PRV_M) { + generate_exception(ctx, RISCV_EXCP_STORE_AMO_ACCESS_FAULT); + } + if (!ctx->bcfi_enabled) { return false; } @@ -97,6 +109,11 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_am= oswap_w *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); + REQUIRE_ZICFISS(ctx); + if (ctx->priv =3D=3D PRV_M) { + generate_exception(ctx, RISCV_EXCP_STORE_AMO_ACCESS_FAULT); + } + if (!ctx->bcfi_enabled) { return false; } --=20 2.48.1 From nobody Thu Apr 3 10:11:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1742371474; cv=none; d=zohomail.com; s=zohoarc; b=J4kQaO6BTqEA2bFo0XxM3H/5cxARyu5UZYBN57Nq60o9MYICn3cTodQazoFnvclgxkxb6GTzMW12/JsgPNaRKVqRd6sZ9YgpBIgyRGYzqIqUoh6Zc/udoAjeF5ZXclbU+8L1GFkQdPa+61m0Vr54cRqeXGEdaCdWpeSfF9EdqFI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742371474; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bT/bW29GwGcJx+ezk5/UB0aQ+0X7tJA6z6SWSn/AAEY=; b=fNCGczmxMJtJNJCUTM1BbLZktBz9t8hJppX4z7jEiQEedYF+YQIjwP519jMtAOiOs4cl1F1ZWEQA7OF4XSSDLq86zXYofOKqMjESxSDJDQFofLZnOzlnQ72ogLjTIVdPpsO6lPNaW7aEWvkwcPtxBO+Sp430viUhEA2LgnpZ+nA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174237147407547.5914468660128; Wed, 19 Mar 2025 01:04:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuoPY-0008QO-CK; Wed, 19 Mar 2025 04:04:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuoOn-00081X-Lm for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:43 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuoOl-0004Qb-VT for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:37 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-2239c066347so139691025ad.2 for ; Wed, 19 Mar 2025 01:03:35 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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The original implementation incorrectly used the leaf entry's PPN mask to extract the PPN from a non-leaf entry, leading to an erroneous page table walk. This commit introduces new macros to properly define the fields for non-leaf PDT entries and corrects the page table walk. Signed-off-by: Jason Chien Reviewed-by: Daniel Henrique Barboza Message-ID: <20250301173751.9446-1-jason.chien@sifive.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 6 +++++- hw/riscv/riscv-iommu.c | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h index b7cb1bc736..1017d73fc6 100644 --- a/hw/riscv/riscv-iommu-bits.h +++ b/hw/riscv/riscv-iommu-bits.h @@ -415,12 +415,16 @@ enum riscv_iommu_fq_causes { #define RISCV_IOMMU_DC_MSIPTP_MODE_OFF 0 #define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT 1 =20 +/* 2.2 Process Directory Table */ +#define RISCV_IOMMU_PDTE_VALID BIT_ULL(0) +#define RISCV_IOMMU_PDTE_PPN RISCV_IOMMU_PPN_FIELD + /* Translation attributes fields */ #define RISCV_IOMMU_PC_TA_V BIT_ULL(0) #define RISCV_IOMMU_PC_TA_RESERVED GENMASK_ULL(63, 32) =20 /* First stage context fields */ -#define RISCV_IOMMU_PC_FSC_PPN GENMASK_ULL(43, 0) +#define RISCV_IOMMU_PC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD #define RISCV_IOMMU_PC_FSC_RESERVED GENMASK_ULL(59, 44) =20 enum riscv_iommu_fq_ttypes { diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index d46beb2d64..76e0fcd873 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -1042,10 +1042,10 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s= , RISCVIOMMUContext *ctx) return RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT; } le64_to_cpus(&de); - if (!(de & RISCV_IOMMU_PC_TA_V)) { + if (!(de & RISCV_IOMMU_PDTE_VALID)) { return RISCV_IOMMU_FQ_CAUSE_PDT_INVALID; } - addr =3D PPN_PHYS(get_field(de, RISCV_IOMMU_PC_FSC_PPN)); + addr =3D PPN_PHYS(get_field(de, RISCV_IOMMU_PDTE_PPN)); } =20 riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_PD_WALK); --=20 2.48.1 From nobody Thu Apr 3 10:11:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1742371603; cv=none; d=zohomail.com; s=zohoarc; b=K/cnR7AkS97a8iaTZDHQ+AZuVL4e950lIyXBOWebtt1akadEDW6aotyALQGxpacLpjZuF7PHHXSP8oNWbBC9mEm5Tz3P+F3WMqmt/xH9BgIO1zC4lBeW2mlLaf1DA6AtNLKMqaDBC6twriF8mDlyJ9WWOQUR8kKsANxkkMhGpWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742371603; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+GZozLRxbDuwVPT+dECukr5ZKZWvyjcyqsgsCIhcR3E=; b=LjS1DD7nJzEq+oE0Jvx2GtGCN+QSk0XOFf2gRc/QtfMKhvX2T3mxs9/edViW6qM8FO9mrC7mtUQDo2N9QAGtc3TVH63WGL9SXBWQ9nMVxpOF3ccCy9yrrMzQxotnZvExxrIPKqwiwbaxA7rKJ5wo55yLaparNx49GlcR4+XlDYk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742371603423753.6140784914868; Wed, 19 Mar 2025 01:06:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuoPZ-0008Vx-GE; Wed, 19 Mar 2025 04:04:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuoOr-00082H-Vg for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:43 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuoOp-0004RG-4v for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:41 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-225a28a511eso111789325ad.1 for ; Wed, 19 Mar 2025 01:03:38 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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Resolves: Coverity CID 1593156 Fixes: c48bd18eae ("target/riscv: Add support for Control Transfer Records = extension CSRs.") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250307124602.1905754-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8225e9bb4b..7948188356 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -4302,7 +4302,7 @@ static RISCVException rmw_sctrdepth(CPURISCVState *en= v, int csrno, } =20 /* Update sctrstatus.WRPTR with a legal value */ - depth =3D 16 << depth; + depth =3D 16ULL << depth; env->sctrstatus =3D env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1)); } --=20 2.48.1 From nobody Thu Apr 3 10:11:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1742371572; cv=none; d=zohomail.com; s=zohoarc; b=TgxarzWtTUXH1b4A+u9A8wwsguspxGTF8RyYM2OsaSeYKlWTsYOkDBdyRiGMmsZabPKJ8tjBlDCURKBsWreyJlclr9oSUDw83SQXwRQ6xZVFxS32oCPFu7hIyZiqcAsMPgX+h81XzvuqBdgaf4/zf5LZIE0gE7Ufa26FyTsmFbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742371572; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zZtaI2LPwyCYv21aReKRYOqNA1C4T/+IrDFAVcQAkcg=; b=JTMau9/Kx7EwBTIc9awojbPg6NAT8wihkVXlNCiH8poSaaYrO8f8UXa7Oy2FV9rRyoVCgfF1cEDP+sPrvVE9buXsRREezCUSUttMNOaFQPuUR3uG7uCq+LhF+OkYUyi8R1GQ2mLEEFCSOn6xFaS7qwlNAwsxyL71J98sMgh2g9k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742371572000698.869525716757; Wed, 19 Mar 2025 01:06:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuoPh-0000Iv-Je; Wed, 19 Mar 2025 04:04:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuoOv-00082i-JL for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:49 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuoOs-0004Rc-EF for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:45 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-223fb0f619dso110557135ad.1 for ; Wed, 19 Mar 2025 01:03:42 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-225c6ba6c8dsm107725255ad.156.2025.03.19.01.03.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Mar 2025 01:03:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742371421; x=1742976221; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zZtaI2LPwyCYv21aReKRYOqNA1C4T/+IrDFAVcQAkcg=; b=d44yCwrK0ZrbemjDbVaMghkeBP3QCEh5/DCuA1XWfmzvWKvsAZPUJ1H59aTkh9wXGn Wf2gZQMVaszMx82TvvPZDI+y2xz/DUOveyK0Q7zHLFvJOzhP0837on8Q333Z+jj+ccQ3 /WrRQ1tVzuNZrAMKv3+VNaoyeXYwbs7xsCANqQIlRVntsa7VAQiaDz+KIsGaOYZZixAV 8OFY1yOVuySpor/U1tWYKnNo7XoAUtZw1ybH7e0Mh9PAQc3c62EBJmceWXl7yyEWqfgq Ws1I+/HfESc3V74w8syh9QWbfjT/dBNPuhtvz0wjS0aD9mZ/IlzSOUL6vHsrwC6r1Q/o KmUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742371421; x=1742976221; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zZtaI2LPwyCYv21aReKRYOqNA1C4T/+IrDFAVcQAkcg=; b=MyhXnoFFXYk0m6Ed7hiFBz+cEdTsy/v++idAgBcn4uQdgCalA7djBsGXbkawlCoJxP 4HcnTwZctyq6rAp6apxrA6ZbUeMNtTM+PUdYW1F4oekiHvt5IZhLmIrJfY0H45rQslcw KUAXl759hOW3VFnXJnIQJmCs7BQc2zYagfJli00INA/elRmeJDeDf7Q71Sdr5TbKZzPa /mRuG4WzxIUBGSScpWRd/o7FI9UyZ2ozUTo18FhMxdp76yHvgYdoao9TZX/6vtgsC+KI QzzLKMnKmfSnLnWtglmE5M7M7RjeFPPVe25DPxFUYucEtr9bmRStdyg3YBGuQnzrjSj0 JSFQ== X-Gm-Message-State: AOJu0YwY17Wey+lved4R/Wh4Eh1ee92RZIewVdxg8C4ChgtvCcYsXYaV B+5QkzsQbMiff7sWtzQYkvUbND6WvwHi/3DnWjif0u7Sl+/GJXxZBTAj0g== X-Gm-Gg: ASbGncvW8Nau6GNTzIbSQVw1kUebJKEBz6JZCwlgTIaNRhB8uh5+YLXAAdzdzMWNYyK eVBy8H734TJQX1+b0rB4fOkHAwAiBok40SvgPPCKAgWxSQxazVu7ROxrV8V4kD7xwTPUHvCHhnU s6YGYkApHCHPSOI9rJXpgo6bfTerLAZnep0mALP2TCuv9Rch5bJWFtkIuPdR1KXX8UZAoSY4JEJ DSgr/V0zWnVo6GNYfQwh1WSSX4WfUPBgk2zyJrPImcpcudyLmrDXvTVk+6nZW/f1MTonTyCjaMn YKoW1ts+Nvi84it9E+uN42VX6N+E9fwcEI0t9FkWJpInlm2YgYEvlvp3JidqRuZxXrzSTfM7o5I V2QM2JQKYFhEEZNaTkU1CGD/cs8GNK57vaURohnnydrrIH73y X-Google-Smtp-Source: AGHT+IGDro9Oo843uM1QVx4ckswysrDgZke06l5xs4b9isVfDbjOUmAV0s11ShyspyEfhx/W04xSkQ== X-Received: by 2002:a17:902:d488:b0:224:13a4:d62e with SMTP id d9443c01a7336-22649a7c1afmr25349965ad.35.1742371420533; Wed, 19 Mar 2025 01:03:40 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Chao Liu , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 07/10] target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter Date: Wed, 19 Mar 2025 18:03:05 +1000 Message-ID: <20250319080308.609520-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250319080308.609520-1-alistair.francis@wdc.com> References: <20250319080308.609520-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1742371574286019100 Content-Type: text/plain; charset="utf-8" From: Chao Liu Some vector instructions are special, such as the vlm.v instruction, where setting its vl actually sets evl =3D (vl + 7) >> 3. To improve maintainability, we will uniformly use VSTART_CHECK_EARLY_EXIT() to check for the condition vstart >=3D vl. This function will also handle cases involving evl. Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when vstart >=3D vl") Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Message-ID: Signed-off-by: Alistair Francis --- target/riscv/vector_internals.h | 12 +++--- target/riscv/vcrypto_helper.c | 32 +++++++-------- target/riscv/vector_helper.c | 69 ++++++++++++++++----------------- target/riscv/vector_internals.c | 4 +- 4 files changed, 57 insertions(+), 60 deletions(-) diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h index a11cc8366d..8eee7e5c31 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -25,11 +25,11 @@ #include "tcg/tcg-gvec-desc.h" #include "internals.h" =20 -#define VSTART_CHECK_EARLY_EXIT(env) do { \ - if (env->vstart >=3D env->vl) { \ - env->vstart =3D 0; \ - return; \ - } \ +#define VSTART_CHECK_EARLY_EXIT(env, vl) do { \ + if (env->vstart >=3D vl) { \ + env->vstart =3D 0; \ + return; \ + } \ } while (0) =20 static inline uint32_t vext_nf(uint32_t desc) @@ -159,7 +159,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index f7423df226..1526de96f5 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -222,7 +222,7 @@ static inline void xor_round_key(AESState *round_state,= AESState *round_key) uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ uint32_t vta =3D vext_vta(desc); = \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ AESState round_key; \ @@ -248,7 +248,7 @@ static inline void xor_round_key(AESState *round_state,= AESState *round_key) uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ uint32_t vta =3D vext_vta(desc); = \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ AESState round_key; \ @@ -309,7 +309,7 @@ void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, = uint32_t uimm, uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); uint32_t vta =3D vext_vta(desc); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, vl); =20 uimm &=3D 0b1111; if (uimm > 10 || uimm =3D=3D 0) { @@ -357,7 +357,7 @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, = uint32_t uimm, uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); uint32_t vta =3D vext_vta(desc); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, vl); =20 uimm &=3D 0b1111; if (uimm > 14 || uimm < 2) { @@ -465,7 +465,7 @@ void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2,= CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { if (sew =3D=3D MO_32) { @@ -582,7 +582,7 @@ void HELPER(vsha2ch32_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, @@ -602,7 +602,7 @@ void HELPER(vsha2ch64_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, @@ -622,7 +622,7 @@ void HELPER(vsha2cl32_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, @@ -642,7 +642,7 @@ void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, uint32_t total_elems; uint32_t vta =3D vext_vta(desc); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, @@ -676,7 +676,7 @@ void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, v= oid *vs2_vptr, uint32_t *vs1 =3D vs1_vptr; uint32_t *vs2 =3D vs2_vptr; =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { uint32_t w[24]; @@ -777,7 +777,7 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, ui= nt32_t uimm, uint32_t *vs2 =3D vs2_vptr; uint32_t v1[8], v2[8], v3[8]; =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { for (int k =3D 0; k < 8; k++) { @@ -802,7 +802,7 @@ void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, vo= id *vs2_vptr, uint32_t vta =3D vext_vta(desc); uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { uint64_t Y[2] =3D {vd[i * 2 + 0], vd[i * 2 + 1]}; @@ -841,7 +841,7 @@ void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CP= URISCVState *env, uint32_t vta =3D vext_vta(desc); uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { uint64_t Y[2] =3D {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])}; @@ -879,7 +879,7 @@ void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uim= m5, CPURISCVState *env, uint32_t esz =3D sizeof(uint32_t); uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D group_start; i < group_end; ++i) { uint32_t vstart =3D i * egs; @@ -937,7 +937,7 @@ void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVStat= e *env, uint32_t desc) uint32_t esz =3D sizeof(uint32_t); uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D group_start; i < group_end; ++i) { uint32_t vstart =3D i * egs; @@ -973,7 +973,7 @@ void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVStat= e *env, uint32_t desc) uint32_t esz =3D sizeof(uint32_t); uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (uint32_t i =3D group_start; i < group_end; ++i) { uint32_t vstart =3D i * egs; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 71b823d5d4..217d2f60a5 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -260,7 +260,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,= target_ulong stride, uint32_t esz =3D 1 << log2_esz; uint32_t vma =3D vext_vma(desc); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 for (i =3D env->vstart; i < env->vl; env->vstart =3D ++i) { k =3D 0; @@ -383,10 +383,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVStat= e *env, uint32_t desc, uint32_t msize =3D nf * esz; int mmu_index =3D riscv_env_mmu_index(env, false); =20 - if (env->vstart >=3D evl) { - env->vstart =3D 0; - return; - } + VSTART_CHECK_EARLY_EXIT(env, evl); =20 #if defined(CONFIG_USER_ONLY) /* @@ -544,7 +541,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t esz =3D 1 << log2_esz; uint32_t vma =3D vext_vma(desc); =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 /* load bytes from guest memory */ for (i =3D env->vstart; i < env->vl; env->vstart =3D ++i) { @@ -638,7 +635,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, CPURIS= CVState *env, int flags; void *host; =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, env->vl); =20 addr =3D base + ((env->vstart * nf) << log2_esz); page_split =3D -(addr | TARGET_PAGE_MASK); @@ -1116,7 +1113,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ @@ -1150,7 +1147,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t vta =3D vext_vta(desc); = \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { = \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); = \ @@ -1187,7 +1184,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ @@ -1227,7 +1224,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ @@ -1325,7 +1322,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t vma =3D vext_vma(desc); = \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -1374,7 +1371,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -1438,7 +1435,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ @@ -1505,7 +1502,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ @@ -2054,7 +2051,7 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState = *env, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ @@ -2080,7 +2077,7 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVStat= e *env, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ *((ETYPE *)vd + H(i)) =3D (ETYPE)s1; \ @@ -2105,7 +2102,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE *vt =3D (!vext_elem_mask(v0, i) ? vs2 : vs1); \ @@ -2131,7 +2128,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ @@ -2178,7 +2175,7 @@ vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, uint32_t vl, uint32_t vm, int vxrm, opivv2_rm_fn *fn, uint32_t vma, uint32_t esz) { - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, vl); =20 for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { @@ -2305,7 +2302,7 @@ vext_vx_rm_1(void *vd, void *v0, target_long s1, void= *vs2, uint32_t vl, uint32_t vm, int vxrm, opivx2_rm_fn *fn, uint32_t vma, uint32_t esz) { - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, vl); =20 for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { @@ -3104,7 +3101,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -3149,7 +3146,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -3737,7 +3734,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ if (vl =3D=3D 0) { \ return; \ @@ -4260,7 +4257,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ @@ -4302,7 +4299,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ @@ -4497,7 +4494,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ @@ -4827,7 +4824,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t i; \ int a, b; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ a =3D vext_elem_mask(vs1, i); \ @@ -5022,7 +5019,7 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *= env, uint32_t desc) \ uint32_t vma =3D vext_vma(desc); = \ int i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -5059,7 +5056,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t vma =3D vext_vma(desc); = \ target_ulong offset =3D s1, i_min, i; = \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ i_min =3D MAX(env->vstart, offset); = \ for (i =3D i_min; i < vl; i++) { = \ @@ -5094,7 +5091,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t vma =3D vext_vma(desc); = \ target_ulong i_max, i_min, i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ i_min =3D MIN(s1 < vlmax ? vlmax - s1 : 0, vl); = \ i_max =3D MAX(i_min, env->vstart); = \ @@ -5138,7 +5135,7 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, = uint64_t s1, \ uint32_t vma =3D vext_vma(desc); = \ uint32_t i; = \ = \ - VSTART_CHECK_EARLY_EXIT(env); = \ + VSTART_CHECK_EARLY_EXIT(env, vl); = \ = \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { = \ @@ -5189,7 +5186,7 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0= , uint64_t s1, \ uint32_t vma =3D vext_vma(desc); = \ uint32_t i; = \ = \ - VSTART_CHECK_EARLY_EXIT(env); = \ + VSTART_CHECK_EARLY_EXIT(env, vl); = \ = \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { = \ @@ -5266,7 +5263,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint64_t index; \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -5311,7 +5308,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint64_t index =3D s1; = \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -5407,7 +5404,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ - VSTART_CHECK_EARLY_EXIT(env); \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internal= s.c index 05b2d01e58..b490b1d398 100644 --- a/target/riscv/vector_internals.c +++ b/target/riscv/vector_internals.c @@ -66,7 +66,7 @@ void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, uint32_t vma =3D vext_vma(desc); uint32_t i; =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, vl); =20 for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { @@ -92,7 +92,7 @@ void do_vext_vx(void *vd, void *v0, target_long s1, void = *vs2, uint32_t vma =3D vext_vma(desc); uint32_t i; =20 - VSTART_CHECK_EARLY_EXIT(env); + VSTART_CHECK_EARLY_EXIT(env, vl); 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After troubleshooting, it was found that the vext_vx_rm_1 function was call= ed in the vext_vx_rm_2, and then the vext_set_elems_1s function was called to pro= cess the tail element, but only VSTART >=3D vl was checked in the vext_vx_rm_1 function, which caused the tail element to still be processed even if it was returned in advance. So I've made the following change: Put VSTART_CHECK_EARLY_EXIT(env) at the beginning of the vext_vx_rm_2 funct= ion, so that the VSTART register is checked correctly. Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when vstart >=3D vl") Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Message-ID: Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 217d2f60a5..67b3bafebb 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2175,8 +2175,6 @@ vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, uint32_t vl, uint32_t vm, int vxrm, opivv2_rm_fn *fn, uint32_t vma, uint32_t esz) { - VSTART_CHECK_EARLY_EXIT(env, vl); - for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ @@ -2200,6 +2198,8 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, uint32_t vta =3D vext_vta(desc); uint32_t vma =3D vext_vma(desc); =20 + VSTART_CHECK_EARLY_EXIT(env, vl); + switch (env->vxrm) { case 0: /* rnu */ vext_vv_rm_1(vd, v0, vs1, vs2, @@ -2302,8 +2302,6 @@ vext_vx_rm_1(void *vd, void *v0, target_long s1, void= *vs2, uint32_t vl, uint32_t vm, int vxrm, opivx2_rm_fn *fn, uint32_t vma, uint32_t esz) { - VSTART_CHECK_EARLY_EXIT(env, vl); - for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ @@ -2327,6 +2325,8 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void= *vs2, uint32_t vta =3D vext_vta(desc); uint32_t vma =3D vext_vma(desc); =20 + VSTART_CHECK_EARLY_EXIT(env, vl); + switch (env->vxrm) { case 0: /* rnu */ vext_vx_rm_1(vd, v0, s1, vs2, @@ -4662,6 +4662,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t i; \ TD s1 =3D *((TD *)vs1 + HD(0)); \ \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ for (i =3D env->vstart; i < vl; i++) { \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -4750,6 +4752,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t i; \ TD s1 =3D *((TD *)vs1 + HD(0)); \ \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ for (i =3D env->vstart; i < vl; i++) { \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -4914,6 +4918,8 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPU= RISCVState *env, int i; bool first_mask_bit =3D false; =20 + VSTART_CHECK_EARLY_EXIT(env, vl); + for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ @@ -4986,6 +4992,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPUR= ISCVState *env, \ uint32_t sum =3D 0; = \ int i; \ \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ @@ -5344,6 +5352,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vta =3D vext_vta(desc); = \ uint32_t num =3D 0, i; = \ \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vext_elem_mask(vs1, i)) { \ continue; \ --=20 2.48.1 From nobody Thu Apr 3 10:11:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Nor is the size rounded up to a multiple of sizeof(abi_ulong). Cc: qemu-stable@nongnu.org Reported-by: Andreas Schwab Fixes: 9e1c7d982d7 ("linux-user/riscv: Add syscall riscv_hwprobe") Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20250308225902.1208237-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- linux-user/syscall.c | 55 +++++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index b32de763f7..8bfe4912e1 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9119,35 +9119,38 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *= env, } } =20 -static int cpu_set_valid(abi_long arg3, abi_long arg4) +/* + * If the cpumask_t of (target_cpus, cpusetsize) cannot be read: -EFAULT. + * If the cpumast_t has no bits set: -EINVAL. + * Otherwise the cpumask_t contains some bit set: 0. + * Unlike the kernel, we do not mask cpumask_t by the set of online cpus, + * nor bound the search by cpumask_size(). + */ +static int nonempty_cpu_set(abi_ulong cpusetsize, abi_ptr target_cpus) { - int ret, i, tmp; - size_t host_mask_size, target_mask_size; - unsigned long *host_mask; - - /* - * cpu_set_t represent CPU masks as bit masks of type unsigned long *. - * arg3 contains the cpu count. - */ - tmp =3D (8 * sizeof(abi_ulong)); - target_mask_size =3D ((arg3 + tmp - 1) / tmp) * sizeof(abi_ulong); - host_mask_size =3D (target_mask_size + (sizeof(*host_mask) - 1)) & - ~(sizeof(*host_mask) - 1); - - host_mask =3D alloca(host_mask_size); - - ret =3D target_to_host_cpu_mask(host_mask, host_mask_size, - arg4, target_mask_size); - if (ret !=3D 0) { - return ret; - } + unsigned char *p =3D lock_user(VERIFY_READ, target_cpus, cpusetsize, 1= ); + int ret =3D -TARGET_EFAULT; =20 - for (i =3D 0 ; i < host_mask_size / sizeof(*host_mask); i++) { - if (host_mask[i] !=3D 0) { - return 0; + if (p) { + ret =3D -TARGET_EINVAL; + /* + * Since we only care about the empty/non-empty state of the cpuma= sk_t + * not the individual bits, we do not need to repartition the bits + * from target abi_ulong to host unsigned long. + * + * Note that the kernel does not round up cpusetsize to a multiple= of + * sizeof(abi_ulong). After bounding cpusetsize by cpumask_size(), + * it copies exactly cpusetsize bytes into a zeroed buffer. + */ + for (abi_ulong i =3D 0; i < cpusetsize; ++i) { + if (p[i]) { + ret =3D 0; + break; + } } + unlock_user(p, target_cpus, 0); } - return -TARGET_EINVAL; + return ret; } =20 static abi_long do_riscv_hwprobe(CPUArchState *cpu_env, abi_long arg1, @@ -9164,7 +9167,7 @@ static abi_long do_riscv_hwprobe(CPUArchState *cpu_en= v, abi_long arg1, =20 /* check cpu_set */ if (arg3 !=3D 0) { - ret =3D cpu_set_valid(arg3, arg4); + ret =3D nonempty_cpu_set(arg3, arg4); if (ret !=3D 0) { return ret; } --=20 2.48.1 From nobody Thu Apr 3 10:11:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1742371576; cv=none; d=zohomail.com; s=zohoarc; b=S1PNFRMqEXDUC6X778gi8WClYPTzf4PRZf5gHR5y8OLvgDJhpMdQaQdaysoK5z8znqnYymEeJLaVX3kWO9EHznK8K/Ake81IBieCg5ersOKMcWDxFU2WY9LW2QQMnf1RR3VROMUJpaZxYhjlgc+umsh9/le7oHql/1BMADOy0uU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742371576; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IRFeyxnlx7B6/bhH6tCMKsSu+jXikzi9UZmWl9GXpsY=; b=SiX/nkUzhFpEHssjrL0VwkMgSsC6xgmhr5825lmxDmHwPEYnhM8J+rzDxN+8MQU0ZtJEGe6EF/xv2NmvYjavE6780FOgRT3FITX/+bywmuPRSF0/xLhzMhAV28mjtthfauZVC9O/ztLBItLS8laI6peWz2DTpZHx1PHu9gKxyk4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742371575999205.05601204771403; Wed, 19 Mar 2025 01:06:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tuoPj-0000Mt-2I; Wed, 19 Mar 2025 04:04:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tuoP4-00085m-Jr for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:56 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tuoP2-0004Uc-Jz for qemu-devel@nongnu.org; Wed, 19 Mar 2025 04:03:54 -0400 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-300f92661fcso6882062a91.3 for ; Wed, 19 Mar 2025 01:03:52 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-225c6ba6c8dsm107725255ad.156.2025.03.19.01.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Mar 2025 01:03:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742371431; x=1742976231; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IRFeyxnlx7B6/bhH6tCMKsSu+jXikzi9UZmWl9GXpsY=; b=HR/WPBNJfx1oxTLrvnOK8BxBnNt+rSA8JkHYVw3Y/AkxBJ6KJ56yW1dTehdvUaPpS6 iE6NE7fxGEh8jTsJE2NPQzfmvO/mNfIA0ZedDv4RYKIr4jyhbVc2trKE9KUTd5C6ITnV IULT5izP/wNzFZwDPmzCi5RNAF+WYjCziQ24Hg1IKr7Q3EHa3AVM/cxQ5P4/Xbrw+UbX PxJxn9IKqApXRVu4SptTByXcxYRSZJz/vfFUVCuJARjh5qHRDSmeocEFXQiT029CoLhj zKBwktIQgd1+yrBEiER+RI1sC54FBol2pufNBVnNJ9mon9QeURG5DHwlla8ylwwOkMqz riCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742371431; x=1742976231; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IRFeyxnlx7B6/bhH6tCMKsSu+jXikzi9UZmWl9GXpsY=; b=bLlPqZ7IlV0URyP1CYU7aqPkN0UlD6Vtjbn9Hf6Xdsz71sPQ3IejZ9UhPWn7HGSPq4 flc41P8fyz/7jtuLFLBmWjklhK8aTN9KxIU5ME36P65LaaQJCYSbhjoK6apRyx7UXTGF D4Yt6T8MI3Qz0lJT3b+eFStZXOATg3GrpGOu1hs4cZ3DJPV7bY8/BwCofLE/HbTtNedM XK9zl8KIb3PnBrAURYldMVEX6fCZ3U7gopH74gmCMT58UXYmfyarg83EC28DwXCT0+kh aGaU7l4qrMxgcAafNTJP8Mahj6V34mfpmzMRpouW8AOBDLT4/LEZ+s4yDBB8rXZbQqry RqtA== X-Gm-Message-State: AOJu0YxKxoDFtVvCrl5rMMwWQNfqzjKQlixmCFDdK/Z52wd7llnqJeav hoa0zYJdpl/kiJvgX6bZxjnfepByTi3vOyGJDXE5QJC3pbCxPfFnsTcVKg== X-Gm-Gg: ASbGncvl5CWoCCBV3c6kvccDuLYpjJ2vuxQXnXTzazFO9VDELWhgTMzdGxbVAr1Y04/ CzSyOm6WaX2xDr4n58ddF5GBzmd2TZxxgyNVpUVOXzoWN7DL6oDMxxVWof4Xy+tL1i09sbML9C/ mzpOhCBQamLOgcDiPmw+P2tCmhjYVtA9915m34OIJNZpGEuWc+VGFWa/O6enl7juB7RC7gZBzMK O3nBufQpZNCNhdmiwgKlv17z+k8qpMo6EMaO05RElH6CVarqjMkFspL85tnd7QebHCvpa4ZprQ0 URk6uvY9EXBI3vCfKP53i+9bpz4NKJjSz5Lcn6SNgeWwLiPBFiLMrrPRHfWQ1bJw5PV9rdMKhew KcCBR6OL5SOMHiev9vx2Or5mIh+tWCDYTTcBt/bqCFS2seHnQ X-Google-Smtp-Source: AGHT+IHzBLNjgxLLSvuWhv1/uuaTros0JCIJbc2zJOzc5842bJYU8qY2h58gEhbs3pC6xVx9UpCVlQ== X-Received: by 2002:a17:90b:4fc4:b0:301:1c29:a1d9 with SMTP id 98e67ed59e1d1-301be0925b9mr2790860a91.21.1742371430658; Wed, 19 Mar 2025 01:03:50 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yu-Ming Chang , Alistair Francis Subject: [PULL 10/10] target/riscv: Add check for 16-bit aligned PC for different priv versions. Date: Wed, 19 Mar 2025 18:03:08 +1000 Message-ID: <20250319080308.609520-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250319080308.609520-1-alistair.francis@wdc.com> References: <20250319080308.609520-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1742371579157019100 Content-Type: text/plain; charset="utf-8" From: Yu-Ming Chang For privilege version 1.12 or newer, C always implies Zca. We can only check ext_zca to allow 16-bit aligned PC addresses. For older privilege versions, we only check C. Signed-off-by: Yu-Ming Chang Reviewed-by: Alistair Francis Message-ID: <174184718265.10540.10120024221661781046-0@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 12 ++++++++++++ target/riscv/op_helper.c | 8 ++++++-- target/riscv/translate.c | 4 +++- target/riscv/insn_trans/trans_rvi.c.inc | 8 ++++++-- 4 files changed, 27 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7de19b4183..51e49e03de 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -765,6 +765,18 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *en= v) } #endif =20 +static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg, + target_long priv_ver, + uint32_t misa_ext) +{ + /* In priv spec version 1.12 or newer, C always implies Zca */ + if (priv_ver >=3D PRIV_VERSION_1_12_0) { + return cfg->ext_zca; + } else { + return misa_ext & RVC; + } +} + /* * Encode LMUL to lmul as follows: * LMUL vlmul lmul diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 0d4220ba93..72dc48e58d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -279,7 +279,9 @@ target_ulong helper_sret(CPURISCVState *env) } =20 target_ulong retpc =3D env->sepc; - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { + if (!riscv_cpu_allow_16bit_insn(&env_archcpu(env)->cfg, + env->priv_ver, + env->misa_ext) && (retpc & 0x3)) { riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 @@ -357,7 +359,9 @@ static void check_ret_from_m_mode(CPURISCVState *env, t= arget_ulong retpc, riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { + if (!riscv_cpu_allow_16bit_insn(&env_archcpu(env)->cfg, + env->priv_ver, + env->misa_ext) && (retpc & 0x3)) { riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index eaa5d86eae..d6651f244f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -606,7 +606,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_u= long imm) TCGv succ_pc =3D dest_gpr(ctx, rd); =20 /* check misaligned: */ - if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { + if (!riscv_cpu_allow_16bit_insn(ctx->cfg_ptr, + ctx->priv_ver, + ctx->misa_ext)) { if ((imm & 0x3) !=3D 0) { TCGv target_pc =3D tcg_temp_new(); gen_pc_plus_diff(target_pc, ctx, imm); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index b55f56a5eb..b9c7160468 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -151,7 +151,9 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) tcg_gen_ext32s_tl(target_pc, target_pc); } =20 - if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { + if (!riscv_cpu_allow_16bit_insn(ctx->cfg_ptr, + ctx->priv_ver, + ctx->misa_ext)) { TCGv t0 =3D tcg_temp_new(); =20 misaligned =3D gen_new_label(); @@ -300,7 +302,9 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCG= Cond cond) =20 gen_set_label(l); /* branch taken */ =20 - if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca && + if (!riscv_cpu_allow_16bit_insn(ctx->cfg_ptr, + ctx->priv_ver, + ctx->misa_ext) && (a->imm & 0x3)) { /* misaligned */ TCGv target_pc =3D tcg_temp_new(); --=20 2.48.1