Hi; here's a target-arm pullreq to go in before softfreeze.
This is actually pretty much entirely bugfixes (since the
SEL2 timers we implement here are a missing part of a feature
we claim to already implement).
thanks
-- PMM
The following changes since commit 98c7362b1efe651327385a25874a73e008c6549e:
Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging (2025-03-07 07:39:49 +0800)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250307
for you to fetch changes up to 0ce0739d46983e5e88fa9c149cb305689c9d8c6f:
target/rx: Remove TCG_CALL_NO_WG from helpers which write env (2025-03-07 15:03:20 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/arm/smmu-common: Remove the repeated ttb field
* hw/gpio: npcm7xx: fixup out-of-bounds access
* tests/functional/test_arm_sx1: Check whether the serial console is working
* target/arm: Fix minor bugs in generic timer register handling
* target/arm: Implement SEL2 physical and virtual timers
* target/arm: Correct STRD, LDRD atomicity and fault behaviour
* target/arm: Make dummy debug registers RAZ, not NOP
* util/qemu-timer.c: Don't warp timer from timerlist_rearm()
* include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
* hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
* target/rx: Set exception vector base to 0xffffff80
* target/rx: Remove TCG_CALL_NO_WG from helpers which write env
----------------------------------------------------------------
Alex Bennée (4):
target/arm: Implement SEL2 physical and virtual timers
target/arm: Document the architectural names of our GTIMERs
hw/arm: enable secure EL2 timers for virt machine
hw/arm: enable secure EL2 timers for sbsa machine
JianChunfu (2):
hw/arm/smmu-common: Remove the repeated ttb field
hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
Keith Packard (2):
target/rx: Set exception vector base to 0xffffff80
target/rx: Remove TCG_CALL_NO_WG from helpers which write env
Patrick Venture (1):
hw/gpio: npcm7xx: fixup out-of-bounds access
Peter Maydell (11):
target/arm: Apply correct timer offset when calculating deadlines
target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer
target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
target/arm: Refactor handling of timer offset for direct register accesses
target/arm: Correct LDRD atomicity and fault behaviour
target/arm: Correct STRD atomicity
target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()
target/arm: Make dummy debug registers RAZ, not NOP
util/qemu-timer.c: Don't warp timer from timerlist_rearm()
include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
Thomas Huth (1):
tests/functional/test_arm_sx1: Check whether the serial console is working
MAINTAINERS | 1 +
hw/arm/smmu-internal.h | 5 -
include/exec/memop.h | 8 +-
include/hw/arm/bsa.h | 2 +
include/hw/arm/smmu-common.h | 7 +-
target/arm/cpu.h | 2 +
target/arm/gtimer.h | 14 +-
target/arm/internals.h | 5 +-
target/rx/helper.h | 34 ++--
hw/arm/sbsa-ref.c | 2 +
hw/arm/smmu-common.c | 21 +++
hw/arm/smmuv3.c | 19 +--
hw/arm/virt.c | 2 +
hw/gpio/npcm7xx_gpio.c | 3 +-
target/arm/cpu.c | 4 +
target/arm/debug_helper.c | 7 +-
target/arm/helper.c | 324 ++++++++++++++++++++++++++++++++-------
target/arm/tcg/op_helper.c | 8 +-
target/arm/tcg/translate.c | 147 +++++++++++-------
target/rx/helper.c | 2 +-
util/qemu-timer.c | 4 -
hw/arm/trace-events | 3 +-
tests/functional/test_arm_sx1.py | 7 +-
23 files changed, 455 insertions(+), 176 deletions(-)