Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 82 ++++++++++++++++++++++++++---------------
1 file changed, 52 insertions(+), 30 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 09aad69e3c..eab9674b6c 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -120,21 +120,27 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {
};
/* GICINT 128 */
-static const int aspeed_soc_ast2700_gic128_intcmap[] = {
+/* GICINT 192 */
+static const int ast2700_gic128_gic192_intcmap[] = {
[ASPEED_DEV_LPC] = 0,
[ASPEED_DEV_IBT] = 2,
[ASPEED_DEV_KCS] = 4,
};
+/* GICINT 129 */
+/* GICINT 193 */
+
/* GICINT 130 */
-static const int aspeed_soc_ast2700_gic130_intcmap[] = {
+/* GICINT 194 */
+static const int ast2700_gic130_gic194_intcmap[] = {
[ASPEED_DEV_I2C] = 0,
[ASPEED_DEV_ADC] = 16,
[ASPEED_DEV_GPIO] = 18,
};
/* GICINT 131 */
-static const int aspeed_soc_ast2700_gic131_intcmap[] = {
+/* GICINT 195 */
+static const int ast2700_gic131_gic195_intcmap[] = {
[ASPEED_DEV_I3C] = 0,
[ASPEED_DEV_WDT] = 16,
[ASPEED_DEV_FMC] = 25,
@@ -142,7 +148,8 @@ static const int aspeed_soc_ast2700_gic131_intcmap[] = {
};
/* GICINT 132 */
-static const int aspeed_soc_ast2700_gic132_intcmap[] = {
+/* GICINT 196 */
+static const int ast2700_gic132_gic196_intcmap[] = {
[ASPEED_DEV_ETH1] = 0,
[ASPEED_DEV_ETH2] = 1,
[ASPEED_DEV_ETH3] = 2,
@@ -161,24 +168,26 @@ static const int aspeed_soc_ast2700_gic132_intcmap[] = {
};
/* GICINT 133 */
-static const int aspeed_soc_ast2700_gic133_intcmap[] = {
+/* GICINT 197 */
+static const int ast2700_gic133_gic197_intcmap[] = {
[ASPEED_DEV_SDHCI] = 1,
[ASPEED_DEV_PECI] = 4,
};
/* GICINT 128 ~ 136 */
+/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
int irq;
const int *ptr;
};
-static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = {
- {128, aspeed_soc_ast2700_gic128_intcmap},
+static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
+ {128, ast2700_gic128_gic192_intcmap},
{129, NULL},
- {130, aspeed_soc_ast2700_gic130_intcmap},
- {131, aspeed_soc_ast2700_gic131_intcmap},
- {132, aspeed_soc_ast2700_gic132_intcmap},
- {133, aspeed_soc_ast2700_gic133_intcmap},
+ {130, ast2700_gic130_gic194_intcmap},
+ {131, ast2700_gic131_gic195_intcmap},
+ {132, ast2700_gic132_gic196_intcmap},
+ {133, ast2700_gic133_gic197_intcmap},
{134, NULL},
{135, NULL},
{136, NULL},
@@ -190,11 +199,11 @@ static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int i;
- for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
+ for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]);
+ ast2700_gic_intcmap[i].ptr[dev]);
}
}
@@ -208,16 +217,17 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int i;
- for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
+ for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
+ ast2700_gic_intcmap[i].ptr[dev] + index);
}
}
/*
- * Invalid orgate index, device irq should be 128 to 136.
+ * Invalid OR gate index, device IRQ should be between 128 to 136
+ * and 192 to 201.
*/
g_assert_not_reached();
}
@@ -492,7 +502,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc);
g_autofree char *sram_name = NULL;
qemu_irq irq;
@@ -530,17 +539,18 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
sc->memmap[ASPEED_DEV_INTC]);
- /* source orgates -> INTC */
- for (i = 0; i < ic->num_inpins; i++) {
+ /* irq sources -> orgates -> INTC */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
- qdev_get_gpio_in(DEVICE(&a->intc), i));
+ qdev_get_gpio_in(DEVICE(&a->intc), i));
}
+ /* INTC -> GIC192 - GIC201 */
/* INTC -> GIC128 - GIC136 */
- for (i = 0; i < ic->num_outpins; i++) {
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_outpins; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
qdev_get_gpio_in(DEVICE(&a->gic),
- aspeed_soc_ast2700_gic_intcmap[i].irq));
+ ast2700_gic_intcmap[i].irq));
}
/* SRAM */
@@ -691,10 +701,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
/*
* The AST2700 I2C controller has one source INTC per bus.
- * I2C buses interrupt are connected to GICINT130_INTC
- * from bit 0 to bit 15.
- * I2C bus 0 is connected to GICINT130_INTC at bit 0.
- * I2C bus 15 is connected to GICINT130_INTC at bit 15.
+ *
+ * For AST2700 A0:
+ * I2C bus interrupts are connected to the OR gate from bit 0 to bit
+ * 15, and the OR gate output pin is connected to the input pin of
+ * GICINT130 of INTC (CPU Die). Then, the output pin is connected to
+ * the GIC.
+ *
+ * For AST2700 A1:
+ * I2C bus interrupts are connected to the OR gate from bit 0 to bit
+ * 15, and the OR gate output pin is connected to the input pin of
+ * GICINT194 of INTCIO (IO Die). Then, the output pin is connected
+ * to the INTC (CPU Die) input pin, and its output pin is connected
+ * to the GIC.
+ *
+ * I2C bus 0 is connected to the OR gate at bit 0.
+ * I2C bus 15 is connected to the OR gate at bit 15.
*/
irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
--
2.34.1On 3/3/25 10:54, Jamin Lin wrote:
> Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
> These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
> Updates the interrupt mapping to include support for AST2700 A1 by extending
> the existing mappings to the new GIC range.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/arm/aspeed_ast27x0.c | 82 ++++++++++++++++++++++++++---------------
> 1 file changed, 52 insertions(+), 30 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 09aad69e3c..eab9674b6c 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -120,21 +120,27 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {
> };
>
> /* GICINT 128 */
> -static const int aspeed_soc_ast2700_gic128_intcmap[] = {
> +/* GICINT 192 */
> +static const int ast2700_gic128_gic192_intcmap[] = {
> [ASPEED_DEV_LPC] = 0,
> [ASPEED_DEV_IBT] = 2,
> [ASPEED_DEV_KCS] = 4,
> };
>
> +/* GICINT 129 */
> +/* GICINT 193 */
> +
> /* GICINT 130 */
> -static const int aspeed_soc_ast2700_gic130_intcmap[] = {
> +/* GICINT 194 */
> +static const int ast2700_gic130_gic194_intcmap[] = {
> [ASPEED_DEV_I2C] = 0,
> [ASPEED_DEV_ADC] = 16,
> [ASPEED_DEV_GPIO] = 18,
> };
>
> /* GICINT 131 */
> -static const int aspeed_soc_ast2700_gic131_intcmap[] = {
> +/* GICINT 195 */
> +static const int ast2700_gic131_gic195_intcmap[] = {
> [ASPEED_DEV_I3C] = 0,
> [ASPEED_DEV_WDT] = 16,
> [ASPEED_DEV_FMC] = 25,
> @@ -142,7 +148,8 @@ static const int aspeed_soc_ast2700_gic131_intcmap[] = {
> };
>
> /* GICINT 132 */
> -static const int aspeed_soc_ast2700_gic132_intcmap[] = {
> +/* GICINT 196 */
> +static const int ast2700_gic132_gic196_intcmap[] = {
> [ASPEED_DEV_ETH1] = 0,
> [ASPEED_DEV_ETH2] = 1,
> [ASPEED_DEV_ETH3] = 2,
> @@ -161,24 +168,26 @@ static const int aspeed_soc_ast2700_gic132_intcmap[] = {
> };
>
> /* GICINT 133 */
> -static const int aspeed_soc_ast2700_gic133_intcmap[] = {
> +/* GICINT 197 */
> +static const int ast2700_gic133_gic197_intcmap[] = {
> [ASPEED_DEV_SDHCI] = 1,
> [ASPEED_DEV_PECI] = 4,
> };
>
> /* GICINT 128 ~ 136 */
> +/* GICINT 192 ~ 201 */
> struct gic_intc_irq_info {
> int irq;
> const int *ptr;
> };
>
> -static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = {
> - {128, aspeed_soc_ast2700_gic128_intcmap},
> +static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
> + {128, ast2700_gic128_gic192_intcmap},
> {129, NULL},
> - {130, aspeed_soc_ast2700_gic130_intcmap},
> - {131, aspeed_soc_ast2700_gic131_intcmap},
> - {132, aspeed_soc_ast2700_gic132_intcmap},
> - {133, aspeed_soc_ast2700_gic133_intcmap},
> + {130, ast2700_gic130_gic194_intcmap},
> + {131, ast2700_gic131_gic195_intcmap},
> + {132, ast2700_gic132_gic196_intcmap},
> + {133, ast2700_gic133_gic197_intcmap},
> {134, NULL},
> {135, NULL},
> {136, NULL},
> @@ -190,11 +199,11 @@ static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> int i;
>
> - for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
> - if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
> - assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
> + for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
> + if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
> + assert(ast2700_gic_intcmap[i].ptr);
> return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
> - aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]);
> + ast2700_gic_intcmap[i].ptr[dev]);
> }
> }
>
> @@ -208,16 +217,17 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> int i;
>
> - for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
> - if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
> - assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
> + for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
> + if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
> + assert(ast2700_gic_intcmap[i].ptr);
> return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
> - aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
> + ast2700_gic_intcmap[i].ptr[dev] + index);
> }
> }
>
> /*
> - * Invalid orgate index, device irq should be 128 to 136.
> + * Invalid OR gate index, device IRQ should be between 128 to 136
> + * and 192 to 201.
> */
> g_assert_not_reached();
> }
> @@ -492,7 +502,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> AspeedSoCState *s = ASPEED_SOC(dev);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> - AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc);
I would keep this intermediate variable. Minor.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> g_autofree char *sram_name = NULL;
> qemu_irq irq;
>
> @@ -530,17 +539,18 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
> sc->memmap[ASPEED_DEV_INTC]);
>
> - /* source orgates -> INTC */
> - for (i = 0; i < ic->num_inpins; i++) {
> + /* irq sources -> orgates -> INTC */
> + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_inpins; i++) {
> qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
> - qdev_get_gpio_in(DEVICE(&a->intc), i));
> + qdev_get_gpio_in(DEVICE(&a->intc), i));
> }
>
> + /* INTC -> GIC192 - GIC201 */
> /* INTC -> GIC128 - GIC136 */
> - for (i = 0; i < ic->num_outpins; i++) {
> + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_outpins; i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
> qdev_get_gpio_in(DEVICE(&a->gic),
> - aspeed_soc_ast2700_gic_intcmap[i].irq));
> + ast2700_gic_intcmap[i].irq));
> }
>
> /* SRAM */
> @@ -691,10 +701,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
> /*
> * The AST2700 I2C controller has one source INTC per bus.
> - * I2C buses interrupt are connected to GICINT130_INTC
> - * from bit 0 to bit 15.
> - * I2C bus 0 is connected to GICINT130_INTC at bit 0.
> - * I2C bus 15 is connected to GICINT130_INTC at bit 15.
> + *
> + * For AST2700 A0:
> + * I2C bus interrupts are connected to the OR gate from bit 0 to bit
> + * 15, and the OR gate output pin is connected to the input pin of
> + * GICINT130 of INTC (CPU Die). Then, the output pin is connected to
> + * the GIC.
> + *
> + * For AST2700 A1:
> + * I2C bus interrupts are connected to the OR gate from bit 0 to bit
> + * 15, and the OR gate output pin is connected to the input pin of
> + * GICINT194 of INTCIO (IO Die). Then, the output pin is connected
> + * to the INTC (CPU Die) input pin, and its output pin is connected
> + * to the GIC.
> + *
> + * I2C bus 0 is connected to the OR gate at bit 0.
> + * I2C bus 15 is connected to the OR gate at bit 15.
> */
> irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
Hi Cedric,
> Subject: Re: [PATCH v4 17/23] hw/arm/aspeed_ast27x0.c Support AST2700 A1
> GIC Interrupt Mapping
>
> On 3/3/25 10:54, Jamin Lin wrote:
> > Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
> > These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
> > Updates the interrupt mapping to include support for AST2700 A1 by
> > extending the existing mappings to the new GIC range.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > hw/arm/aspeed_ast27x0.c | 82
> ++++++++++++++++++++++++++---------------
> > 1 file changed, 52 insertions(+), 30 deletions(-)
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > 09aad69e3c..eab9674b6c 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -120,21 +120,27 @@ static const int aspeed_soc_ast2700a0_irqmap[] =
> {
> > };
> >
> > /* GICINT 128 */
> > -static const int aspeed_soc_ast2700_gic128_intcmap[] = {
> > +/* GICINT 192 */
> > +static const int ast2700_gic128_gic192_intcmap[] = {
> > [ASPEED_DEV_LPC] = 0,
> > [ASPEED_DEV_IBT] = 2,
> > [ASPEED_DEV_KCS] = 4,
> > };
> >
> > +/* GICINT 129 */
> > +/* GICINT 193 */
> > +
> > /* GICINT 130 */
> > -static const int aspeed_soc_ast2700_gic130_intcmap[] = {
> > +/* GICINT 194 */
> > +static const int ast2700_gic130_gic194_intcmap[] = {
> > [ASPEED_DEV_I2C] = 0,
> > [ASPEED_DEV_ADC] = 16,
> > [ASPEED_DEV_GPIO] = 18,
> > };
> >
> > /* GICINT 131 */
> > -static const int aspeed_soc_ast2700_gic131_intcmap[] = {
> > +/* GICINT 195 */
> > +static const int ast2700_gic131_gic195_intcmap[] = {
> > [ASPEED_DEV_I3C] = 0,
> > [ASPEED_DEV_WDT] = 16,
> > [ASPEED_DEV_FMC] = 25,
> > @@ -142,7 +148,8 @@ static const int
> aspeed_soc_ast2700_gic131_intcmap[] = {
> > };
> >
> > /* GICINT 132 */
> > -static const int aspeed_soc_ast2700_gic132_intcmap[] = {
> > +/* GICINT 196 */
> > +static const int ast2700_gic132_gic196_intcmap[] = {
> > [ASPEED_DEV_ETH1] = 0,
> > [ASPEED_DEV_ETH2] = 1,
> > [ASPEED_DEV_ETH3] = 2,
> > @@ -161,24 +168,26 @@ static const int
> aspeed_soc_ast2700_gic132_intcmap[] = {
> > };
> >
> > /* GICINT 133 */
> > -static const int aspeed_soc_ast2700_gic133_intcmap[] = {
> > +/* GICINT 197 */
> > +static const int ast2700_gic133_gic197_intcmap[] = {
> > [ASPEED_DEV_SDHCI] = 1,
> > [ASPEED_DEV_PECI] = 4,
> > };
> >
> > /* GICINT 128 ~ 136 */
> > +/* GICINT 192 ~ 201 */
> > struct gic_intc_irq_info {
> > int irq;
> > const int *ptr;
> > };
> >
> > -static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = {
> > - {128, aspeed_soc_ast2700_gic128_intcmap},
> > +static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
> > + {128, ast2700_gic128_gic192_intcmap},
> > {129, NULL},
> > - {130, aspeed_soc_ast2700_gic130_intcmap},
> > - {131, aspeed_soc_ast2700_gic131_intcmap},
> > - {132, aspeed_soc_ast2700_gic132_intcmap},
> > - {133, aspeed_soc_ast2700_gic133_intcmap},
> > + {130, ast2700_gic130_gic194_intcmap},
> > + {131, ast2700_gic131_gic195_intcmap},
> > + {132, ast2700_gic132_gic196_intcmap},
> > + {133, ast2700_gic133_gic197_intcmap},
> > {134, NULL},
> > {135, NULL},
> > {136, NULL},
> > @@ -190,11 +199,11 @@ static qemu_irq
> aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
> > AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > int i;
> >
> > - for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
> > - if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
> > - assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
> > + for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
> > + if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
> > + assert(ast2700_gic_intcmap[i].ptr);
> > return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
> > - aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]);
> > + ast2700_gic_intcmap[i].ptr[dev]);
> > }
> > }
> >
> > @@ -208,16 +217,17 @@ static qemu_irq
> aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
> > AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > int i;
> >
> > - for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
> > - if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
> > - assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
> > + for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
> > + if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
> > + assert(ast2700_gic_intcmap[i].ptr);
> > return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
> > - aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
> > + ast2700_gic_intcmap[i].ptr[dev]
> +
> > + index);
> > }
> > }
> >
> > /*
> > - * Invalid orgate index, device irq should be 128 to 136.
> > + * Invalid OR gate index, device IRQ should be between 128 to 136
> > + * and 192 to 201.
> > */
> > g_assert_not_reached();
> > }
> > @@ -492,7 +502,6 @@ static void aspeed_soc_ast2700_realize(DeviceState
> *dev, Error **errp)
> > Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> > AspeedSoCState *s = ASPEED_SOC(dev);
> > AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > - AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc);
>
> I would keep this intermediate variable. Minor.
>
Thanks for suggestion and review.
Will keep this variable.
Jamin
>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
>
> Thanks,
>
> C.
>
>
>
> > g_autofree char *sram_name = NULL;
> > qemu_irq irq;
> >
> > @@ -530,17 +539,18 @@ static void
> aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> > aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
> > sc->memmap[ASPEED_DEV_INTC]);
> >
> > - /* source orgates -> INTC */
> > - for (i = 0; i < ic->num_inpins; i++) {
> > + /* irq sources -> orgates -> INTC */
> > + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_inpins; i++)
> > + {
> > qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
> > - qdev_get_gpio_in(DEVICE(&a->intc),
> i));
> > + qdev_get_gpio_in(DEVICE(&a->intc),
> i));
> > }
> >
> > + /* INTC -> GIC192 - GIC201 */
> > /* INTC -> GIC128 - GIC136 */
> > - for (i = 0; i < ic->num_outpins; i++) {
> > + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_outpins;
> > + i++) {
> > sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
> > qdev_get_gpio_in(DEVICE(&a->gic),
> > -
> aspeed_soc_ast2700_gic_intcmap[i].irq));
> > +
> > + ast2700_gic_intcmap[i].irq));
> > }
> >
> > /* SRAM */
> > @@ -691,10 +701,22 @@ static void
> aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> > for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
> > /*
> > * The AST2700 I2C controller has one source INTC per bus.
> > - * I2C buses interrupt are connected to GICINT130_INTC
> > - * from bit 0 to bit 15.
> > - * I2C bus 0 is connected to GICINT130_INTC at bit 0.
> > - * I2C bus 15 is connected to GICINT130_INTC at bit 15.
> > + *
> > + * For AST2700 A0:
> > + * I2C bus interrupts are connected to the OR gate from bit 0 to
> bit
> > + * 15, and the OR gate output pin is connected to the input pin of
> > + * GICINT130 of INTC (CPU Die). Then, the output pin is
> connected to
> > + * the GIC.
> > + *
> > + * For AST2700 A1:
> > + * I2C bus interrupts are connected to the OR gate from bit 0 to
> bit
> > + * 15, and the OR gate output pin is connected to the input pin of
> > + * GICINT194 of INTCIO (IO Die). Then, the output pin is
> connected
> > + * to the INTC (CPU Die) input pin, and its output pin is connected
> > + * to the GIC.
> > + *
> > + * I2C bus 0 is connected to the OR gate at bit 0.
> > + * I2C bus 15 is connected to the OR gate at bit 15.
> > */
> > irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i);
> > sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0,
> > irq);
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