From nobody Wed Mar 5 18:32:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1740995875; cv=none; d=zohomail.com; s=zohoarc; b=DZgEgpeZV670jVsYSYrVeMahFxDXG7EpWo6LvTxIJOHtxt/1OZv+LbeV5oF9T2ZlLHIzywhZnpRUH/PHTH1HoVOMNfoi7YEq4yLhnSI0jY0BwgxHp1UOTCr1PRbylnBXfse+mbdLQfZuOXx+HbD9TUfE4kKlPx7FMaWtlRriunU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740995875; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=7OxLiSQfXvQ4Qlr9qMyEmQAZs/r7UIiyvWo87HnAmF0=; b=R/7VDyAUV1dP1z430FJipH+w7ivMZ9TaMbLS2BT+oynNp8amdHa5Rgk2OVX+FWWBba/u1jKc1stYtw/VGaMWgC5MSk/9WqzjoHlSevcEJQjf6BX0J2zq/1wAYqCmBmyecVZCjCf2uqwnzrLG0kpZVasV5/Z5i4U0cBsJJ9Jn384= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740995875455316.55920253722616; Mon, 3 Mar 2025 01:57:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tp2XX-000176-Ft; Mon, 03 Mar 2025 04:56:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2Wt-00088W-FY; Mon, 03 Mar 2025 04:56:07 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2Wr-0001vN-DU; Mon, 03 Mar 2025 04:56:07 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 3 Mar 2025 17:55:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 3 Mar 2025 17:55:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , Subject: [PATCH v4 17/23] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping Date: Mon, 3 Mar 2025 17:54:45 +0800 Message-ID: <20250303095457.2337631-18-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> References: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1740995876260019000 Content-Type: text/plain; charset="utf-8" Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0. These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197. Updates the interrupt mapping to include support for AST2700 A1 by extending the existing mappings to the new GIC range. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 82 ++++++++++++++++++++++++++--------------- 1 file changed, 52 insertions(+), 30 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 09aad69e3c..eab9674b6c 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -120,21 +120,27 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D { }; =20 /* GICINT 128 */ -static const int aspeed_soc_ast2700_gic128_intcmap[] =3D { +/* GICINT 192 */ +static const int ast2700_gic128_gic192_intcmap[] =3D { [ASPEED_DEV_LPC] =3D 0, [ASPEED_DEV_IBT] =3D 2, [ASPEED_DEV_KCS] =3D 4, }; =20 +/* GICINT 129 */ +/* GICINT 193 */ + /* GICINT 130 */ -static const int aspeed_soc_ast2700_gic130_intcmap[] =3D { +/* GICINT 194 */ +static const int ast2700_gic130_gic194_intcmap[] =3D { [ASPEED_DEV_I2C] =3D 0, [ASPEED_DEV_ADC] =3D 16, [ASPEED_DEV_GPIO] =3D 18, }; =20 /* GICINT 131 */ -static const int aspeed_soc_ast2700_gic131_intcmap[] =3D { +/* GICINT 195 */ +static const int ast2700_gic131_gic195_intcmap[] =3D { [ASPEED_DEV_I3C] =3D 0, [ASPEED_DEV_WDT] =3D 16, [ASPEED_DEV_FMC] =3D 25, @@ -142,7 +148,8 @@ static const int aspeed_soc_ast2700_gic131_intcmap[] = =3D { }; =20 /* GICINT 132 */ -static const int aspeed_soc_ast2700_gic132_intcmap[] =3D { +/* GICINT 196 */ +static const int ast2700_gic132_gic196_intcmap[] =3D { [ASPEED_DEV_ETH1] =3D 0, [ASPEED_DEV_ETH2] =3D 1, [ASPEED_DEV_ETH3] =3D 2, @@ -161,24 +168,26 @@ static const int aspeed_soc_ast2700_gic132_intcmap[] = =3D { }; =20 /* GICINT 133 */ -static const int aspeed_soc_ast2700_gic133_intcmap[] =3D { +/* GICINT 197 */ +static const int ast2700_gic133_gic197_intcmap[] =3D { [ASPEED_DEV_SDHCI] =3D 1, [ASPEED_DEV_PECI] =3D 4, }; =20 /* GICINT 128 ~ 136 */ +/* GICINT 192 ~ 201 */ struct gic_intc_irq_info { int irq; const int *ptr; }; =20 -static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] =3D= { - {128, aspeed_soc_ast2700_gic128_intcmap}, +static const struct gic_intc_irq_info ast2700_gic_intcmap[] =3D { + {128, ast2700_gic128_gic192_intcmap}, {129, NULL}, - {130, aspeed_soc_ast2700_gic130_intcmap}, - {131, aspeed_soc_ast2700_gic131_intcmap}, - {132, aspeed_soc_ast2700_gic132_intcmap}, - {133, aspeed_soc_ast2700_gic133_intcmap}, + {130, ast2700_gic130_gic194_intcmap}, + {131, ast2700_gic131_gic195_intcmap}, + {132, ast2700_gic132_gic196_intcmap}, + {133, ast2700_gic133_gic197_intcmap}, {134, NULL}, {135, NULL}, {136, NULL}, @@ -190,11 +199,11 @@ static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCS= tate *s, int dev) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); int i; =20 - for (i =3D 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { - if (sc->irqmap[dev] =3D=3D aspeed_soc_ast2700_gic_intcmap[i].irq) { - assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); + for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { + if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) { + assert(ast2700_gic_intcmap[i].ptr); return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), - aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]); + ast2700_gic_intcmap[i].ptr[dev]); } } =20 @@ -208,16 +217,17 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(Aspe= edSoCState *s, int dev, AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); int i; =20 - for (i =3D 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { - if (sc->irqmap[dev] =3D=3D aspeed_soc_ast2700_gic_intcmap[i].irq) { - assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); + for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { + if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) { + assert(ast2700_gic_intcmap[i].ptr); return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), - aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index); + ast2700_gic_intcmap[i].ptr[dev] + inde= x); } } =20 /* - * Invalid orgate index, device irq should be 128 to 136. + * Invalid OR gate index, device IRQ should be between 128 to 136 + * and 192 to 201. */ g_assert_not_reached(); } @@ -492,7 +502,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(dev); AspeedSoCState *s =3D ASPEED_SOC(dev); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - AspeedINTCClass *ic =3D ASPEED_INTC_GET_CLASS(&a->intc); g_autofree char *sram_name =3D NULL; qemu_irq irq; =20 @@ -530,17 +539,18 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, sc->memmap[ASPEED_DEV_INTC]); =20 - /* source orgates -> INTC */ - for (i =3D 0; i < ic->num_inpins; i++) { + /* irq sources -> orgates -> INTC */ + for (i =3D 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, - qdev_get_gpio_in(DEVICE(&a->intc), i)); + qdev_get_gpio_in(DEVICE(&a->intc), i)); } =20 + /* INTC -> GIC192 - GIC201 */ /* INTC -> GIC128 - GIC136 */ - for (i =3D 0; i < ic->num_outpins; i++) { + for (i =3D 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_outpins; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, qdev_get_gpio_in(DEVICE(&a->gic), - aspeed_soc_ast2700_gic_intcmap[i].irq)); + ast2700_gic_intcmap[i].irq)); } =20 /* SRAM */ @@ -691,10 +701,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) for (i =3D 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { /* * The AST2700 I2C controller has one source INTC per bus. - * I2C buses interrupt are connected to GICINT130_INTC - * from bit 0 to bit 15. - * I2C bus 0 is connected to GICINT130_INTC at bit 0. - * I2C bus 15 is connected to GICINT130_INTC at bit 15. + * + * For AST2700 A0: + * I2C bus interrupts are connected to the OR gate from bit 0 to b= it + * 15, and the OR gate output pin is connected to the input pin of + * GICINT130 of INTC (CPU Die). Then, the output pin is connected = to + * the GIC. + * + * For AST2700 A1: + * I2C bus interrupts are connected to the OR gate from bit 0 to b= it + * 15, and the OR gate output pin is connected to the input pin of + * GICINT194 of INTCIO (IO Die). Then, the output pin is connected + * to the INTC (CPU Die) input pin, and its output pin is connected + * to the GIC. + * + * I2C bus 0 is connected to the OR gate at bit 0. + * I2C bus 15 is connected to the OR gate at bit 15. */ irq =3D aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); --=20 2.34.1