According to:
RISC-V Cryptography Extensions Volume I. Version 1.0.1, 4.1. The seed CSR

On 64 bit machine 32 bit register must be extended with zeroes in higher bits
Previously status mask was formed by integer left bitshift with sign changing,
so higher 32 bits was 1.
Change type from int to ULL fix ZKR seed.

Signed-off-by: Saveliy Motov <saveliy.motov@syntacore.com>
---
 target/riscv/cpu_bits.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index f97c48a394..140b45bda7 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -878,11 +878,11 @@ typedef enum RISCVException {
     (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
 
 /* seed CSR bits */
-#define SEED_OPST                        (0b11 << 30)
-#define SEED_OPST_BIST                   (0b00 << 30)
-#define SEED_OPST_WAIT                   (0b01 << 30)
-#define SEED_OPST_ES16                   (0b10 << 30)
-#define SEED_OPST_DEAD                   (0b11 << 30)
+#define SEED_OPST                          (0b11UL << 30)
+#define SEED_OPST_BIST                     (0b00UL << 30)
+#define SEED_OPST_WAIT                     (0b01UL << 30)
+#define SEED_OPST_ES16                     (0b10UL << 30)
+#define SEED_OPST_DEAD                     (0b11UL << 30)
 /* PMU related bits */
 #define MIE_LCOFIE                         (1 << IRQ_PMU_OVF)
 
-- 
2.34.1