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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.249.69.228; envelope-from=saveliy.motov@syntacore.com; helo=m.syntacore.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 27 Feb 2025 10:23:37 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) X-ZM-MESSAGEID: 1740669875082019000 Content-Type: text/plain; charset="utf-8" According to: RISC-V Cryptography Extensions Volume I. Version 1.0.1, 4.1. The seed CSR On 64 bit machine 32 bit register must be extended with zeroes in higher bi= ts Previously status mask was formed by integer left bitshift with sign changi= ng, so higher 32 bits was 1. Change type from int to ULL fix ZKR seed. Signed-off-by: Saveliy Motov --- target/riscv/cpu_bits.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f97c48a394..140b45bda7 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -878,11 +878,11 @@ typedef enum RISCVException { (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) =20 /* seed CSR bits */ -#define SEED_OPST (0b11 << 30) -#define SEED_OPST_BIST (0b00 << 30) -#define SEED_OPST_WAIT (0b01 << 30) -#define SEED_OPST_ES16 (0b10 << 30) -#define SEED_OPST_DEAD (0b11 << 30) +#define SEED_OPST (0b11UL << 30) +#define SEED_OPST_BIST (0b00UL << 30) +#define SEED_OPST_WAIT (0b01UL << 30) +#define SEED_OPST_ES16 (0b10UL << 30) +#define SEED_OPST_DEAD (0b11UL << 30) /* PMU related bits */ #define MIE_LCOFIE (1 << IRQ_PMU_OVF) =20 --=20 2.34.1