[PULL 0/9] target-arm queue
[PULL v2 00/32] target-arm queue
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This one's almost all docs fixes.
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For some reason the xilinx can bus patches built in my local config
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but not in the merge-test ones; dropped those.
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3
thanks
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-- PMM
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-- PMM
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The following changes since commit ba54a7e6b86884e43bed2d2f5a79c719059652a8:
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The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:
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Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-11-26 14:06:40 +0000)
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Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241126
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914-1
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for you to fetch changes up to d8790ead55a2ef1e65332ebec63ae3c5db598942:
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for you to fetch changes up to 4fe986dd4480308ecf07200cfbd3c3d494a0f639:
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docs/system/arm/aspeed: add missing model supermicrox11spi-bmc (2024-11-26 16:22:38 +0000)
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tests/acceptance: console boot tests for quanta-gsj (2020-09-14 14:24:59 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
19
target-arm queue:
19
* hw/misc/a9scu: Do not allow invalid CPU count
20
* target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
20
* hw/misc/a9scu: Minor cleanups
21
* docs/system/arm: Fix broken links and missing feature names
21
* hw/timer/armv7m_systick: assert that board code set system_clock_scale
22
* decodetree: Improve identifier matching
23
* target/arm: Clean up neon fp insn size field decode
24
* target/arm: Remove KVM support for 32-bit Arm hosts
25
* hw/arm/mps2: New board models mps2-an386, mps2-an500
26
* Deprecate Unicore32 port
27
* Deprecate lm32 port
28
* target/arm: Count PMU events when MDCR.SPME is set
29
* hw/arm: versal-virt: Correct the tx/rx GEM clocks
30
* New Nuvoton iBMC board models npcm750-evb, quanta-gsj
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----------------------------------------------------------------
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----------------------------------------------------------------
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Michael Tokarev (1):
33
Aaron Lindsay (1):
25
target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
34
target/arm: Count PMU events when MDCR.SPME is set
26
35
27
Pierrick Bouvier (8):
36
Edgar E. Iglesias (1):
28
docs/system/arm/emulation: mention armv9
37
hw/arm: versal-virt: Correct the tx/rx GEM clocks
29
docs/system/arm/emulation: fix typo in feature name
30
docs/system/arm/emulation: add FEAT_SSBS2
31
target/arm/tcg/: fix typo in FEAT name
32
docs/system/arm/: add FEAT_MTE_ASYNC
33
docs/system/arm/: add FEAT_DoubleLock
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docs/system/arm/fby35: update link to product page
35
docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
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docs/system/arm/aspeed.rst | 7 ++++---
39
Havard Skinnemoen (14):
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docs/system/arm/emulation.rst | 11 +++++++----
40
hw/misc: Add NPCM7xx System Global Control Registers device model
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docs/system/arm/fby35.rst | 2 +-
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hw/misc: Add NPCM7xx Clock Controller device model
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target/arm/tcg/cpu32.c | 6 +++---
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hw/timer: Add NPCM7xx Timer device model
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4 files changed, 15 insertions(+), 11 deletions(-)
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hw/arm: Add NPCM730 and NPCM750 SoC models
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hw/arm: Add two NPCM7xx-based machines
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roms: Add virtual Boot ROM for NPCM7xx SoCs
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hw/arm: Load -bios image as a boot ROM for npcm7xx
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hw/nvram: NPCM7xx OTP device model
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hw/mem: Stubbed out NPCM7xx Memory Controller model
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hw/ssi: NPCM7xx Flash Interface Unit device model
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hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
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hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
52
docs/system: Add Nuvoton machine documentation
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tests/acceptance: console boot tests for quanta-gsj
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Peter Maydell (11):
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hw/timer/armv7m_systick: assert that board code set system_clock_scale
57
target/arm: Convert Neon 3-same-fp size field to MO_* in decode
58
target/arm: Convert Neon VCVT fp size field to MO_* in decode
59
target/arm: Convert VCMLA, VCADD size field to MO_* in decode
60
target/arm: Remove KVM support for 32-bit Arm hosts
61
target/arm: Remove no-longer-reachable 32-bit KVM code
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hw/arm/mps2: New board model mps2-an386
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hw/arm/mps2: New board model mps2-an500
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docs/system/arm/mps2.rst: Make board list consistent
65
Deprecate Unicore32 port
66
Deprecate lm32 port
67
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Philippe Mathieu-Daudé (4):
69
hw/misc/a9scu: Do not allow invalid CPU count
70
hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
71
hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
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hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
73
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Richard Henderson (1):
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decodetree: Improve identifier matching
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docs/system/arm/mps2.rst | 20 +-
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docs/system/arm/nuvoton.rst | 92 +++++
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docs/system/deprecated.rst | 32 +-
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docs/system/target-arm.rst | 1 +
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configure | 2 +-
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default-configs/arm-softmmu.mak | 1 +
83
include/hw/arm/npcm7xx.h | 112 +++++++
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include/hw/mem/npcm7xx_mc.h | 36 ++
85
include/hw/misc/npcm7xx_clk.h | 48 +++
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include/hw/misc/npcm7xx_gcr.h | 43 +++
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include/hw/nvram/npcm7xx_otp.h | 79 +++++
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include/hw/ssi/npcm7xx_fiu.h | 73 ++++
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include/hw/timer/npcm7xx_timer.h | 78 +++++
90
target/arm/kvm-consts.h | 7 -
91
target/arm/kvm_arm.h | 6 -
92
target/arm/neon-dp.decode | 18 +-
93
target/arm/neon-shared.decode | 18 +-
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tests/decode/succ_ident1.decode | 7 +
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hw/arm/mps2.c | 97 +++++-
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hw/arm/npcm7xx.c | 532 +++++++++++++++++++++++++++++
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hw/arm/npcm7xx_boards.c | 197 +++++++++++
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hw/arm/xlnx-versal-virt.c | 2 +-
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hw/mem/npcm7xx_mc.c | 84 +++++
100
hw/misc/a9scu.c | 59 ++--
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hw/misc/npcm7xx_clk.c | 266 +++++++++++++++
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hw/misc/npcm7xx_gcr.c | 269 +++++++++++++++
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hw/nvram/npcm7xx_otp.c | 440 ++++++++++++++++++++++++
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hw/ssi/npcm7xx_fiu.c | 572 +++++++++++++++++++++++++++++++
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hw/timer/armv7m_systick.c | 8 +
106
hw/timer/npcm7xx_timer.c | 543 ++++++++++++++++++++++++++++++
107
target/arm/cpu.c | 101 +++---
108
target/arm/helper.c | 2 +-
109
target/arm/kvm.c | 7 -
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target/arm/kvm32.c | 595 ---------------------------------
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.gitmodules | 3 +
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MAINTAINERS | 10 +
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hw/arm/Kconfig | 9 +
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hw/arm/meson.build | 1 +
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hw/mem/meson.build | 1 +
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hw/misc/meson.build | 4 +
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hw/misc/trace-events | 8 +
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hw/nvram/meson.build | 1 +
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hw/ssi/meson.build | 1 +
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hw/ssi/trace-events | 11 +
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hw/timer/meson.build | 1 +
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hw/timer/trace-events | 5 +
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pc-bios/README | 6 +
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pc-bios/meson.build | 1 +
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pc-bios/npcm7xx_bootrom.bin | Bin 0 -> 768 bytes
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roms/Makefile | 7 +
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roms/vbootrom | 1 +
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scripts/decodetree.py | 46 ++-
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target/arm/meson.build | 5 +-
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target/arm/translate-neon.c.inc | 42 ++-
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tests/acceptance/boot_linux_console.py | 83 +++++
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55 files changed, 3910 insertions(+), 783 deletions(-)
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create mode 100644 docs/system/arm/nuvoton.rst
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create mode 100644 include/hw/arm/npcm7xx.h
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create mode 100644 include/hw/mem/npcm7xx_mc.h
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create mode 100644 include/hw/misc/npcm7xx_clk.h
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create mode 100644 include/hw/misc/npcm7xx_gcr.h
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create mode 100644 include/hw/nvram/npcm7xx_otp.h
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create mode 100644 include/hw/ssi/npcm7xx_fiu.h
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create mode 100644 include/hw/timer/npcm7xx_timer.h
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create mode 100644 tests/decode/succ_ident1.decode
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create mode 100644 hw/arm/npcm7xx.c
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create mode 100644 hw/arm/npcm7xx_boards.c
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create mode 100644 hw/mem/npcm7xx_mc.c
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create mode 100644 hw/misc/npcm7xx_clk.c
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create mode 100644 hw/misc/npcm7xx_gcr.c
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create mode 100644 hw/nvram/npcm7xx_otp.c
148
create mode 100644 hw/ssi/npcm7xx_fiu.c
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create mode 100644 hw/timer/npcm7xx_timer.c
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delete mode 100644 target/arm/kvm32.c
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create mode 100644 pc-bios/npcm7xx_bootrom.bin
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create mode 160000 roms/vbootrom
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diff view generated by jsdifflib
[PULL 1/9] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
Deleted patch
1
From: Michael Tokarev <mjt@tls.msk.ru>
2
1
3
According to Cortex-R5 r1p2 manual, register with opcode2=0 is
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BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
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qemu labels them. Just swap the labels to avoid confusion, -
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both registers are implemented as always-zero.
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8
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241121171602.3273252-1-mjt@tls.msk.ru
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/tcg/cpu32.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
17
index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/tcg/cpu32.c
19
+++ b/target/arm/tcg/cpu32.c
20
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
21
22
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
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/* Dummy the TCM region regs for the moment */
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- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
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+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST },
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- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
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+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST },
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{ .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
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.opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/9] docs/system/arm/emulation: mention armv9
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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1
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241122225049.1617774-2-pierrick.bouvier@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
8
docs/system/arm/emulation.rst | 6 +++---
9
1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
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index XXXXXXX..XXXXXXX 100644
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--- a/docs/system/arm/emulation.rst
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+++ b/docs/system/arm/emulation.rst
15
@@ -XXX,XX +XXX,XX @@
16
A-profile CPU architecture support
17
==================================
18
19
-QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
20
-Armv8 versions of the A-profile architecture. It also has support for
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+QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7,
22
+Armv8 and Armv9 versions of the A-profile architecture. It also has support for
23
the following architecture extensions:
24
25
- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
26
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
27
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
28
29
For information on the specifics of these extensions, please refer
30
-to the `Armv8-A Arm Architecture Reference Manual
31
+to the `Arm Architecture Reference Manual for A-profile architecture
32
<https://developer.arm.com/documentation/ddi0487/latest>`_.
33
34
When a specific named CPU is being emulated, only those features which
35
--
36
2.34.1
diff view generated by jsdifflib
[PULL 3/9] docs/system/arm/emulation: fix typo in feature name
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241122225049.1617774-3-pierrick.bouvier@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
docs/system/arm/emulation.rst | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
12
index XXXXXXX..XXXXXXX 100644
13
--- a/docs/system/arm/emulation.rst
14
+++ b/docs/system/arm/emulation.rst
15
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
- FEAT_LSE2 (Large System Extensions v2)
17
- FEAT_LVA (Large Virtual Address space)
18
- FEAT_MixedEnd (Mixed-endian support)
19
-- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
20
+- FEAT_MixedEndEL0 (Mixed-endian support at EL0)
21
- FEAT_MOPS (Standardization of memory operations)
22
- FEAT_MTE (Memory Tagging Extension)
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- FEAT_MTE2 (Memory Tagging Extension)
24
--
25
2.34.1
diff view generated by jsdifflib
[PULL 4/9] docs/system/arm/emulation: add FEAT_SSBS2
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
We implemented this at the same times as FEAT_SSBS, but forgot
4
to list it in the documentation.
5
6
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241122225049.1617774-4-pierrick.bouvier@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
[PMM: improve commit message]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/system/arm/emulation.rst | 1 +
14
1 file changed, 1 insertion(+)
15
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
19
+++ b/docs/system/arm/emulation.rst
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
- FEAT_SVE2 (Scalable Vector Extension version 2)
22
- FEAT_SPECRES (Speculation restriction instructions)
23
- FEAT_SSBS (Speculative Store Bypass Safe)
24
+- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2)
25
- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
26
- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
27
- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
28
--
29
2.34.1
diff view generated by jsdifflib
[PULL 5/9] target/arm/tcg/: fix typo in FEAT name
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241122225049.1617774-5-pierrick.bouvier@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/tcg/cpu32.c | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
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12
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/cpu32.c
15
+++ b/target/arm/tcg/cpu32.c
16
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
17
cpu->isar.id_mmfr5 = t;
18
19
t = cpu->isar.id_pfr0;
20
- t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
21
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
22
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
23
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
24
cpu->isar.id_pfr0 = t;
25
--
26
2.34.1
27
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diff view generated by jsdifflib
[PULL 6/9] docs/system/arm/: add FEAT_MTE_ASYNC
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
We already implement FEAT_MTE_ASYNC; we just forgot to list it
4
in the documentation.
5
6
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241122225049.1617774-6-pierrick.bouvier@linaro.org
9
[PMM: expand commit message]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/arm/emulation.rst
18
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
- FEAT_MTE2 (Memory Tagging Extension)
21
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
22
- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
23
+- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault)
24
- FEAT_NMI (Non-maskable Interrupt)
25
- FEAT_NV (Nested Virtualization)
26
- FEAT_NV2 (Enhanced nested virtualization support)
27
--
28
2.34.1
diff view generated by jsdifflib
[PULL 7/9] docs/system/arm/: add FEAT_DoubleLock
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when
4
the ID registers call for it. This feature is actually one that must
5
*not* be implemented in v9.0, but since our documentation lists
6
everything we can emulate, we should include FEAT_DoubleLock in the
7
list.
8
9
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
10
Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
[PMM: expand commit message]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
docs/system/arm/emulation.rst | 1 +
16
1 file changed, 1 insertion(+)
17
18
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
19
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/emulation.rst
21
+++ b/docs/system/arm/emulation.rst
22
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
23
- FEAT_CSV3 (Cache speculation variant 3)
24
- FEAT_DGH (Data gathering hint)
25
- FEAT_DIT (Data Independent Timing instructions)
26
+- FEAT_DoubleLock (Double Lock)
27
- FEAT_DPB (DC CVAP instruction)
28
- FEAT_DPB2 (DC CVADP instruction)
29
- FEAT_Debugv8p1 (Debug with VHE)
30
--
31
2.34.1
diff view generated by jsdifflib
[PULL 8/9] docs/system/arm/fby35: update link to product page
Deleted patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
1
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20241122225049.1617774-8-pierrick.bouvier@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
10
docs/system/arm/fby35.rst | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
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index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/arm/fby35.rst
16
+++ b/docs/system/arm/fby35.rst
17
@@ -XXX,XX +XXX,XX @@ include various compute accelerators (video, inferencing, etc). At the moment,
18
only the first server slot's BIC is included.
19
20
Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
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-can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__
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+can be fit into a chassis. See `here <https://www.opencompute.org/products-chiplets/237/wiwynn-yosemite-v3-server>`__
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for an example.
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In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
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--
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2.34.1
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[PULL 9/9] docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
Deleted patch
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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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1
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Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Message-id: 20241122225049.1617774-13-pierrick.bouvier@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/system/arm/aspeed.rst | 7 ++++---
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1 file changed, 4 insertions(+), 3 deletions(-)
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diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
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index XXXXXXX..XXXXXXX 100644
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--- a/docs/system/arm/aspeed.rst
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+++ b/docs/system/arm/aspeed.rst
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@@ -XXX,XX +XXX,XX @@
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-Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
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-========================================================================================================================================================================================================================================================================================================================================================================================================
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+Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
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+==================================================================================================================================================================================================================================================================================================================================================================================================================================
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The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
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Aspeed evaluation boards. They are based on different releases of the
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@@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines :
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- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
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- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
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-- ``supermicrox11-bmc`` Supermicro X11 BMC
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+- ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
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+- ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
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AST2500 SoC based machines :
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--
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2.34.1
diff view generated by jsdifflib

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