On Tue, Nov 12, 2024 at 07:10:40PM +0100, Philippe Mathieu-Daudé wrote:
> Declare TX registers as MMIO region, split it out
> of the current mixed RAM/MMIO region.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
> ---
> hw/net/xilinx_ethlite.c | 71 ++++++++++++++++++++++++++++++++++-------
> 1 file changed, 59 insertions(+), 12 deletions(-)
>
> diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
> index 161fd97f06..159b2b0c64 100644
> --- a/hw/net/xilinx_ethlite.c
> +++ b/hw/net/xilinx_ethlite.c
> @@ -38,11 +38,11 @@
> #define A_MDIO_BASE 0x07e4
>
> #define R_TX_BUF0 0
> -#define R_TX_LEN0 (0x07f4 / 4)
> +#define A_TX_BASE0 0x07f4
> #define R_TX_GIE0 (0x07f8 / 4)
> #define R_TX_CTRL0 (0x07fc / 4)
> #define R_TX_BUF1 (0x0800 / 4)
> -#define R_TX_LEN1 (0x0ff4 / 4)
> +#define A_TX_BASE1 0x0ff4
> #define R_TX_CTRL1 (0x0ffc / 4)
>
> #define R_RX_BUF0 (0x1000 / 4)
> @@ -53,6 +53,11 @@
>
> #define RX_BUFSZ_MAX 0x07e0
>
> +enum {
> + TX_LEN = 0,
> + TX_MAX
> +};
> +
> enum {
> RX_CTRL = 0,
> RX_MAX
> @@ -125,6 +130,51 @@ static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index)
> return &s->regs[rxbase + R_RX_BUF0];
> }
>
> +static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> + XlnxXpsEthLite *s = opaque;
> + unsigned port_index = addr_to_port_index(addr);
> + uint32_t r = 0;
> +
> + switch (addr >> 2) {
> + case TX_LEN:
> + r = s->port[port_index].reg.tx_len;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + return r;
> +}
> +
> +static void port_tx_write(void *opaque, hwaddr addr, uint64_t value,
> + unsigned int size)
> +{
> + XlnxXpsEthLite *s = opaque;
> +
> + switch (addr >> 2) {
> + case TX_LEN:
> + s->port[port_index].reg.tx_len = value;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> +static const MemoryRegionOps eth_porttx_ops = {
> + .read = port_tx_read,
> + .write = port_tx_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .impl = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> +};
> +
> static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size)
> {
> XlnxXpsEthLite *s = opaque;
> @@ -187,11 +237,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
> r = s->port[port_index].reg.tx_gie;
> break;
>
> - case R_TX_LEN0:
> - case R_TX_LEN1:
> - r = s->port[port_index].reg.tx_len;
> - break;
> -
> case R_TX_CTRL1:
> case R_TX_CTRL0:
> r = s->port[port_index].reg.tx_ctrl;
> @@ -237,11 +282,6 @@ eth_write(void *opaque, hwaddr addr,
> break;
>
> /* Keep these native. */
> - case R_TX_LEN0:
> - case R_TX_LEN1:
> - s->port[port_index].reg.tx_len = value;
> - break;
> -
> case R_TX_GIE0:
> s->port[port_index].reg.tx_gie = value;
> break;
> @@ -330,6 +370,13 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0));
>
> for (unsigned i = 0; i < 2; i++) {
> + memory_region_init_io(&s->port[i].txio, OBJECT(dev),
> + ð_porttx_ops, s,
> + i ? "ethlite.tx[1]io" : "ethlite.tx[0]io",
> + 4 * TX_MAX);
> + memory_region_add_subregion(&s->mmio, i ? A_TX_BASE1 : A_TX_BASE0,
> + &s->port[i].txio);
> +
> memory_region_init_io(&s->port[i].rxio, OBJECT(dev),
> ð_portrx_ops, s,
> i ? "ethlite.rx[1]io" : "ethlite.rx[0]io",
> --
> 2.45.2
>