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[176.184.27.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381fc0f5f91sm7530136f8f.62.2024.11.12.10.12.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Nov 2024 10:12:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731435145; x=1732039945; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vGBo3n6UAnKrx1s/4bgTSsf0dXQKvd5mL1bf1mP4VKA=; b=qBkdv6jyWCtN8zjpBJWyuWiJX8yGSfdNNvIj9VLOoCk+sxL7ADaniBmSLhIEa5DQ1/ Vypk9eUNaBhsCgj3aagxVVPuJuQFvk4SXo0kVZTtNxm59phJfY8TZyOCGOToQckUET5U mWWf7vCydBRjY+XhosN6ikG3Cv6FeQiic7vDk+yT3E/Nm3x/FRQq5sytVx+BhRfwaF/N JrjIhh7P+Qj2/A2l5M3VBkSeG82108Qx5qJ05Ae2MmGRUZRCSTvT9nQxN7QXbhTxVrPJ LRvTVyqCw/iDYlNBoOsm+4BnZ0wib39+5N64e7BEn8H0+8izT3NGnq0nNAM2bAN7Id+Q A9jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731435145; x=1732039945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vGBo3n6UAnKrx1s/4bgTSsf0dXQKvd5mL1bf1mP4VKA=; b=oT+OVxxj/LqxrFOMiNVbxTxfwN3BW/h8UGpwqxXTF+A5uP4uGvYmgFRLe5HGTlJe9y cLB1ytuZw2f7pwU5GHmjgL4jMndwMp3lCrXISaDuKhqxJiDEISZ5hTkuWhG0rAoElKWC 79Qb1/hzGj0pAe9eG8xhr6JM+eWwXRlLolQhhJ5Zo229H//eGLvdtqJ/ZZyRDBIqTFsb lG+elwWZQvF1KVSmf+U5ifKopD27n10lJSZrTxl19jdjZPeSyOQPCUXC2hy5qsm+MF3B GQbNk8uB/T54mxzFVtO1FYJ98wou+KJnSy1z69Ca6ounb1XX0pD+SeVkMObzibCxKdp/ P6zw== X-Gm-Message-State: AOJu0Yw4GT253a3vqVyV9DPLMdhVM3bUWWMSbZcSNK4sSEbfQKvjM9yS ddQ8H+I2AGFz3JlIA3FS+iAZKxAm8TRm+U/AsU7Ag73HN+oEhanQ++AQ03GPkXAidRrj/0SfPR3 x X-Google-Smtp-Source: AGHT+IHAM2pwkgrLR2TnCGdm16wR68240SOagncYTL8Mt//7CKDK2CJti6oNBn9nOlRjKlJhFwVZBw== X-Received: by 2002:a5d:6484:0:b0:37e:d92f:c14a with SMTP id ffacd0b85a97d-381f188583bmr13802823f8f.42.1731435145331; Tue, 12 Nov 2024 10:12:25 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Richard Henderson , Peter Maydell , Anton Johansson , Jason Wang , qemu-arm@nongnu.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 16/20] hw/net/xilinx_ethlite: Map TX_LEN as MMIO Date: Tue, 12 Nov 2024 19:10:40 +0100 Message-ID: <20241112181044.92193-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112181044.92193-1-philmd@linaro.org> References: <20241112181044.92193-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731435391946116600 Declare TX registers as MMIO region, split it out of the current mixed RAM/MMIO region. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 71 ++++++++++++++++++++++++++++++++++------- 1 file changed, 59 insertions(+), 12 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 161fd97f06..159b2b0c64 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -38,11 +38,11 @@ #define A_MDIO_BASE 0x07e4 =20 #define R_TX_BUF0 0 -#define R_TX_LEN0 (0x07f4 / 4) +#define A_TX_BASE0 0x07f4 #define R_TX_GIE0 (0x07f8 / 4) #define R_TX_CTRL0 (0x07fc / 4) #define R_TX_BUF1 (0x0800 / 4) -#define R_TX_LEN1 (0x0ff4 / 4) +#define A_TX_BASE1 0x0ff4 #define R_TX_CTRL1 (0x0ffc / 4) =20 #define R_RX_BUF0 (0x1000 / 4) @@ -53,6 +53,11 @@ =20 #define RX_BUFSZ_MAX 0x07e0 =20 +enum { + TX_LEN =3D 0, + TX_MAX +}; + enum { RX_CTRL =3D 0, RX_MAX @@ -125,6 +130,51 @@ static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned por= t_index) return &s->regs[rxbase + R_RX_BUF0]; } =20 +static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) +{ + XlnxXpsEthLite *s =3D opaque; + unsigned port_index =3D addr_to_port_index(addr); + uint32_t r =3D 0; + + switch (addr >> 2) { + case TX_LEN: + r =3D s->port[port_index].reg.tx_len; + break; + default: + g_assert_not_reached(); + } + + return r; +} + +static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + XlnxXpsEthLite *s =3D opaque; + + switch (addr >> 2) { + case TX_LEN: + s->port[port_index].reg.tx_len =3D value; + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps eth_porttx_ops =3D { + .read =3D port_tx_read, + .write =3D port_tx_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size) { XlnxXpsEthLite *s =3D opaque; @@ -187,11 +237,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) r =3D s->port[port_index].reg.tx_gie; break; =20 - case R_TX_LEN0: - case R_TX_LEN1: - r =3D s->port[port_index].reg.tx_len; - break; - case R_TX_CTRL1: case R_TX_CTRL0: r =3D s->port[port_index].reg.tx_ctrl; @@ -237,11 +282,6 @@ eth_write(void *opaque, hwaddr addr, break; =20 /* Keep these native. */ - case R_TX_LEN0: - case R_TX_LEN1: - s->port[port_index].reg.tx_len =3D value; - break; - case R_TX_GIE0: s->port[port_index].reg.tx_gie =3D value; break; @@ -330,6 +370,13 @@ static void xilinx_ethlite_realize(DeviceState *dev, E= rror **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio= ), 0)); =20 for (unsigned i =3D 0; i < 2; i++) { + memory_region_init_io(&s->port[i].txio, OBJECT(dev), + ð_porttx_ops, s, + i ? "ethlite.tx[1]io" : "ethlite.tx[0]io", + 4 * TX_MAX); + memory_region_add_subregion(&s->mmio, i ? A_TX_BASE1 : A_TX_BASE0, + &s->port[i].txio); + memory_region_init_io(&s->port[i].rxio, OBJECT(dev), ð_portrx_ops, s, i ? "ethlite.rx[1]io" : "ethlite.rx[0]io", --=20 2.45.2