Set the NaN propagation rule explicitly for the float_status word
used in the rx target.
This not the architecturally correct behaviour, but since this is a
no-behaviour-change patch, we leave a TODO note to that effect.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-21-peter.maydell@linaro.org
---
target/rx/cpu.c | 7 +++++++
fpu/softfloat-specialize.c.inc | 3 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 36d2a6f1890..65a74ce720f 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -93,6 +93,13 @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
env->fpsw = 0;
set_flush_to_zero(1, &env->fp_status);
set_flush_inputs_to_zero(1, &env->fp_status);
+ /*
+ * TODO: this is not the correct NaN propagation rule for this
+ * architecture. The "RX Family User's Manual: Software" table 1.6
+ * defines the propagation rules as "prefer SNaN over QNaN;
+ * then prefer dest over source", which is float_2nan_prop_s_ab.
+ */
+ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
}
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index ee5c73cad46..254bbd67168 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -407,7 +407,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
|| defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \
|| defined(TARGET_SPARC) || defined(TARGET_XTENSA) \
|| defined(TARGET_I386) || defined(TARGET_ALPHA) \
- || defined(TARGET_MICROBLAZE) || defined(TARGET_OPENRISC)
+ || defined(TARGET_MICROBLAZE) || defined(TARGET_OPENRISC) \
+ || defined(TARGET_RX)
g_assert_not_reached();
#else
rule = float_2nan_prop_x87;
--
2.34.1