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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432a3688813sm16354555e9.1.2024.11.05.03.19.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2024 03:19:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730805589; x=1731410389; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=c8Sl2WdMeznJ3O6Hl+0ANVSekrp0/KXuiL2fAiYWe7Y=; b=EotC5W3wV5nQVA1Ke8WpTF007lOMb1cWooXAsyiANAhkKjC4umHkDzBMrzgZgRIWHE uBJ5msPmXvQlWzhQhnJ39grrI0UMQ4mn0ApbByFAfIFrtrIehQp9oEfMA5lhiXat5g/0 Ma78ALUfxlWvoz8FgGjVstqHA/arFdBG3XXA5EN8ZSVfaZ3vEMQEmo9MnA8Mr6XPdTas V2Fy+DvROddHLGUOLUTsPejxhMBxH0l4FBJkycYUVyHeIJL9mkVhM6a+GkJOnyLeewYR Pd50XEmL4ngFUQPxlsUqOFleWb0A0VmTSwdhLRG1aBLxiaCLd7M1ubW6xbHMauWEOZEO bnoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730805589; x=1731410389; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c8Sl2WdMeznJ3O6Hl+0ANVSekrp0/KXuiL2fAiYWe7Y=; b=rHYCHEjGkv1uc2pigdWC4qh1FPO5cEjxiT0i5UXMCQ7eoJVcNxCGhglgjNmV00oa0U m7/182SC4GqmEf1HEw50wUcvFvBxDAfhgeu0r2iH5a7B74cRGT+hFpl6zCNDaBnfaIJS SnOgIKvbjyPRnAcSl2ySBV1917XMskmCjGJ1PC8Ubma+3Cy/6WWiJ7bZJZ7omETAKk2D TOdntrC438aDzZr8TGstDRm87qkDjyPa2S+HAQCp/BiU0M48/fo+jvviJK/PabNipEoK oFQBBn1uinPVbrbnVxf/EedEyPcD0/nHsQdSX4nwk3jzY2gL56zRyCvYlQAsOq1HLBYG 0gRg== X-Gm-Message-State: AOJu0Yxd8YqagAehR4RnOKLPKjUT0BFFFlgkXTAKKvdltw6naW2oR5V7 QukvXcezM0Hoyj4dY6RKK0IkXUInhQwvGXBWKfeYGJFgVT6PPtvnAAkhnti2V+9Wf2PgEoeOzo2 3 X-Google-Smtp-Source: AGHT+IHeeZkES+0Ju2dE+HLTNR5HPuj11tiMMZi4a6APqWtBjhuH1PkSALEwUqxAWmI8Pc5a+yxT3w== X-Received: by 2002:a05:600c:3591:b0:431:680e:95d9 with SMTP id 5b1f17b1804b1-4327b7eac4emr165388775e9.22.1730805588717; Tue, 05 Nov 2024 03:19:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/31] target/rx: Explicitly set 2-NaN propagation rule Date: Tue, 5 Nov 2024 11:19:24 +0000 Message-Id: <20241105111935.2747034-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105111935.2747034-1-peter.maydell@linaro.org> References: <20241105111935.2747034-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730805671038116600 Set the NaN propagation rule explicitly for the float_status word used in the rx target. This not the architecturally correct behaviour, but since this is a no-behaviour-change patch, we leave a TODO note to that effect. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20241025141254.2141506-21-peter.maydell@linaro.org --- target/rx/cpu.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 36d2a6f1890..65a74ce720f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -93,6 +93,13 @@ static void rx_cpu_reset_hold(Object *obj, ResetType typ= e) env->fpsw =3D 0; set_flush_to_zero(1, &env->fp_status); set_flush_inputs_to_zero(1, &env->fp_status); + /* + * TODO: this is not the correct NaN propagation rule for this + * architecture. The "RX Family User's Manual: Software" table 1.6 + * defines the propagation rules as "prefer SNaN over QNaN; + * then prefer dest over source", which is float_2nan_prop_s_ab. + */ + set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); } =20 static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ee5c73cad46..254bbd67168 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -407,7 +407,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K= ) \ || defined(TARGET_SPARC) || defined(TARGET_XTENSA) \ || defined(TARGET_I386) || defined(TARGET_ALPHA) \ - || defined(TARGET_MICROBLAZE) || defined(TARGET_OPENRISC) + || defined(TARGET_MICROBLAZE) || defined(TARGET_OPENRISC) \ + || defined(TARGET_RX) g_assert_not_reached(); #else rule =3D float_2nan_prop_x87; --=20 2.34.1