The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:

  Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-10-29 14:00:43 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241031-1

for you to fetch changes up to c128d39edeff337220fc536a3e935bcba01ecb49:

  target/riscv: Fix vcompress with rvv_ta_all_1s (2024-10-31 13:51:24 +1000)

----------------------------------------------------------------
RISC-V PR for 9.2

* Fix an access to VXSAT
* Expose RV32 cpu to RV64 QEMU
* Don't clear PLIC pending bits on IRQ lowering
* Make PLIC zeroth priority register read-only
* Set vtype.vill on CPU reset
* Check and update APLIC pending when write sourcecfg
* Avoid dropping charecters with HTIF
* Apply FIFO backpressure to guests using SiFive UART
* Support for control flow integrity extensions
* Support for the IOMMU with the virt machine
* set 'aia_mode' to default in error path
* clarify how 'riscv-aia' default works

----------------------------------------------------------------
Alistair Francis (2):
      hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all
      hw/char: sifive_uart: Print uart characters async

Anton Blanchard (1):
      target/riscv: Fix vcompress with rvv_ta_all_1s

Daniel Henrique Barboza (6):
      pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
      test/qtest: add riscv-iommu-pci tests
      qtest/riscv-iommu-test: add init queues test
      docs/specs: add riscv-iommu
      target/riscv/kvm: set 'aia_mode' to default in error path
      target/riscv/kvm: clarify how 'riscv-aia' default works

Deepak Gupta (20):
      target/riscv: expose *envcfg csr and priv to qemu-user as well
      target/riscv: Add zicfilp extension
      target/riscv: Introduce elp state and enabling controls for zicfilp
      target/riscv: save and restore elp state on priv transitions
      target/riscv: additional code information for sw check
      target/riscv: tracking indirect branches (fcfi) for zicfilp
      target/riscv: zicfilp `lpad` impl and branch tracking
      disas/riscv: enable `lpad` disassembly
      target/riscv: Expose zicfilp extension as a cpu property
      target/riscv: Add zicfiss extension
      target/riscv: introduce ssp and enabling controls for zicfiss
      target/riscv: tb flag for shadow stack instructions
      target/riscv: mmu changes for zicfiss shadow stack protection
      target/riscv: AMO operations always raise store/AMO fault
      target/riscv: update `decode_save_opc` to store extra word2
      target/riscv: implement zicfiss instructions
      target/riscv: compressed encodings for sspush and sspopchk
      disas/riscv: enable disassembly for zicfiss instructions
      disas/riscv: enable disassembly for compressed sspush/sspopchk
      target/riscv: Expose zicfiss extension as a cpu property

Evgenii Prokopiev (1):
      target/riscv/csr.c: Fix an access to VXSAT

LIU Zhiwei (2):
      target/riscv: Add max32 CPU for RV64 QEMU
      tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU

Rob Bradford (1):
      target/riscv: Set vtype.vill on CPU reset

Sergey Makarov (2):
      hw/intc: Make zeroth priority register read-only
      hw/intc: Don't clear pending bits on IRQ lowering

TANG Tiancheng (6):
      target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
      target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
      target/riscv: Correct SXL return value for RV32 in RV64 QEMU
      target/riscv: Detect sxl to set bit width for RV32 in RV64
      target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
      target/riscv: Enable RV32 CPU support in RV64 QEMU

Tomasz Jeznach (8):
      exec/memtxattr: add process identifier to the transaction attributes
      hw/riscv: add riscv-iommu-bits.h
      hw/riscv: add RISC-V IOMMU base emulation
      hw/riscv: add riscv-iommu-pci reference device
      hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
      hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
      hw/riscv/riscv-iommu: add ATS support
      hw/riscv/riscv-iommu: add DBG support

Yong-Xuan Wang (1):
      hw/intc/riscv_aplic: Check and update pending when write sourcecfg

 docs/specs/index.rst                           |    1 +
 docs/specs/pci-ids.rst                         |    2 +
 docs/specs/riscv-iommu.rst                     |   90 +
 docs/system/riscv/virt.rst                     |   13 +
 configs/targets/riscv64-softmmu.mak            |    2 +-
 meson.build                                    |    1 +
 disas/riscv.h                                  |    4 +
 hw/riscv/riscv-iommu-bits.h                    |  421 +++++
 hw/riscv/riscv-iommu.h                         |  130 ++
 hw/riscv/trace.h                               |    1 +
 include/exec/memattrs.h                        |    5 +
 include/hw/char/sifive_uart.h                  |   16 +-
 include/hw/pci/pci.h                           |    1 +
 include/hw/riscv/boot.h                        |    4 +-
 include/hw/riscv/boot_opensbi.h                |   29 +
 include/hw/riscv/iommu.h                       |   36 +
 target/riscv/cpu-qom.h                         |    1 +
 target/riscv/cpu.h                             |   36 +-
 target/riscv/cpu_bits.h                        |   17 +
 target/riscv/cpu_cfg.h                         |    2 +
 target/riscv/cpu_user.h                        |    1 +
 target/riscv/internals.h                       |    3 +
 target/riscv/pmp.h                             |    3 +-
 tests/qtest/libqos/riscv-iommu.h               |  101 +
 target/riscv/insn16.decode                     |    4 +
 target/riscv/insn32.decode                     |   26 +-
 disas/riscv.c                                  |   77 +-
 hw/char/riscv_htif.c                           |   12 +-
 hw/char/sifive_uart.c                          |   97 +-
 hw/intc/riscv_aplic.c                          |   51 +-
 hw/intc/sifive_plic.c                          |   15 +-
 hw/riscv/boot.c                                |   35 +-
 hw/riscv/riscv-iommu-pci.c                     |  202 ++
 hw/riscv/riscv-iommu.c                         | 2399 ++++++++++++++++++++++++
 hw/riscv/sifive_u.c                            |    3 +-
 hw/riscv/virt.c                                |   33 +-
 target/riscv/cpu.c                             |   43 +-
 target/riscv/cpu_helper.c                      |  209 ++-
 target/riscv/csr.c                             |   88 +-
 target/riscv/kvm/kvm-cpu.c                     |   22 +-
 target/riscv/machine.c                         |   38 +
 target/riscv/op_helper.c                       |   17 +
 target/riscv/pmp.c                             |    7 +-
 target/riscv/tcg/tcg-cpu.c                     |   29 +
 target/riscv/translate.c                       |   44 +-
 target/riscv/vector_helper.c                   |    2 +-
 tests/qtest/libqos/riscv-iommu.c               |   76 +
 tests/qtest/riscv-iommu-test.c                 |  210 +++
 target/riscv/insn_trans/trans_privileged.c.inc |    8 +-
 target/riscv/insn_trans/trans_rva.c.inc        |    4 +-
 target/riscv/insn_trans/trans_rvd.c.inc        |    4 +-
 target/riscv/insn_trans/trans_rvf.c.inc        |    4 +-
 target/riscv/insn_trans/trans_rvh.c.inc        |    8 +-
 target/riscv/insn_trans/trans_rvi.c.inc        |   61 +-
 target/riscv/insn_trans/trans_rvvk.c.inc       |   10 +-
 target/riscv/insn_trans/trans_rvzacas.c.inc    |    4 +-
 target/riscv/insn_trans/trans_rvzfh.c.inc      |    4 +-
 target/riscv/insn_trans/trans_rvzicfiss.c.inc  |  114 ++
 target/riscv/insn_trans/trans_svinval.c.inc    |    6 +-
 hw/riscv/Kconfig                               |    4 +
 hw/riscv/meson.build                           |    1 +
 hw/riscv/trace-events                          |   17 +
 tests/avocado/tuxrun_baselines.py              |   16 +
 tests/qtest/libqos/meson.build                 |    4 +
 tests/qtest/meson.build                        |    1 +
 65 files changed, 4790 insertions(+), 139 deletions(-)
 create mode 100644 docs/specs/riscv-iommu.rst
 create mode 100644 hw/riscv/riscv-iommu-bits.h
 create mode 100644 hw/riscv/riscv-iommu.h
 create mode 100644 hw/riscv/trace.h
 create mode 100644 include/hw/riscv/iommu.h
 create mode 100644 tests/qtest/libqos/riscv-iommu.h
 create mode 100644 hw/riscv/riscv-iommu-pci.c
 create mode 100644 hw/riscv/riscv-iommu.c
 create mode 100644 tests/qtest/libqos/riscv-iommu.c
 create mode 100644 tests/qtest/riscv-iommu-test.c
 create mode 100644 target/riscv/insn_trans/trans_rvzicfiss.c.inc
 create mode 100644 hw/riscv/trace-events

On Thu, 31 Oct 2024 at 03:54, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
>
>   Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-10-29 14:00:43 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241031-1
>
> for you to fetch changes up to c128d39edeff337220fc536a3e935bcba01ecb49:
>
>   target/riscv: Fix vcompress with rvv_ta_all_1s (2024-10-31 13:51:24 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.2
>
> * Fix an access to VXSAT
> * Expose RV32 cpu to RV64 QEMU
> * Don't clear PLIC pending bits on IRQ lowering
> * Make PLIC zeroth priority register read-only
> * Set vtype.vill on CPU reset
> * Check and update APLIC pending when write sourcecfg
> * Avoid dropping charecters with HTIF
> * Apply FIFO backpressure to guests using SiFive UART
> * Support for control flow integrity extensions
> * Support for the IOMMU with the virt machine
> * set 'aia_mode' to default in error path
> * clarify how 'riscv-aia' default works


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2
for any user-visible changes.

-- PMM

31.10.2024 06:52, Alistair Francis wrote:

> ----------------------------------------------------------------
> RISC-V PR for 9.2
> 
> * Fix an access to VXSAT
> * Expose RV32 cpu to RV64 QEMU
> * Don't clear PLIC pending bits on IRQ lowering
> * Make PLIC zeroth priority register read-only
> * Set vtype.vill on CPU reset
> * Check and update APLIC pending when write sourcecfg
> * Avoid dropping charecters with HTIF
> * Apply FIFO backpressure to guests using SiFive UART
> * Support for control flow integrity extensions
> * Support for the IOMMU with the virt machine
> * set 'aia_mode' to default in error path
> * clarify how 'riscv-aia' default works

Is there anything in there which is worth picking up for qemu-stable?
I see numerous "fixes" in there, but I'm not sure which is which and
what is important to have working in 9.1, 9.0, 8.2 (ubuntu lts) or 7.2...
(I've added some CCs)

Thanks,

/mjt

> ----------------------------------------------------------------
> Alistair Francis (2):
>        hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all
>        hw/char: sifive_uart: Print uart characters async
> 
> Anton Blanchard (1):
>        target/riscv: Fix vcompress with rvv_ta_all_1s
> 
> Daniel Henrique Barboza (6):
>        pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
>        test/qtest: add riscv-iommu-pci tests
>        qtest/riscv-iommu-test: add init queues test
>        docs/specs: add riscv-iommu
>        target/riscv/kvm: set 'aia_mode' to default in error path
>        target/riscv/kvm: clarify how 'riscv-aia' default works
> 
> Deepak Gupta (20):
>        target/riscv: expose *envcfg csr and priv to qemu-user as well
>        target/riscv: Add zicfilp extension
>        target/riscv: Introduce elp state and enabling controls for zicfilp
>        target/riscv: save and restore elp state on priv transitions
>        target/riscv: additional code information for sw check
>        target/riscv: tracking indirect branches (fcfi) for zicfilp
>        target/riscv: zicfilp `lpad` impl and branch tracking
>        disas/riscv: enable `lpad` disassembly
>        target/riscv: Expose zicfilp extension as a cpu property
>        target/riscv: Add zicfiss extension
>        target/riscv: introduce ssp and enabling controls for zicfiss
>        target/riscv: tb flag for shadow stack instructions
>        target/riscv: mmu changes for zicfiss shadow stack protection
>        target/riscv: AMO operations always raise store/AMO fault
>        target/riscv: update `decode_save_opc` to store extra word2
>        target/riscv: implement zicfiss instructions
>        target/riscv: compressed encodings for sspush and sspopchk
>        disas/riscv: enable disassembly for zicfiss instructions
>        disas/riscv: enable disassembly for compressed sspush/sspopchk
>        target/riscv: Expose zicfiss extension as a cpu property
> 
> Evgenii Prokopiev (1):
>        target/riscv/csr.c: Fix an access to VXSAT
> 
> LIU Zhiwei (2):
>        target/riscv: Add max32 CPU for RV64 QEMU
>        tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
> 
> Rob Bradford (1):
>        target/riscv: Set vtype.vill on CPU reset
> 
> Sergey Makarov (2):
>        hw/intc: Make zeroth priority register read-only
>        hw/intc: Don't clear pending bits on IRQ lowering
> 
> TANG Tiancheng (6):
>        target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
>        target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
>        target/riscv: Correct SXL return value for RV32 in RV64 QEMU
>        target/riscv: Detect sxl to set bit width for RV32 in RV64
>        target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
>        target/riscv: Enable RV32 CPU support in RV64 QEMU
> 
> Tomasz Jeznach (8):
>        exec/memtxattr: add process identifier to the transaction attributes
>        hw/riscv: add riscv-iommu-bits.h
>        hw/riscv: add RISC-V IOMMU base emulation
>        hw/riscv: add riscv-iommu-pci reference device
>        hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
>        hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
>        hw/riscv/riscv-iommu: add ATS support
>        hw/riscv/riscv-iommu: add DBG support
> 
> Yong-Xuan Wang (1):
>        hw/intc/riscv_aplic: Check and update pending when write sourcecfg

On Fri, Nov 1, 2024 at 11:40 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 31.10.2024 06:52, Alistair Francis wrote:
>
> > ----------------------------------------------------------------
> > RISC-V PR for 9.2
> >
> > * Fix an access to VXSAT
> > * Expose RV32 cpu to RV64 QEMU
> > * Don't clear PLIC pending bits on IRQ lowering
> > * Make PLIC zeroth priority register read-only
> > * Set vtype.vill on CPU reset
> > * Check and update APLIC pending when write sourcecfg
> > * Avoid dropping charecters with HTIF
> > * Apply FIFO backpressure to guests using SiFive UART
> > * Support for control flow integrity extensions
> > * Support for the IOMMU with the virt machine
> > * set 'aia_mode' to default in error path
> > * clarify how 'riscv-aia' default works
>
> Is there anything in there which is worth picking up for qemu-stable?

Sorry, I forgot to CC the patches

I think these are all worth backporting, but aren't critical fixes so
if there are any issues applying them just skip them:

target/riscv/csr.c: Fix an access to VXSAT
hw/intc: Don't clear pending bits on IRQ lowering
target/riscv: Set vtype.vill on CPU reset
hw/intc/riscv_aplic: Check and update pending when write sourcecfg
target/riscv/kvm: set 'aia_mode' to default in error path
target/riscv/kvm: clarify how 'riscv-aia' default works
target/riscv: Fix vcompress with rvv_ta_all_1s

Alistair

> I see numerous "fixes" in there, but I'm not sure which is which and
> what is important to have working in 9.1, 9.0, 8.2 (ubuntu lts) or 7.2...
> (I've added some CCs)
>
> Thanks,
>
> /mjt
>
> > ----------------------------------------------------------------
> > Alistair Francis (2):
> >        hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all
> >        hw/char: sifive_uart: Print uart characters async
> >
> > Anton Blanchard (1):
> >        target/riscv: Fix vcompress with rvv_ta_all_1s
> >
> > Daniel Henrique Barboza (6):
> >        pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
> >        test/qtest: add riscv-iommu-pci tests
> >        qtest/riscv-iommu-test: add init queues test
> >        docs/specs: add riscv-iommu
> >        target/riscv/kvm: set 'aia_mode' to default in error path
> >        target/riscv/kvm: clarify how 'riscv-aia' default works
> >
> > Deepak Gupta (20):
> >        target/riscv: expose *envcfg csr and priv to qemu-user as well
> >        target/riscv: Add zicfilp extension
> >        target/riscv: Introduce elp state and enabling controls for zicfilp
> >        target/riscv: save and restore elp state on priv transitions
> >        target/riscv: additional code information for sw check
> >        target/riscv: tracking indirect branches (fcfi) for zicfilp
> >        target/riscv: zicfilp `lpad` impl and branch tracking
> >        disas/riscv: enable `lpad` disassembly
> >        target/riscv: Expose zicfilp extension as a cpu property
> >        target/riscv: Add zicfiss extension
> >        target/riscv: introduce ssp and enabling controls for zicfiss
> >        target/riscv: tb flag for shadow stack instructions
> >        target/riscv: mmu changes for zicfiss shadow stack protection
> >        target/riscv: AMO operations always raise store/AMO fault
> >        target/riscv: update `decode_save_opc` to store extra word2
> >        target/riscv: implement zicfiss instructions
> >        target/riscv: compressed encodings for sspush and sspopchk
> >        disas/riscv: enable disassembly for zicfiss instructions
> >        disas/riscv: enable disassembly for compressed sspush/sspopchk
> >        target/riscv: Expose zicfiss extension as a cpu property
> >
> > Evgenii Prokopiev (1):
> >        target/riscv/csr.c: Fix an access to VXSAT
> >
> > LIU Zhiwei (2):
> >        target/riscv: Add max32 CPU for RV64 QEMU
> >        tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
> >
> > Rob Bradford (1):
> >        target/riscv: Set vtype.vill on CPU reset
> >
> > Sergey Makarov (2):
> >        hw/intc: Make zeroth priority register read-only
> >        hw/intc: Don't clear pending bits on IRQ lowering
> >
> > TANG Tiancheng (6):
> >        target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
> >        target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
> >        target/riscv: Correct SXL return value for RV32 in RV64 QEMU
> >        target/riscv: Detect sxl to set bit width for RV32 in RV64
> >        target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
> >        target/riscv: Enable RV32 CPU support in RV64 QEMU
> >
> > Tomasz Jeznach (8):
> >        exec/memtxattr: add process identifier to the transaction attributes
> >        hw/riscv: add riscv-iommu-bits.h
> >        hw/riscv: add RISC-V IOMMU base emulation
> >        hw/riscv: add riscv-iommu-pci reference device
> >        hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
> >        hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
> >        hw/riscv/riscv-iommu: add ATS support
> >        hw/riscv/riscv-iommu: add DBG support
> >
> > Yong-Xuan Wang (1):
> >        hw/intc/riscv_aplic: Check and update pending when write sourcecfg
>
>

05.11.2024 01:57, Alistair Francis wrote:

>>> RISC-V PR for 9.2
>>>
>>> * Fix an access to VXSAT
>>> * Expose RV32 cpu to RV64 QEMU
>>> * Don't clear PLIC pending bits on IRQ lowering
>>> * Make PLIC zeroth priority register read-only
>>> * Set vtype.vill on CPU reset
>>> * Check and update APLIC pending when write sourcecfg
>>> * Avoid dropping charecters with HTIF
>>> * Apply FIFO backpressure to guests using SiFive UART
>>> * Support for control flow integrity extensions
>>> * Support for the IOMMU with the virt machine
>>> * set 'aia_mode' to default in error path
>>> * clarify how 'riscv-aia' default works
>>
>> Is there anything in there which is worth picking up for qemu-stable?
> 
> Sorry, I forgot to CC the patches
> 
> I think these are all worth backporting, but aren't critical fixes so
> if there are any issues applying them just skip them:
> 
> target/riscv/csr.c: Fix an access to VXSAT
> hw/intc: Don't clear pending bits on IRQ lowering
> target/riscv: Set vtype.vill on CPU reset
> hw/intc/riscv_aplic: Check and update pending when write sourcecfg
> target/riscv/kvm: set 'aia_mode' to default in error path
> target/riscv/kvm: clarify how 'riscv-aia' default works
> target/riscv: Fix vcompress with rvv_ta_all_1s

So I picked up all the above for 9.1.x & 9.0.x.

For 2ae6cca1d33898 "hw/intc/riscv_aplic: Check and update pending when
write sourcecfg", for 8.2.x and 7.2.x, an additional patch were needed,
0678e9f29c2301 "hw/intc/riscv_aplic: Fix in_clrip[x] read emulation"
(both applies cleanly) - hopefully this one is also okay, though it is
a bit old(ish) already.

And the aia changes are not relevant for 7.2.x.

I'm now running tests, but it looks like the whole thing is quite good
now.

Does it look ok?

I pushed current staging-7.2, staging-8.2, staging-9.0 and staging-9.1
branches to https://gitlab.com/mjt0k/qemu.git/

Thank you for the comments!

BTW, tangtiancheng.ttc@alibaba-inc.com bounces: host mx1.alibaba-inc.com[47.246.137.48]
     said: 553 "RCPT TO" mailbox unavailable (in reply to RCPT TO command)

/mjt

On Tue, Nov 5, 2024 at 5:45 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 05.11.2024 01:57, Alistair Francis wrote:
>
> >>> RISC-V PR for 9.2
> >>>
> >>> * Fix an access to VXSAT
> >>> * Expose RV32 cpu to RV64 QEMU
> >>> * Don't clear PLIC pending bits on IRQ lowering
> >>> * Make PLIC zeroth priority register read-only
> >>> * Set vtype.vill on CPU reset
> >>> * Check and update APLIC pending when write sourcecfg
> >>> * Avoid dropping charecters with HTIF
> >>> * Apply FIFO backpressure to guests using SiFive UART
> >>> * Support for control flow integrity extensions
> >>> * Support for the IOMMU with the virt machine
> >>> * set 'aia_mode' to default in error path
> >>> * clarify how 'riscv-aia' default works
> >>
> >> Is there anything in there which is worth picking up for qemu-stable?
> >
> > Sorry, I forgot to CC the patches
> >
> > I think these are all worth backporting, but aren't critical fixes so
> > if there are any issues applying them just skip them:
> >
> > target/riscv/csr.c: Fix an access to VXSAT
> > hw/intc: Don't clear pending bits on IRQ lowering
> > target/riscv: Set vtype.vill on CPU reset
> > hw/intc/riscv_aplic: Check and update pending when write sourcecfg
> > target/riscv/kvm: set 'aia_mode' to default in error path
> > target/riscv/kvm: clarify how 'riscv-aia' default works
> > target/riscv: Fix vcompress with rvv_ta_all_1s
>
> So I picked up all the above for 9.1.x & 9.0.x.

Thanks!

>
> For 2ae6cca1d33898 "hw/intc/riscv_aplic: Check and update pending when
> write sourcecfg", for 8.2.x and 7.2.x, an additional patch were needed,
> 0678e9f29c2301 "hw/intc/riscv_aplic: Fix in_clrip[x] read emulation"
> (both applies cleanly) - hopefully this one is also okay, though it is
> a bit old(ish) already.
>
> And the aia changes are not relevant for 7.2.x.
>
> I'm now running tests, but it looks like the whole thing is quite good
> now.
>
> Does it look ok?

That sounds fine to me.

Alistair

>
> I pushed current staging-7.2, staging-8.2, staging-9.0 and staging-9.1
> branches to https://gitlab.com/mjt0k/qemu.git/
>
> Thank you for the comments!
>
> BTW, tangtiancheng.ttc@alibaba-inc.com bounces: host mx1.alibaba-inc.com[47.246.137.48]
>      said: 553 "RCPT TO" mailbox unavailable (in reply to RCPT TO command)
>
> /mjt

05.11.2024 10:45, Michael Tokarev wrote:

>> target/riscv/csr.c: Fix an access to VXSAT
>> hw/intc: Don't clear pending bits on IRQ lowering
>> target/riscv: Set vtype.vill on CPU reset
>> hw/intc/riscv_aplic: Check and update pending when write sourcecfg
>> target/riscv/kvm: set 'aia_mode' to default in error path
>> target/riscv/kvm: clarify how 'riscv-aia' default works
>> target/riscv: Fix vcompress with rvv_ta_all_1s
> 
> So I picked up all the above for 9.1.x & 9.0.x.
> 
> For 2ae6cca1d33898 "hw/intc/riscv_aplic: Check and update pending when
> write sourcecfg", for 8.2.x and 7.2.x, an additional patch were needed,
> 0678e9f29c2301 "hw/intc/riscv_aplic: Fix in_clrip[x] read emulation"
> (both applies cleanly) - hopefully this one is also okay, though it is
> a bit old(ish) already.
> 
> And the aia changes are not relevant for 7.2.x.
> 
> I'm now running tests, but it looks like the whole thing is quite good
> now.
> 
> Does it look ok?
> 
> I pushed current staging-7.2, staging-8.2, staging-9.0 and staging-9.1
> branches to https://gitlab.com/mjt0k/qemu.git/

To clarify.

7.2 is current debian stable (bookworm).
8.2 is current ubuntu LTS (noble) - hopefully anyway, - they promised me
     to pick things up from the upstream stable-8.2 branch

So 7.2.x and 8.2.x might be with us for quite some time, with users
actually using them, also in various data centers, hostings etc.

next 9.0 will be the last release in 9.0.x series
9.1 is the current qemu stable (latest qemu release).

Thanks,

/mjt

On 11/1/24 10:39 AM, Michael Tokarev wrote:
> 31.10.2024 06:52, Alistair Francis wrote:
> 
>> ----------------------------------------------------------------
>> RISC-V PR for 9.2
>>
>> * Fix an access to VXSAT
>> * Expose RV32 cpu to RV64 QEMU
>> * Don't clear PLIC pending bits on IRQ lowering
>> * Make PLIC zeroth priority register read-only
>> * Set vtype.vill on CPU reset
>> * Check and update APLIC pending when write sourcecfg
>> * Avoid dropping charecters with HTIF
>> * Apply FIFO backpressure to guests using SiFive UART
>> * Support for control flow integrity extensions
>> * Support for the IOMMU with the virt machine
>> * set 'aia_mode' to default in error path
>> * clarify how 'riscv-aia' default works
> 
> Is there anything in there which is worth picking up for qemu-stable?

I believe everything that has a "Fixes" tags can be ported to qemu-stable.

As for what should be ported to older stables, unless there's an open bug in Gitlab
that is aimed at an older stable release I wouldn't worry about it. Applying in the
current qemu-stable is enough.


Thanks,

Daniel

> I see numerous "fixes" in there, but I'm not sure which is which and
> what is important to have working in 9.1, 9.0, 8.2 (ubuntu lts) or 7.2...
> (I've added some CCs)
> 
> Thanks,
> 
> /mjt
> 
>> ----------------------------------------------------------------
>> Alistair Francis (2):
>>        hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all
>>        hw/char: sifive_uart: Print uart characters async
>>
>> Anton Blanchard (1):
>>        target/riscv: Fix vcompress with rvv_ta_all_1s
>>
>> Daniel Henrique Barboza (6):
>>        pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
>>        test/qtest: add riscv-iommu-pci tests
>>        qtest/riscv-iommu-test: add init queues test
>>        docs/specs: add riscv-iommu
>>        target/riscv/kvm: set 'aia_mode' to default in error path
>>        target/riscv/kvm: clarify how 'riscv-aia' default works
>>
>> Deepak Gupta (20):
>>        target/riscv: expose *envcfg csr and priv to qemu-user as well
>>        target/riscv: Add zicfilp extension
>>        target/riscv: Introduce elp state and enabling controls for zicfilp
>>        target/riscv: save and restore elp state on priv transitions
>>        target/riscv: additional code information for sw check
>>        target/riscv: tracking indirect branches (fcfi) for zicfilp
>>        target/riscv: zicfilp `lpad` impl and branch tracking
>>        disas/riscv: enable `lpad` disassembly
>>        target/riscv: Expose zicfilp extension as a cpu property
>>        target/riscv: Add zicfiss extension
>>        target/riscv: introduce ssp and enabling controls for zicfiss
>>        target/riscv: tb flag for shadow stack instructions
>>        target/riscv: mmu changes for zicfiss shadow stack protection
>>        target/riscv: AMO operations always raise store/AMO fault
>>        target/riscv: update `decode_save_opc` to store extra word2
>>        target/riscv: implement zicfiss instructions
>>        target/riscv: compressed encodings for sspush and sspopchk
>>        disas/riscv: enable disassembly for zicfiss instructions
>>        disas/riscv: enable disassembly for compressed sspush/sspopchk
>>        target/riscv: Expose zicfiss extension as a cpu property
>>
>> Evgenii Prokopiev (1):
>>        target/riscv/csr.c: Fix an access to VXSAT
>>
>> LIU Zhiwei (2):
>>        target/riscv: Add max32 CPU for RV64 QEMU
>>        tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
>>
>> Rob Bradford (1):
>>        target/riscv: Set vtype.vill on CPU reset
>>
>> Sergey Makarov (2):
>>        hw/intc: Make zeroth priority register read-only
>>        hw/intc: Don't clear pending bits on IRQ lowering
>>
>> TANG Tiancheng (6):
>>        target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
>>        target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
>>        target/riscv: Correct SXL return value for RV32 in RV64 QEMU
>>        target/riscv: Detect sxl to set bit width for RV32 in RV64
>>        target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
>>        target/riscv: Enable RV32 CPU support in RV64 QEMU
>>
>> Tomasz Jeznach (8):
>>        exec/memtxattr: add process identifier to the transaction attributes
>>        hw/riscv: add riscv-iommu-bits.h
>>        hw/riscv: add RISC-V IOMMU base emulation
>>        hw/riscv: add riscv-iommu-pci reference device
>>        hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
>>        hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
>>        hw/riscv/riscv-iommu: add ATS support
>>        hw/riscv/riscv-iommu: add DBG support
>>
>> Yong-Xuan Wang (1):
>>        hw/intc/riscv_aplic: Check and update pending when write sourcecfg
> 
> 
>