The RISC-V unprivileged specification "31.3.11. State of Vector
Extension at Reset" has a note that recommends vtype.vill be set on
reset as part of ensuring that the vector extension have a consistent
state at reset.

This change now makes QEMU consistent with Spike which sets vtype.vill
on reset.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bda754b01..af602e3caf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -997,6 +997,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+    env->vill = true;
 
 #ifndef CONFIG_USER_ONLY
     if (cpu->cfg.debug) {
-- 
2.46.0

On Tue, Oct 1, 2024 at 2:53 AM Rob Bradford <rbradford@rivosinc.com> wrote:
>
> The RISC-V unprivileged specification "31.3.11. State of Vector
> Extension at Reset" has a note that recommends vtype.vill be set on
> reset as part of ensuring that the vector extension have a consistent
> state at reset.
>
> This change now makes QEMU consistent with Spike which sets vtype.vill
> on reset.
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4bda754b01..af602e3caf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -997,6 +997,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>      cs->exception_index = RISCV_EXCP_NONE;
>      env->load_res = -1;
>      set_default_nan_mode(1, &env->fp_status);
> +    env->vill = true;
>
>  #ifndef CONFIG_USER_ONLY
>      if (cpu->cfg.debug) {
> --
> 2.46.0
>
>

On 9/30/24 1:52 PM, Rob Bradford wrote:
> The RISC-V unprivileged specification "31.3.11. State of Vector
> Extension at Reset" has a note that recommends vtype.vill be set on
> reset as part of ensuring that the vector extension have a consistent
> state at reset.
> 
> This change now makes QEMU consistent with Spike which sets vtype.vill
> on reset.
> 
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4bda754b01..af602e3caf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -997,6 +997,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>       cs->exception_index = RISCV_EXCP_NONE;
>       env->load_res = -1;
>       set_default_nan_mode(1, &env->fp_status);
> +    env->vill = true;
>   
>   #ifndef CONFIG_USER_ONLY
>       if (cpu->cfg.debug) {