The chip_pir chip class method allows the platform to set the PIR
processor identification register. Extend this to a more general
ID function which also allows the TIR to be set. This is in
preparation for "big core", which is a more complicated topology
of cores and threads.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/pnv_chip.h | 4 +-
hw/ppc/pnv.c | 85 +++++++++++++++++++++++++--------------
hw/ppc/pnv_core.c | 10 +++--
3 files changed, 64 insertions(+), 35 deletions(-)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index decfbc0ff7..1fca540eb1 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -152,7 +152,9 @@ struct PnvChipClass {
DeviceRealize parent_realize;
- uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id);
+ /* Get PIR and TIR values for a CPU thread identified by core/thread id */
+ void (*get_pir_tir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id,
+ uint32_t *pir, uint32_t *tir);
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 4252bcd28d..b593a41f7c 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -154,7 +154,7 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
char *nodename;
int cpus_offset = get_cpus_node(fdt);
- pir = pnv_cc->chip_pir(chip, pc->hwid, 0);
+ pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, NULL);
nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
offset = fdt_add_subnode(fdt, cpus_offset, nodename);
@@ -236,7 +236,8 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
/* Build interrupt servers properties */
for (i = 0; i < smt_threads; i++) {
- servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i));
+ pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
+ servers_prop[i] = cpu_to_be32(pir);
}
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
servers_prop, sizeof(*servers_prop) * smt_threads)));
@@ -248,14 +249,17 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid,
uint32_t nr_threads)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
- uint32_t pir = pcc->chip_pir(chip, hwid, 0);
- uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
+ uint32_t pir;
+ uint64_t addr;
char *name;
const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
uint32_t irange[2], i, rsize;
uint64_t *reg;
int offset;
+ pcc->get_pir_tir(chip, hwid, 0, &pir, NULL);
+ addr = PNV_ICP_BASE(chip) | (pir << 12);
+
irange[0] = cpu_to_be32(pir);
irange[1] = cpu_to_be32(nr_threads);
@@ -1106,10 +1110,16 @@ static void pnv_init(MachineState *machine)
* 25:28 Core number
* 29:31 Thread ID
*/
-static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id,
- uint32_t thread_id)
+static void pnv_get_pir_tir_p8(PnvChip *chip,
+ uint32_t core_id, uint32_t thread_id,
+ uint32_t *pir, uint32_t *tir)
{
- return (chip->chip_id << 7) | (core_id << 3) | thread_id;
+ if (pir) {
+ *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id;
+ }
+ if (tir) {
+ *tir = thread_id;
+ }
}
static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
@@ -1161,14 +1171,20 @@ static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
*
* We only care about the lower bits. uint32_t is fine for the moment.
*/
-static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id,
- uint32_t thread_id)
-{
- if (chip->nr_threads == 8) {
- return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) |
- (thread_id >> 1);
- } else {
- return (chip->chip_id << 8) | (core_id << 2) | thread_id;
+static void pnv_get_pir_tir_p9(PnvChip *chip,
+ uint32_t core_id, uint32_t thread_id,
+ uint32_t *pir, uint32_t *tir)
+{
+ if (pir) {
+ if (chip->nr_threads == 8) {
+ *pir = (chip->chip_id << 8) | ((thread_id & 1) << 2) |
+ (core_id << 3) | (thread_id >> 1);
+ } else {
+ *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id;
+ }
+ }
+ if (tir) {
+ *tir = thread_id;
}
}
@@ -1183,14 +1199,20 @@ static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id,
*
* We only care about the lower bits. uint32_t is fine for the moment.
*/
-static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id,
- uint32_t thread_id)
-{
- if (chip->nr_threads == 8) {
- return (chip->chip_id << 8) | ((core_id / 4) << 4) |
- ((core_id % 2) << 3) | thread_id;
- } else {
- return (chip->chip_id << 8) | (core_id << 2) | thread_id;
+static void pnv_get_pir_tir_p10(PnvChip *chip,
+ uint32_t core_id, uint32_t thread_id,
+ uint32_t *pir, uint32_t *tir)
+{
+ if (pir) {
+ if (chip->nr_threads == 8) {
+ *pir = (chip->chip_id << 8) | ((core_id / 4) << 4) |
+ ((core_id % 2) << 3) | thread_id;
+ } else {
+ *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id;
+ }
+ }
+ if (tir) {
+ *tir = thread_id;
}
}
@@ -1370,8 +1392,11 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
int core_hwid = CPU_CORE(pnv_core)->core_id;
for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
- uint32_t pir = pcc->chip_pir(chip, core_hwid, j);
- PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
+ uint32_t pir;
+ PnvICPState *icp;
+
+ pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL);
+ icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
&icp->mmio);
@@ -1483,7 +1508,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
k->cores_mask = POWER8E_CORE_MASK;
k->num_phbs = 3;
- k->chip_pir = pnv_chip_pir_p8;
+ k->get_pir_tir = pnv_get_pir_tir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
@@ -1507,7 +1532,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 3;
- k->chip_pir = pnv_chip_pir_p8;
+ k->get_pir_tir = pnv_get_pir_tir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
@@ -1531,7 +1556,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 4;
- k->chip_pir = pnv_chip_pir_p8;
+ k->get_pir_tir = pnv_get_pir_tir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
@@ -1814,7 +1839,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
k->cores_mask = POWER9_CORE_MASK;
- k->chip_pir = pnv_chip_pir_p9;
+ k->get_pir_tir = pnv_get_pir_tir_p9;
k->intc_create = pnv_chip_power9_intc_create;
k->intc_reset = pnv_chip_power9_intc_reset;
k->intc_destroy = pnv_chip_power9_intc_destroy;
@@ -2136,7 +2161,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
k->cores_mask = POWER10_CORE_MASK;
- k->chip_pir = pnv_chip_pir_p10;
+ k->get_pir_tir = pnv_get_pir_tir_p10;
k->intc_create = pnv_chip_power10_intc_create;
k->intc_reset = pnv_chip_power10_intc_reset;
k->intc_destroy = pnv_chip_power10_intc_destroy;
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 2da271ffb6..28ca61926d 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -227,8 +227,9 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
{
CPUPPCState *env = &cpu->env;
int core_hwid;
- ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
- ppc_spr_t *tir = &env->spr_cb[SPR_TIR];
+ ppc_spr_t *pir_spr = &env->spr_cb[SPR_PIR];
+ ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR];
+ uint32_t pir, tir;
Error *local_err = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
@@ -244,8 +245,9 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort);
- tir->default_value = thread_index;
- pir->default_value = pcc->chip_pir(pc->chip, core_hwid, thread_index);
+ pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir);
+ pir_spr->default_value = pir;
+ tir_spr->default_value = tir;
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
--
2.45.1On 7/11/24 16:18, Nicholas Piggin wrote:
> The chip_pir chip class method allows the platform to set the PIR
> processor identification register. Extend this to a more general
> ID function which also allows the TIR to be set. This is in
> preparation for "big core", which is a more complicated topology
> of cores and threads.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> include/hw/ppc/pnv_chip.h | 4 +-
> hw/ppc/pnv.c | 85 +++++++++++++++++++++++++--------------
> hw/ppc/pnv_core.c | 10 +++--
> 3 files changed, 64 insertions(+), 35 deletions(-)
>
> diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
> index decfbc0ff7..1fca540eb1 100644
> --- a/include/hw/ppc/pnv_chip.h
> +++ b/include/hw/ppc/pnv_chip.h
> @@ -152,7 +152,9 @@ struct PnvChipClass {
>
> DeviceRealize parent_realize;
>
> - uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id);
> + /* Get PIR and TIR values for a CPU thread identified by core/thread id */
> + void (*get_pir_tir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id,
> + uint32_t *pir, uint32_t *tir);
> void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
> void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
> void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 4252bcd28d..b593a41f7c 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -154,7 +154,7 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
> char *nodename;
> int cpus_offset = get_cpus_node(fdt);
>
> - pir = pnv_cc->chip_pir(chip, pc->hwid, 0);
> + pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, NULL);
>
> nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
> offset = fdt_add_subnode(fdt, cpus_offset, nodename);
> @@ -236,7 +236,8 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
>
> /* Build interrupt servers properties */
> for (i = 0; i < smt_threads; i++) {
> - servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i));
> + pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
> + servers_prop[i] = cpu_to_be32(pir);
> }
> _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
> servers_prop, sizeof(*servers_prop) * smt_threads)));
> @@ -248,14 +249,17 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid,
> uint32_t nr_threads)
> {
> PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> - uint32_t pir = pcc->chip_pir(chip, hwid, 0);
> - uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
> + uint32_t pir;
> + uint64_t addr;
> char *name;
> const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
> uint32_t irange[2], i, rsize;
> uint64_t *reg;
> int offset;
>
> + pcc->get_pir_tir(chip, hwid, 0, &pir, NULL);
> + addr = PNV_ICP_BASE(chip) | (pir << 12);
> +
> irange[0] = cpu_to_be32(pir);
> irange[1] = cpu_to_be32(nr_threads);
>
> @@ -1106,10 +1110,16 @@ static void pnv_init(MachineState *machine)
> * 25:28 Core number
> * 29:31 Thread ID
> */
> -static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id,
> - uint32_t thread_id)
> +static void pnv_get_pir_tir_p8(PnvChip *chip,
> + uint32_t core_id, uint32_t thread_id,
> + uint32_t *pir, uint32_t *tir)
> {
> - return (chip->chip_id << 7) | (core_id << 3) | thread_id;
> + if (pir) {
> + *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id;
> + }
> + if (tir) {
> + *tir = thread_id;
> + }
> }
>
> static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
> @@ -1161,14 +1171,20 @@ static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
> *
> * We only care about the lower bits. uint32_t is fine for the moment.
> */
> -static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id,
> - uint32_t thread_id)
> -{
> - if (chip->nr_threads == 8) {
> - return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) |
> - (thread_id >> 1);
> - } else {
> - return (chip->chip_id << 8) | (core_id << 2) | thread_id;
> +static void pnv_get_pir_tir_p9(PnvChip *chip,
> + uint32_t core_id, uint32_t thread_id,
> + uint32_t *pir, uint32_t *tir)
> +{
> + if (pir) {
> + if (chip->nr_threads == 8) {
> + *pir = (chip->chip_id << 8) | ((thread_id & 1) << 2) |
> + (core_id << 3) | (thread_id >> 1);
> + } else {
> + *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id;
> + }
> + }
> + if (tir) {
> + *tir = thread_id;
> }
> }
>
> @@ -1183,14 +1199,20 @@ static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id,
> *
> * We only care about the lower bits. uint32_t is fine for the moment.
> */
> -static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id,
> - uint32_t thread_id)
> -{
> - if (chip->nr_threads == 8) {
> - return (chip->chip_id << 8) | ((core_id / 4) << 4) |
> - ((core_id % 2) << 3) | thread_id;
> - } else {
> - return (chip->chip_id << 8) | (core_id << 2) | thread_id;
> +static void pnv_get_pir_tir_p10(PnvChip *chip,
> + uint32_t core_id, uint32_t thread_id,
> + uint32_t *pir, uint32_t *tir)
> +{
> + if (pir) {
> + if (chip->nr_threads == 8) {
> + *pir = (chip->chip_id << 8) | ((core_id / 4) << 4) |
> + ((core_id % 2) << 3) | thread_id;
> + } else {
> + *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id;
> + }
> + }
> + if (tir) {
> + *tir = thread_id;
> }
> }
>
> @@ -1370,8 +1392,11 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
> int core_hwid = CPU_CORE(pnv_core)->core_id;
>
> for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
> - uint32_t pir = pcc->chip_pir(chip, core_hwid, j);
> - PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
> + uint32_t pir;
> + PnvICPState *icp;
> +
> + pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL);
> + icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
>
> memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
> &icp->mmio);
> @@ -1483,7 +1508,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
> k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
> k->cores_mask = POWER8E_CORE_MASK;
> k->num_phbs = 3;
> - k->chip_pir = pnv_chip_pir_p8;
> + k->get_pir_tir = pnv_get_pir_tir_p8;
> k->intc_create = pnv_chip_power8_intc_create;
> k->intc_reset = pnv_chip_power8_intc_reset;
> k->intc_destroy = pnv_chip_power8_intc_destroy;
> @@ -1507,7 +1532,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
> k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
> k->cores_mask = POWER8_CORE_MASK;
> k->num_phbs = 3;
> - k->chip_pir = pnv_chip_pir_p8;
> + k->get_pir_tir = pnv_get_pir_tir_p8;
> k->intc_create = pnv_chip_power8_intc_create;
> k->intc_reset = pnv_chip_power8_intc_reset;
> k->intc_destroy = pnv_chip_power8_intc_destroy;
> @@ -1531,7 +1556,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
> k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
> k->cores_mask = POWER8_CORE_MASK;
> k->num_phbs = 4;
> - k->chip_pir = pnv_chip_pir_p8;
> + k->get_pir_tir = pnv_get_pir_tir_p8;
> k->intc_create = pnv_chip_power8_intc_create;
> k->intc_reset = pnv_chip_power8_intc_reset;
> k->intc_destroy = pnv_chip_power8_intc_destroy;
> @@ -1814,7 +1839,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
>
> k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
> k->cores_mask = POWER9_CORE_MASK;
> - k->chip_pir = pnv_chip_pir_p9;
> + k->get_pir_tir = pnv_get_pir_tir_p9;
> k->intc_create = pnv_chip_power9_intc_create;
> k->intc_reset = pnv_chip_power9_intc_reset;
> k->intc_destroy = pnv_chip_power9_intc_destroy;
> @@ -2136,7 +2161,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
>
> k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
> k->cores_mask = POWER10_CORE_MASK;
> - k->chip_pir = pnv_chip_pir_p10;
> + k->get_pir_tir = pnv_get_pir_tir_p10;
> k->intc_create = pnv_chip_power10_intc_create;
> k->intc_reset = pnv_chip_power10_intc_reset;
> k->intc_destroy = pnv_chip_power10_intc_destroy;
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 2da271ffb6..28ca61926d 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -227,8 +227,9 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
> {
> CPUPPCState *env = &cpu->env;
> int core_hwid;
> - ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
> - ppc_spr_t *tir = &env->spr_cb[SPR_TIR];
> + ppc_spr_t *pir_spr = &env->spr_cb[SPR_PIR];
> + ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR];
> + uint32_t pir, tir;
> Error *local_err = NULL;
> PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
>
> @@ -244,8 +245,9 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
>
> core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort);
>
> - tir->default_value = thread_index;
> - pir->default_value = pcc->chip_pir(pc->chip, core_hwid, thread_index);
> + pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir);
> + pir_spr->default_value = pir;
> + tir_spr->default_value = tir;
>
> /* Set time-base frequency to 512 MHz */
> cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
© 2016 - 2024 Red Hat, Inc.