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Thu, 11 Jul 2024 07:19:28 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Harsh Prateek Bora , qemu-devel@nongnu.org Subject: [PATCH 07/18] ppc/pnv: Extend chip_pir class method to TIR as well Date: Fri, 12 Jul 2024 00:18:39 +1000 Message-ID: <20240711141851.406677-8-npiggin@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240711141851.406677-1-npiggin@gmail.com> References: <20240711141851.406677-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=npiggin@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720707712919116600 Content-Type: text/plain; charset="utf-8" The chip_pir chip class method allows the platform to set the PIR processor identification register. Extend this to a more general ID function which also allows the TIR to be set. This is in preparation for "big core", which is a more complicated topology of cores and threads. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_chip.h | 4 +- hw/ppc/pnv.c | 85 +++++++++++++++++++++++++-------------- hw/ppc/pnv_core.c | 10 +++-- 3 files changed, 64 insertions(+), 35 deletions(-) diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index decfbc0ff7..1fca540eb1 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -152,7 +152,9 @@ struct PnvChipClass { =20 DeviceRealize parent_realize; =20 - uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_= id); + /* Get PIR and TIR values for a CPU thread identified by core/thread i= d */ + void (*get_pir_tir)(PnvChip *chip, uint32_t core_id, uint32_t thread_i= d, + uint32_t *pir, uint32_t *tir); void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 4252bcd28d..b593a41f7c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -154,7 +154,7 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void= *fdt) char *nodename; int cpus_offset =3D get_cpus_node(fdt); =20 - pir =3D pnv_cc->chip_pir(chip, pc->hwid, 0); + pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, NULL); =20 nodename =3D g_strdup_printf("%s@%x", dc->fw_name, pir); offset =3D fdt_add_subnode(fdt, cpus_offset, nodename); @@ -236,7 +236,8 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void= *fdt) =20 /* Build interrupt servers properties */ for (i =3D 0; i < smt_threads; i++) { - servers_prop[i] =3D cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i= )); + pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); + servers_prop[i] =3D cpu_to_be32(pir); } _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", servers_prop, sizeof(*servers_prop) * smt_threads))= ); @@ -248,14 +249,17 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint= 32_t hwid, uint32_t nr_threads) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - uint32_t pir =3D pcc->chip_pir(chip, hwid, 0); - uint64_t addr =3D PNV_ICP_BASE(chip) | (pir << 12); + uint32_t pir; + uint64_t addr; char *name; const char compat[] =3D "IBM,power8-icp\0IBM,ppc-xicp"; uint32_t irange[2], i, rsize; uint64_t *reg; int offset; =20 + pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); + addr =3D PNV_ICP_BASE(chip) | (pir << 12); + irange[0] =3D cpu_to_be32(pir); irange[1] =3D cpu_to_be32(nr_threads); =20 @@ -1106,10 +1110,16 @@ static void pnv_init(MachineState *machine) * 25:28 Core number * 29:31 Thread ID */ -static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, - uint32_t thread_id) +static void pnv_get_pir_tir_p8(PnvChip *chip, + uint32_t core_id, uint32_t thread_id, + uint32_t *pir, uint32_t *tir) { - return (chip->chip_id << 7) | (core_id << 3) | thread_id; + if (pir) { + *pir =3D (chip->chip_id << 7) | (core_id << 3) | thread_id; + } + if (tir) { + *tir =3D thread_id; + } } =20 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, @@ -1161,14 +1171,20 @@ static void pnv_chip_power8_intc_print_info(PnvChip= *chip, PowerPCCPU *cpu, * * We only care about the lower bits. uint32_t is fine for the moment. */ -static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, - uint32_t thread_id) -{ - if (chip->nr_threads =3D=3D 8) { - return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id <<= 3) | - (thread_id >> 1); - } else { - return (chip->chip_id << 8) | (core_id << 2) | thread_id; +static void pnv_get_pir_tir_p9(PnvChip *chip, + uint32_t core_id, uint32_t thread_id, + uint32_t *pir, uint32_t *tir) +{ + if (pir) { + if (chip->nr_threads =3D=3D 8) { + *pir =3D (chip->chip_id << 8) | ((thread_id & 1) << 2) | + (core_id << 3) | (thread_id >> 1); + } else { + *pir =3D (chip->chip_id << 8) | (core_id << 2) | thread_id; + } + } + if (tir) { + *tir =3D thread_id; } } =20 @@ -1183,14 +1199,20 @@ static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint= 32_t core_id, * * We only care about the lower bits. uint32_t is fine for the moment. */ -static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, - uint32_t thread_id) -{ - if (chip->nr_threads =3D=3D 8) { - return (chip->chip_id << 8) | ((core_id / 4) << 4) | - ((core_id % 2) << 3) | thread_id; - } else { - return (chip->chip_id << 8) | (core_id << 2) | thread_id; +static void pnv_get_pir_tir_p10(PnvChip *chip, + uint32_t core_id, uint32_t thread_id, + uint32_t *pir, uint32_t *tir) +{ + if (pir) { + if (chip->nr_threads =3D=3D 8) { + *pir =3D (chip->chip_id << 8) | ((core_id / 4) << 4) | + ((core_id % 2) << 3) | thread_id; + } else { + *pir =3D (chip->chip_id << 8) | (core_id << 2) | thread_id; + } + } + if (tir) { + *tir =3D thread_id; } } =20 @@ -1370,8 +1392,11 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Er= ror **errp) int core_hwid =3D CPU_CORE(pnv_core)->core_id; =20 for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { - uint32_t pir =3D pcc->chip_pir(chip, core_hwid, j); - PnvICPState *icp =3D PNV_ICP(xics_icp_get(chip8->xics, pir)); + uint32_t pir; + PnvICPState *icp; + + pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); + icp =3D PNV_ICP(xics_icp_get(chip8->xics, pir)); =20 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, &icp->mmio); @@ -1483,7 +1508,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; k->num_phbs =3D 3; - k->chip_pir =3D pnv_chip_pir_p8; + k->get_pir_tir =3D pnv_get_pir_tir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; @@ -1507,7 +1532,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->num_phbs =3D 3; - k->chip_pir =3D pnv_chip_pir_p8; + k->get_pir_tir =3D pnv_get_pir_tir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; @@ -1531,7 +1556,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->num_phbs =3D 4; - k->chip_pir =3D pnv_chip_pir_p8; + k->get_pir_tir =3D pnv_get_pir_tir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; @@ -1814,7 +1839,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) =20 k->chip_cfam_id =3D 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ k->cores_mask =3D POWER9_CORE_MASK; - k->chip_pir =3D pnv_chip_pir_p9; + k->get_pir_tir =3D pnv_get_pir_tir_p9; k->intc_create =3D pnv_chip_power9_intc_create; k->intc_reset =3D pnv_chip_power9_intc_reset; k->intc_destroy =3D pnv_chip_power9_intc_destroy; @@ -2136,7 +2161,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) =20 k->chip_cfam_id =3D 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ k->cores_mask =3D POWER10_CORE_MASK; - k->chip_pir =3D pnv_chip_pir_p10; + k->get_pir_tir =3D pnv_get_pir_tir_p10; k->intc_create =3D pnv_chip_power10_intc_create; k->intc_reset =3D pnv_chip_power10_intc_reset; k->intc_destroy =3D pnv_chip_power10_intc_destroy; diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 2da271ffb6..28ca61926d 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -227,8 +227,9 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCP= U *cpu, Error **errp, { CPUPPCState *env =3D &cpu->env; int core_hwid; - ppc_spr_t *pir =3D &env->spr_cb[SPR_PIR]; - ppc_spr_t *tir =3D &env->spr_cb[SPR_TIR]; + ppc_spr_t *pir_spr =3D &env->spr_cb[SPR_PIR]; + ppc_spr_t *tir_spr =3D &env->spr_cb[SPR_TIR]; + uint32_t pir, tir; Error *local_err =3D NULL; PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(pc->chip); =20 @@ -244,8 +245,9 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCP= U *cpu, Error **errp, =20 core_hwid =3D object_property_get_uint(OBJECT(pc), "hwid", &error_abor= t); =20 - tir->default_value =3D thread_index; - pir->default_value =3D pcc->chip_pir(pc->chip, core_hwid, thread_index= ); + pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir); + pir_spr->default_value =3D pir; + tir_spr->default_value =3D tir; =20 /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); --=20 2.45.1