Series comparison

-[PULL 00/28] riscv-to-apply queue
+[PULL v2 00/42] riscv-to-apply queue
-The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
+The following changes since commit d45a5270d075ea589f0b0ddcf963a5fea1f500ac:
-  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
+  Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging (2021-05-05 13:52:00 +0100)
 are available in the Git repository at:
-  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210506
-for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
+for you to fetch changes up to d9e1a4683bc52ff218dcc133f73017bc4c496346:
-  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
+  target/riscv: Fix the RV64H decode comment (2021-05-06 08:59:59 +1000)
 ----------------------------------------------------------------
-RISC-V PR for 9.1
+A large collection of RISC-V fixes, improvements and features
-* APLICs add child earlier than realize
+ - Clenaup some left over v1.9 code
-* Fix exposure of Zkr
+ - Documentation improvements
-* Raise exceptions on wrs.nto
+ - Support for the shakti_c machine
-* Implement SBI debug console (DBCN) calls for KVM
+ - Internal cleanup of the CSR accesses
-* Support 64-bit addresses for initrd
+ - Updates to the OpenTitan platform
-* Change RISCV_EXCP_SEMIHOST exception number to 63
+ - Support for the virtio-vga
-* Tolerate KVM disable ext errors
+ - Fix for the saturate subtract in vector extensions
-* Set tval in breakpoints
+ - Experimental support for the ePMP spec
-* Add support for Zve32x extension
+ - A range of other internal code cleanups and bug fixes
 * Add support for Zve64x extension
 * Relax vector register check in RISCV gdbstub
 * Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Alexei Filippov (1):
+Alexander Wagner (1):
-      target/riscv: do not set mtval2 for non guest-page faults
+      hw/riscv: Fix OT IBEX reset vector
-Alistair Francis (2):
+Alistair Francis (22):
-      target/riscv: rvzicbo: Fixup CBO extension register calculation
+      target/riscv: Convert the RISC-V exceptions to an enum
-      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
+      target/riscv: Use the RISCVException enum for CSR predicates
       target/riscv: Fix 32-bit HS mode access permissions
       target/riscv: Use the RISCVException enum for CSR operations
       target/riscv: Use RISCVException enum for CSR access
       MAINTAINERS: Update the RISC-V CPU Maintainers
       hw/opentitan: Update the interrupt layout
       hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
       target/riscv: Fix the PMP is locked check when using TOR
       target/riscv: Add the ePMP feature
       target/riscv/pmp: Remove outdated comment
       target/riscv: Add ePMP support for the Ibex CPU
       target/riscv: Remove the hardcoded RVXLEN macro
       target/riscv: Remove the hardcoded SSTATUS_SD macro
       target/riscv: Remove the hardcoded HGATP_MODE macro
       target/riscv: Remove the hardcoded MSTATUS_SD macro
       target/riscv: Remove the hardcoded SATP_MODE macro
       target/riscv: Remove the unused HSTATUS_WPRI macro
       target/riscv: Remove an unused CASE_OP_32_64 macro
       target/riscv: Consolidate RV32/64 32-bit instructions
       target/riscv: Consolidate RV32/64 16-bit instructions
       target/riscv: Fix the RV64H decode comment
-Andrew Jones (2):
+Atish Patra (1):
-      target/riscv/kvm: Fix exposure of Zkr
+      target/riscv: Remove privilege v1.9 specific CSR related code
       target/riscv: Raise exceptions on wrs.nto
-Cheng Yang (1):
+Axel Heider (1):
-      hw/riscv/boot.c: Support 64-bit address for initrd
+      docs/system/generic-loader.rst: Fix style
-Christoph Müllner (1):
+Bin Meng (1):
-      riscv: thead: Add th.sxstatus CSR emulation
+      hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
-Clément Léger (1):
+Dylan Jhong (1):
-      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
+      target/riscv: Align the data type of reset vector address
-Daniel Henrique Barboza (6):
+Emmanuel Blot (2):
-      target/riscv/kvm: implement SBI debug console (DBCN) calls
+      target/riscv: fix exception index on instruction access fault
-      target/riscv/kvm: tolerate KVM disable ext errors
+      target/riscv: fix a typo with interrupt names
       target/riscv/debug: set tval=pc in breakpoint exceptions
       trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
       target/riscv: prioritize pmp errors in raise_mmu_exception()
       riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
-Huang Tao (2):
+Frank Chang (2):
-      target/riscv: Fix the element agnostic function problem
+      target/riscv: fix vrgather macro index variable type bug
-      target/riscv: Implement dynamic establishment of custom decoder
+      fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
-Jason Chien (3):
+Hou Weiying (4):
-      target/riscv: Add support for Zve32x extension
+      target/riscv: Define ePMP mseccfg
-      target/riscv: Add support for Zve64x extension
+      target/riscv: Add ePMP CSR access functions
-      target/riscv: Relax vector register check in RISCV gdbstub
+      target/riscv: Implementation of enhanced PMP (ePMP)
       target/riscv: Add a config option for ePMP
-Max Chou (4):
+Jade Fink (1):
-      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+      riscv: don't look at SUM when accessing memory from a debugger context
       target/riscv: rvv: Check single width operator for vector fp widen instructions
       target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
       target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
-Rob Bradford (1):
+LIU Zhiwei (1):
-      target/riscv: Remove experimental prefix from "B" extension
+      target/riscv: Fixup saturate subtract function
-Yangyu Chen (1):
+Vijai Kumar K (5):
-      target/riscv/cpu.c: fix Zvkb extension config
+      target/riscv: Add Shakti C class CPU
       riscv: Add initial support for Shakti C machine
       hw/char: Add Shakti UART emulation
       hw/riscv: Connect Shakti UART to Shakti platform
       docs: Add documentation for shakti_c machine
-Yong-Xuan Wang (1):
+ docs/system/generic-loader.rst              |   9 +-
-      target/riscv/kvm.c: Fix the hart bit setting of AIA
+ docs/system/riscv/shakti-c.rst              |  82 +++
  docs/system/target-riscv.rst                |   1 +
  default-configs/devices/riscv64-softmmu.mak |   1 +
  include/hw/char/shakti_uart.h               |  74 +++
  include/hw/riscv/opentitan.h                |  16 +-
  include/hw/riscv/shakti_c.h                 |  75 +++
  target/riscv/cpu.h                          |  42 +-
  target/riscv/cpu_bits.h                     | 114 +---
  target/riscv/helper.h                       |  18 +-
  target/riscv/pmp.h                          |  14 +
  target/riscv/insn16-32.decode               |  28 -
  target/riscv/insn16-64.decode               |  36 --
  target/riscv/insn16.decode                  |  30 +
  target/riscv/insn32-64.decode               |  88 ---
  target/riscv/insn32.decode                  |  67 ++-
  hw/char/shakti_uart.c                       | 185 +++++++
  hw/intc/ibex_plic.c                         |  20 +-
  hw/riscv/opentitan.c                        |  10 +-
  hw/riscv/shakti_c.c                         | 178 ++++++
  hw/riscv/sifive_e.c                         |   2 +-
  target/riscv/cpu.c                          |  26 +-
  target/riscv/cpu_helper.c                   |  88 ++-
  target/riscv/csr.c                          | 824 +++++++++++++++++-----------
  target/riscv/fpu_helper.c                   |  16 +-
  target/riscv/gdbstub.c                      |   8 +-
  target/riscv/machine.c                      |   8 +-
  target/riscv/monitor.c                      |  22 +-
  target/riscv/op_helper.c                    |  18 +-
  target/riscv/pmp.c                          | 218 +++++++-
  target/riscv/translate.c                    |  38 +-
  target/riscv/vector_helper.c                |  18 +-
  fpu/softfloat-specialize.c.inc              |   6 +
  target/riscv/insn_trans/trans_rva.c.inc     |  14 +-
  target/riscv/insn_trans/trans_rvd.c.inc     |  17 +-
  target/riscv/insn_trans/trans_rvf.c.inc     |   6 +-
  target/riscv/insn_trans/trans_rvh.c.inc     |   8 +-
  target/riscv/insn_trans/trans_rvi.c.inc     |  22 +-
  target/riscv/insn_trans/trans_rvm.c.inc     |  12 +-
  target/riscv/insn_trans/trans_rvv.c.inc     |  39 +-
  MAINTAINERS                                 |  14 +-
  hw/char/meson.build                         |   1 +
  hw/char/trace-events                        |   4 +
  hw/riscv/Kconfig                            |  11 +
  hw/riscv/meson.build                        |   1 +
  target/riscv/meson.build                    |  13 +-
  target/riscv/trace-events                   |   3 +
 files changed, 1756 insertions(+), 789 deletions(-)
  create mode 100644 docs/system/riscv/shakti-c.rst
  create mode 100644 include/hw/char/shakti_uart.h
  create mode 100644 include/hw/riscv/shakti_c.h
  delete mode 100644 target/riscv/insn16-32.decode
  delete mode 100644 target/riscv/insn16-64.decode
  delete mode 100644 target/riscv/insn32-64.decode
  create mode 100644 hw/char/shakti_uart.c
  create mode 100644 hw/riscv/shakti_c.c
-Yu-Ming Chang (1):
-      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
-yang.zhang (1):
-      hw/intc/riscv_aplic: APLICs should add child earlier than realize
- MAINTAINERS                                    |   1 +
- target/riscv/cpu.h                             |  11 ++
- target/riscv/cpu_bits.h                        |   2 +-
- target/riscv/cpu_cfg.h                         |   2 +
- target/riscv/helper.h                          |   1 +
- target/riscv/sbi_ecall_interface.h             |  17 +++
- target/riscv/tcg/tcg-cpu.h                     |  15 +++
- disas/riscv.c                                  |  65 +++++++++-
- hw/intc/riscv_aplic.c                          |   8 +-
- hw/riscv/boot.c                                |   4 +-
- target/riscv/cpu.c                             |  10 +-
- target/riscv/cpu_helper.c                      |  37 +++---
- target/riscv/csr.c                             |  71 +++++++++--
- target/riscv/debug.c                           |   3 +
- target/riscv/gdbstub.c                         |   8 +-
- target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
- target/riscv/op_helper.c                       |  17 ++-
- target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
- target/riscv/th_csr.c                          |  79 +++++++++++++
- target/riscv/translate.c                       |  31 +++--
- target/riscv/vector_internals.c                |  22 ++++
- target/riscv/insn_trans/trans_privileged.c.inc |   2 +
- target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
- target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
- target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
- target/riscv/meson.build                       |   1 +
-files changed, 596 insertions(+), 109 deletions(-)
- create mode 100644 target/riscv/th_csr.c

-[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
+[PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code
-From: Huang Tao <eric.huang@linux.alibaba.com>
+From: Atish Patra <atish.patra@wdc.com>
-In this patch, we modify the decoder to be a freely composable data
+Qemu doesn't support RISC-V privilege specification v1.9. Remove the
-structure instead of a hardcoded one. It can be dynamically builded up
+remaining v1.9 specific references from the implementation.
-according to the extensions.
-This approach has several benefits:
+Signed-off-by: Atish Patra <atish.patra@wdc.com>
 . Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
 Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
 Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
 Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
+Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com>
 [Changes by AF:
  - Rebase on latest patches
  - Bump the vmstate_riscv_cpu version_id and minimum_version_id
  ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |  1 +
+ target/riscv/cpu.h        |  4 +---
- target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
+ target/riscv/cpu_bits.h   | 23 ---------------------
- target/riscv/cpu.c         |  1 +
+ target/riscv/cpu.c        |  2 +-
- target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
+ target/riscv/cpu_helper.c | 12 +++++------
- target/riscv/translate.c   | 31 +++++++++++++++----------------
+ target/riscv/csr.c        | 42 ++++++++++-----------------------------
-files changed, 47 insertions(+), 16 deletions(-)
+ target/riscv/machine.c    |  8 +++-----
  target/riscv/translate.c  |  4 ++--
 files changed, 23 insertions(+), 72 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
+@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
-     uint32_t pmu_avail_ctrs;
+     target_ulong mie;
-     /* Mapping of events to counters */
+     target_ulong mideleg;
-     GHashTable *pmu_event_ctr_map;
-+    const GPtrArray *decoders;
+-    target_ulong sptbr;  /* until: priv-1.9.1 */
- };
+     target_ulong satp;   /* since: priv-1.10.0 */
+-    target_ulong sbadaddr;
- /**
+-    target_ulong mbadaddr;
-diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
++    target_ulong stval;
-index XXXXXXX..XXXXXXX 100644
+     target_ulong medeleg;
---- a/target/riscv/tcg/tcg-cpu.h
-+++ b/target/riscv/tcg/tcg-cpu.h
+     target_ulong stvec;
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
- void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
+index XXXXXXX..XXXXXXX 100644
- bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
-+struct DisasContext;
+@@ -XXX,XX +XXX,XX @@
-+struct RISCVCPUConfig;
+ /* 32-bit only */
-+typedef struct RISCVDecoder {
+ #define CSR_MSTATUSH        0x310
-+    bool (*guard_func)(const struct RISCVCPUConfig *);
-+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+-/* Legacy Counter Setup (priv v1.9.1) */
-+} RISCVDecoder;
+-/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
-+
+-#define CSR_MUCOUNTEREN     0x320
-+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+-#define CSR_MSCOUNTEREN     0x321
-+
+-#define CSR_MHCOUNTEREN     0x322
-+extern const size_t decoder_table_size;
+-
-+
+ /* Machine Trap Handling */
-+extern const RISCVDecoder decoder_table[];
+ #define CSR_MSCRATCH        0x340
-+
+ #define CSR_MEPC            0x341
-+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+@@ -XXX,XX +XXX,XX @@
-+
+ #define CSR_MTVAL           0x343
- #endif
+ #define CSR_MIP             0x344
 -/* Legacy Machine Trap Handling (priv v1.9.1) */
 -#define CSR_MBADADDR        0x343
 -
  /* Supervisor Trap Setup */
  #define CSR_SSTATUS         0x100
  #define CSR_SEDELEG         0x102
@@ -XXX,XX +XXX,XX @@
  #define CSR_STVAL           0x143
  #define CSR_SIP             0x144
 -/* Legacy Supervisor Trap Handling (priv v1.9.1) */
 -#define CSR_SBADADDR        0x143
 -
  /* Supervisor Protection and Translation */
  #define CSR_SPTBR           0x180
  #define CSR_SATP            0x180
@@ -XXX,XX +XXX,XX @@
  #define CSR_MHPMCOUNTER30H  0xb9e
  #define CSR_MHPMCOUNTER31H  0xb9f
 -/* Legacy Machine Protection and Translation (priv v1.9.1) */
 -#define CSR_MBASE           0x380
 -#define CSR_MBOUND          0x381
 -#define CSR_MIBASE          0x382
 -#define CSR_MIBOUND         0x383
 -#define CSR_MDBASE          0x384
 -#define CSR_MDBOUND         0x385
 -
  /* mstatus CSR bits */
  #define MSTATUS_UIE         0x00000001
  #define MSTATUS_SIE         0x00000002
@@ -XXX,XX +XXX,XX @@
  #define MSTATUS_FS          0x00006000
  #define MSTATUS_XS          0x00018000
  #define MSTATUS_MPRV        0x00020000
 -#define MSTATUS_PUM         0x00040000 /* until: priv-1.9.1 */
  #define MSTATUS_SUM         0x00040000 /* since: priv-1.10 */
  #define MSTATUS_MXR         0x00080000
 -#define MSTATUS_VM          0x1F000000 /* until: priv-1.9.1 */
  #define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */
  #define MSTATUS_TW          0x00200000 /* since: priv-1.10 */
  #define MSTATUS_TSR         0x00400000 /* since: priv-1.10 */
@@ -XXX,XX +XXX,XX @@
  #define SSTATUS_SPP         0x00000100
  #define SSTATUS_FS          0x00006000
  #define SSTATUS_XS          0x00018000
 -#define SSTATUS_PUM         0x00040000 /* until: priv-1.9.1 */
  #define SSTATUS_SUM         0x00040000 /* since: priv-1.10 */
  #define SSTATUS_MXR         0x00080000
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-             error_propagate(errp, local_err);
+         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
              return;
          }
 +        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
      } else if (kvm_enabled()) {
          riscv_kvm_cpu_finalize_features(cpu, &local_err);
          if (local_err != NULL) {
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
      }
- }
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
-+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
-+{
+     if (riscv_has_ext(env, RVH)) {
-+    GPtrArray *dynamic_decoders;
+         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
-+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
-+    for (size_t i = 0; i < decoder_table_size; ++i) {
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-+        if (decoder_table[i].guard_func &&
+index XXXXXXX..XXXXXXX 100644
-+            decoder_table[i].guard_func(&cpu->cfg)) {
+--- a/target/riscv/cpu_helper.c
-+            g_ptr_array_add(dynamic_decoders,
++++ b/target/riscv/cpu_helper.c
-+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
-+        }
+         env->vscause = env->scause;
-+    }
+         env->scause = env->scause_hs;
-+
-+    cpu->decoders = dynamic_decoders;
+-        env->vstval = env->sbadaddr;
-+}
+-        env->sbadaddr = env->stval_hs;
-+
++        env->vstval = env->stval;
- bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
++        env->stval = env->stval_hs;
- {
-     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
+         env->vsatp = env->satp;
          env->satp = env->satp_hs;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
          env->scause_hs = env->scause;
          env->scause = env->vscause;
 -        env->stval_hs = env->sbadaddr;
 -        env->sbadaddr = env->vstval;
 +        env->stval_hs = env->stval;
 +        env->stval = env->vstval;
          env->satp_hs = env->satp;
          env->satp = env->vsatp;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
          env->mstatus = s;
          env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
          env->sepc = env->pc;
 -        env->sbadaddr = tval;
 +        env->stval = tval;
          env->htval = htval;
          env->pc = (env->stvec >> 2 << 2) +
              ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
          env->mstatus = s;
          env->mcause = cause | ~(((target_ulong)-1) >> async);
          env->mepc = env->pc;
 -        env->mbadaddr = tval;
 +        env->mtval = tval;
          env->mtval2 = mtval2;
          env->pc = (env->mtvec >> 2 << 2) +
              ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 -static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 -{
 -    if (env->priv_ver < PRIV_VERSION_1_11_0) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 -    }
 -    *val = env->mcounteren;
 -    return 0;
 -}
 -
 -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 -static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 -{
 -    if (env->priv_ver < PRIV_VERSION_1_11_0) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 -    }
 -    env->mcounteren = val;
 -    return 0;
 -}
 -
  /* Machine Trap Handling */
  static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
  {
@@ -XXX,XX +XXX,XX @@ static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 -static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 +static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
  {
 -    *val = env->mbadaddr;
 +    *val = env->mtval;
      return 0;
  }
 -static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 +static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
  {
 -    env->mbadaddr = val;
 +    env->mtval = val;
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
      return 0;
  }
 -static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 +static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
  {
 -    *val = env->sbadaddr;
 +    *val = env->stval;
      return 0;
  }
 -static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 +static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
  {
 -    env->sbadaddr = val;
 +    env->stval = val;
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
 -    [CSR_MSCOUNTEREN] = { "msounteren", any,   read_mscounteren, write_mscounteren },
 -
      /* Machine Trap Handling */
      [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch },
      [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
      [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
 -    [CSR_MBADADDR] = { "mbadaddr", any,  read_mbadaddr, write_mbadaddr },
 +    [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
      [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
      /* Supervisor Trap Setup */
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
      [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
      [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
 -    [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
 +    [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
      [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
      /* Supervisor Protection and Translation */
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
  const VMStateDescription vmstate_riscv_cpu = {
      .name = "cpu",
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 +    .version_id = 2,
 +    .minimum_version_id = 2,
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
          VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
          VMSTATE_UINT32(env.miclaim, RISCVCPU),
          VMSTATE_UINTTL(env.mie, RISCVCPU),
          VMSTATE_UINTTL(env.mideleg, RISCVCPU),
 -        VMSTATE_UINTTL(env.sptbr, RISCVCPU),
          VMSTATE_UINTTL(env.satp, RISCVCPU),
 -        VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
 -        VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
 +        VMSTATE_UINTTL(env.stval, RISCVCPU),
          VMSTATE_UINTTL(env.medeleg, RISCVCPU),
          VMSTATE_UINTTL(env.stvec, RISCVCPU),
          VMSTATE_UINTTL(env.sepc, RISCVCPU),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void generate_exception(DisasContext *ctx, int excp)
- #include "exec/helper-info.c.inc"
+     ctx->base.is_jmp = DISAS_NORETURN;
- #undef  HELPER_H
+ }
-+#include "tcg/tcg-cpu.h"
+-static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
-+
++static void generate_exception_mtval(DisasContext *ctx, int excp)
- /* global register indices */
+ {
- static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
+     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
+     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
-     /* FRM is known to contain a valid value. */
-     bool frm_valid;
+ static void gen_exception_inst_addr_mis(DisasContext *ctx)
-     bool insn_start_updated;
+ {
-+    const GPtrArray *decoders;
+-    generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
- } DisasContext;
++    generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
+ }
- static inline bool has_ext(DisasContext *ctx, uint32_t ext)
-@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
+ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
      return (first_word & 3) == 3 ? 4 : 2;
  }
 +const RISCVDecoder decoder_table[] = {
 +    { always_true_p, decode_insn32 },
 +    { has_xthead_p, decode_xthead},
 +    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
 +};
 +
 +const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
 +
  static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
  {
 -    /*
 -     * A table with predicate (i.e., guard) functions and decoder functions
 -     * that are tested in-order until a decoder matches onto the opcode.
 -     */
 -    static const struct {
 -        bool (*guard_func)(const RISCVCPUConfig *);
 -        bool (*decode_func)(DisasContext *, uint32_t);
 -    } decoders[] = {
 -        { always_true_p,  decode_insn32 },
 -        { has_xthead_p, decode_xthead },
 -        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
 -    };
 -
      ctx->virt_inst_excp = false;
      ctx->cur_insn_len = insn_len(opcode);
      /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                               ctx->base.pc_next + 2));
          ctx->opcode = opcode32;
 -        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
 -            if (decoders[i].guard_func(ctx->cfg_ptr) &&
 -                decoders[i].decode_func(ctx, opcode32)) {
 +        for (guint i = 0; i < ctx->decoders->len; ++i) {
 +            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
 +            if (func(ctx, opcode32)) {
                  return;
              }
          }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
      ctx->zero = tcg_constant_tl(0);
      ctx->virt_inst_excp = false;
 +    ctx->decoders = cpu->decoders;
  }
  static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 --
-.45.1
+.31.1

-New patch
+[PULL v2 02/42] docs/system/generic-loader.rst: Fix style
+From: Axel Heider <axelheider@gmx.de>
+Fix style to have a proper description of the parameter 'force-raw'.
+Signed-off-by: Axel Heider <axelheider@gmx.de>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a659ac@gmx.de
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ docs/system/generic-loader.rst | 9 ++++++---
+file changed, 6 insertions(+), 3 deletions(-)
+diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/generic-loader.rst
++++ b/docs/system/generic-loader.rst
+@@ -XXX,XX +XXX,XX @@ shown below:
+   specified in the executable format header. This option should only
+   be used for the boot image. This will also cause the image to be
+   written to the specified CPU's address space. If not specified, the
+-  default is CPU 0. <force-raw> - Setting force-raw=on forces the file
+-  to be treated as a raw image. This can be used to load supported
+-  executable formats as if they were raw.
++  default is CPU 0.
++
++``<force-raw>``
++  Setting 'force-raw=on' forces the file to be treated as a raw image.
++  This can be used to load supported executable formats as if they
++  were raw.
+ All values are parsed using the standard QemuOpts parsing. This allows the user
+ to specify any values in any format supported. By default the values
+--
+.31.1

-[PULL 13/28] target/riscv: Fix the element agnostic function problem
+[PULL v2 03/42] target/riscv: Align the data type of reset vector address
-From: Huang Tao <eric.huang@linux.alibaba.com>
+From: Dylan Jhong <dylan@andestech.com>
-In RVV and vcrypto instructions, the masked and tail elements are set to 1s
+Use target_ulong to instead of uint64_t on reset vector address
-using vext_set_elems_1s function if the vma/vta bit is set. It is the element
+to adapt on both 32/64 machine.
 agnostic policy.
-However, this function can't deal the big endian situation. This patch fixes
+Signed-off-by: Dylan Jhong <dylan@andestech.com>
-the problem by adding handling of such case.
+Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210329034801.22667-1-dylan@andestech.com
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
+ target/riscv/cpu.c | 2 +-
-file changed, 22 insertions(+)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/vector_internals.c
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/vector_internals.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
+@@ -XXX,XX +XXX,XX @@ static void set_feature(CPURISCVState *env, int feature)
-     if (tot - cnt == 0) {
+     env->features |= (1ULL << feature);
          return ;
      }
 +
 +    if (HOST_BIG_ENDIAN) {
 +        /*
 +         * Deal the situation when the elements are insdie
 +         * only one uint64 block including setting the
 +         * masked-off element.
 +         */
 +        if (((tot - 1) ^ cnt) < 8) {
 +            memset(base + H1(tot - 1), -1, tot - cnt);
 +            return;
 +        }
 +        /*
 +         * Otherwise, at least cross two uint64_t blocks.
 +         * Set first unaligned block.
 +         */
 +        if (cnt % 8 != 0) {
 +            uint32_t j = ROUND_UP(cnt, 8);
 +            memset(base + H1(j - 1), -1, j - cnt);
 +            cnt = j;
 +        }
 +        /* Set other 64bit aligend blocks */
 +    }
      memset(base + cnt, -1, tot - cnt);
  }
+-static void set_resetvec(CPURISCVState *env, int resetvec)
++static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
+ {
+ #ifndef CONFIG_USER_ONLY
+     env->resetvec = resetvec;
 --
-.45.1
+.31.1

-New patch
+[PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
+From: Bin Meng <bmeng.cn@gmail.com>
+This was accidentally dropped before. Add it back.
+Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
+Reported-by: Emmanuel Blot <eblot.ml@gmail.com>
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210331103612.654261-1-bmeng.cn@gmail.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/sifive_e.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/sifive_e.c
++++ b/hw/riscv/sifive_e.c
+@@ -XXX,XX +XXX,XX @@
+ #include "sysemu/arch_init.h"
+ #include "sysemu/sysemu.h"
+-static MemMapEntry sifive_e_memmap[] = {
++static const MemMapEntry sifive_e_memmap[] = {
+     [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
+     [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
+     [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
+--
+.31.1

-[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
+[PULL v2 05/42] target/riscv: Add Shakti C class CPU
-From: Cheng Yang <yangcheng.work@foxmail.com>
+From: Vijai Kumar K <vijai@behindbytes.com>
-Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
+C-Class is a member of the SHAKTI family of processors from IIT-M.
 to set the address of initrd in FDT to support 64-bit address.
-Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
+It is an extremely configurable and commercial-grade 5-stage in-order
 core supporting the standard RV64GCSUN ISA extensions.
 Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
+Message-id: 20210401181457.73039-2-vijai@behindbytes.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/boot.c | 4 ++--
+ target/riscv/cpu.h | 1 +
-file changed, 2 insertions(+), 2 deletions(-)
+ target/riscv/cpu.c | 1 +
 files changed, 2 insertions(+)
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
+--- a/target/riscv/cpu.h
-+++ b/hw/riscv/boot.c
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+@@ -XXX,XX +XXX,XX @@
-     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
+ #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
-     if (fdt) {
+ #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
-         end = start + size;
+ #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
--        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
++#define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
--        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+ #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
-+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+ #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
-+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
+ #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
-     }
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
- }
+index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
      DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 +    DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
  #endif
  };
 --
-.45.1
+.31.1

-New patch
+[PULL v2 06/42] riscv: Add initial support for Shakti C machine
+From: Vijai Kumar K <vijai@behindbytes.com>
 Add support for emulating Shakti reference platform based on C-class
 running on arty-100T board.
 https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
 Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210401181457.73039-3-vijai@behindbytes.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  default-configs/devices/riscv64-softmmu.mak |   1 +
  include/hw/riscv/shakti_c.h                 |  73 +++++++++
  hw/riscv/shakti_c.c                         | 170 ++++++++++++++++++++
  MAINTAINERS                                 |   7 +
  hw/riscv/Kconfig                            |  10 ++
  hw/riscv/meson.build                        |   1 +
 files changed, 262 insertions(+)
  create mode 100644 include/hw/riscv/shakti_c.h
  create mode 100644 hw/riscv/shakti_c.c
 diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
 index XXXXXXX..XXXXXXX 100644
 --- a/default-configs/devices/riscv64-softmmu.mak
 +++ b/default-configs/devices/riscv64-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_SIFIVE_E=y
  CONFIG_SIFIVE_U=y
  CONFIG_RISCV_VIRT=y
  CONFIG_MICROCHIP_PFSOC=y
 +CONFIG_SHAKTI_C=y
 diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/riscv/shakti_c.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Shakti C-class SoC emulation
 + *
 + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef HW_SHAKTI_H
 +#define HW_SHAKTI_H
 +
 +#include "hw/riscv/riscv_hart.h"
 +#include "hw/boards.h"
 +
 +#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
 +#define RISCV_SHAKTI_SOC(obj) \
 +    OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
 +
 +typedef struct ShaktiCSoCState {
 +    /*< private >*/
 +    DeviceState parent_obj;
 +
 +    /*< public >*/
 +    RISCVHartArrayState cpus;
 +    DeviceState *plic;
 +    MemoryRegion rom;
 +
 +} ShaktiCSoCState;
 +
 +#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
 +#define RISCV_SHAKTI_MACHINE(obj) \
 +    OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
 +typedef struct ShaktiCMachineState {
 +    /*< private >*/
 +    MachineState parent_obj;
 +
 +    /*< public >*/
 +    ShaktiCSoCState soc;
 +} ShaktiCMachineState;
 +
 +enum {
 +    SHAKTI_C_ROM,
 +    SHAKTI_C_RAM,
 +    SHAKTI_C_UART,
 +    SHAKTI_C_GPIO,
 +    SHAKTI_C_PLIC,
 +    SHAKTI_C_CLINT,
 +    SHAKTI_C_I2C,
 +};
 +
 +#define SHAKTI_C_PLIC_HART_CONFIG "MS"
 +/* Including Interrupt ID 0 (no interrupt)*/
 +#define SHAKTI_C_PLIC_NUM_SOURCES 28
 +/* Excluding Priority 0 */
 +#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
 +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
 +#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
 +#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
 +#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
 +#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
 +#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
 +
 +#endif
 diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Shakti C-class SoC emulation
 + *
 + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/boards.h"
 +#include "hw/riscv/shakti_c.h"
 +#include "qapi/error.h"
 +#include "hw/intc/sifive_plic.h"
 +#include "hw/intc/sifive_clint.h"
 +#include "sysemu/sysemu.h"
 +#include "hw/qdev-properties.h"
 +#include "exec/address-spaces.h"
 +#include "hw/riscv/boot.h"
 +
 +
 +static const struct MemmapEntry {
 +    hwaddr base;
 +    hwaddr size;
 +} shakti_c_memmap[] = {
 +    [SHAKTI_C_ROM]   =  {  0x00001000,  0x2000   },
 +    [SHAKTI_C_RAM]   =  {  0x80000000,  0x0      },
 +    [SHAKTI_C_UART]  =  {  0x00011300,  0x00040  },
 +    [SHAKTI_C_GPIO]  =  {  0x020d0000,  0x00100  },
 +    [SHAKTI_C_PLIC]  =  {  0x0c000000,  0x20000  },
 +    [SHAKTI_C_CLINT] =  {  0x02000000,  0xc0000  },
 +    [SHAKTI_C_I2C]   =  {  0x20c00000,  0x00100  },
 +};
 +
 +static void shakti_c_machine_state_init(MachineState *mstate)
 +{
 +    ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
 +    MemoryRegion *system_memory = get_system_memory();
 +    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 +
 +    /* Allow only Shakti C CPU for this platform */
 +    if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
 +        error_report("This board can only be used with Shakti C CPU");
 +        exit(1);
 +    }
 +
 +    /* Initialize SoC */
 +    object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
 +                            TYPE_RISCV_SHAKTI_SOC);
 +    qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
 +
 +    /* register RAM */
 +    memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
 +                           mstate->ram_size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                shakti_c_memmap[SHAKTI_C_RAM].base,
 +                                main_mem);
 +
 +    /* ROM reset vector */
 +    riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
 +                              shakti_c_memmap[SHAKTI_C_RAM].base,
 +                              shakti_c_memmap[SHAKTI_C_ROM].base,
 +                              shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
 +                              NULL);
 +    riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].base,
 +                        NULL);
 +}
 +
 +static void shakti_c_machine_instance_init(Object *obj)
 +{
 +}
 +
 +static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
 +{
 +    MachineClass *mc = MACHINE_CLASS(klass);
 +    mc->desc = "RISC-V Board compatible with Shakti SDK";
 +    mc->init = shakti_c_machine_state_init;
 +    mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
 +}
 +
 +static const TypeInfo shakti_c_machine_type_info = {
 +    .name = TYPE_RISCV_SHAKTI_MACHINE,
 +    .parent = TYPE_MACHINE,
 +    .class_init = shakti_c_machine_class_init,
 +    .instance_init = shakti_c_machine_instance_init,
 +    .instance_size = sizeof(ShaktiCMachineState),
 +};
 +
 +static void shakti_c_machine_type_info_register(void)
 +{
 +    type_register_static(&shakti_c_machine_type_info);
 +}
 +type_init(shakti_c_machine_type_info_register)
 +
 +static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
 +{
 +    ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
 +    MemoryRegion *system_memory = get_system_memory();
 +
 +    sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
 +
 +    sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
 +        (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
 +        SHAKTI_C_PLIC_NUM_SOURCES,
 +        SHAKTI_C_PLIC_NUM_PRIORITIES,
 +        SHAKTI_C_PLIC_PRIORITY_BASE,
 +        SHAKTI_C_PLIC_PENDING_BASE,
 +        SHAKTI_C_PLIC_ENABLE_BASE,
 +        SHAKTI_C_PLIC_ENABLE_STRIDE,
 +        SHAKTI_C_PLIC_CONTEXT_BASE,
 +        SHAKTI_C_PLIC_CONTEXT_STRIDE,
 +        shakti_c_memmap[SHAKTI_C_PLIC].size);
 +
 +    sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
 +        shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
 +        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 +        SIFIVE_CLINT_TIMEBASE_FREQ, false);
 +
 +    /* ROM */
 +    memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
 +                           shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +        shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
 +}
 +
 +static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    dc->realize = shakti_c_soc_state_realize;
 +}
 +
 +static void shakti_c_soc_instance_init(Object *obj)
 +{
 +    ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
 +
 +    object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
 +
 +    /*
 +     * CPU type is fixed and we are not supporting passing from commandline yet.
 +     * So let it be in instance_init. When supported should use ms->cpu_type
 +     * instead of TYPE_RISCV_CPU_SHAKTI_C
 +     */
 +    object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
 +                            TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
 +    object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
 +                            &error_abort);
 +}
 +
 +static const TypeInfo shakti_c_type_info = {
 +    .name = TYPE_RISCV_SHAKTI_SOC,
 +    .parent = TYPE_DEVICE,
 +    .class_init = shakti_c_soc_class_init,
 +    .instance_init = shakti_c_soc_instance_init,
 +    .instance_size = sizeof(ShaktiCSoCState),
 +};
 +
 +static void shakti_c_type_info_register(void)
 +{
 +    type_register_static(&shakti_c_type_info);
 +}
 +type_init(shakti_c_type_info_register)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/mchp_pfsoc_dmc.h
  F: include/hw/misc/mchp_pfsoc_ioscb.h
  F: include/hw/misc/mchp_pfsoc_sysreg.h
 +Shakti C class SoC
 +M: Vijai Kumar K <vijai@behindbytes.com>
 +L: qemu-riscv@nongnu.org
 +S: Supported
 +F: hw/riscv/shakti_c.c
 +F: include/hw/riscv/shakti_c.h
 +
  SiFive Machines
  M: Alistair Francis <Alistair.Francis@wdc.com>
  M: Bin Meng <bin.meng@windriver.com>
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config OPENTITAN
      select IBEX
      select UNIMP
 +config SHAKTI
 +    bool
 +
 +config SHAKTI_C
 +    bool
 +    select UNIMP
 +    select SHAKTI
 +    select SIFIVE_CLINT
 +    select SIFIVE_PLIC
 +
  config RISCV_VIRT
      bool
      imply PCI_DEVICES
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
  riscv_ss.add(files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 +riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 --
 .31.1

-[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
+[PULL v2 07/42] hw/char: Add Shakti UART emulation
-From: Alistair Francis <alistair23@gmail.com>
+From: Vijai Kumar K <vijai@behindbytes.com>
-Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
+This is the initial implementation of Shakti UART.
-CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
-CSRs are part of the disassembly.
+Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
+Message-id: 20210401181457.73039-4-vijai@behindbytes.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Fixes: ea10325917 ("RISC-V Disassembler")
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
+ include/hw/char/shakti_uart.h |  74 ++++++++++++++
-file changed, 64 insertions(+), 1 deletion(-)
+ hw/char/shakti_uart.c         | 185 ++++++++++++++++++++++++++++++++++
+ MAINTAINERS                   |   2 +
-diff --git a/disas/riscv.c b/disas/riscv.c
+ hw/char/meson.build           |   1 +
  hw/char/trace-events          |   4 +
 files changed, 266 insertions(+)
  create mode 100644 include/hw/char/shakti_uart.h
  create mode 100644 hw/char/shakti_uart.c
 diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/char/shakti_uart.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SHAKTI UART
 + *
 + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#ifndef HW_SHAKTI_UART_H
 +#define HW_SHAKTI_UART_H
 +
 +#include "hw/sysbus.h"
 +#include "chardev/char-fe.h"
 +
 +#define SHAKTI_UART_BAUD        0x00
 +#define SHAKTI_UART_TX          0x04
 +#define SHAKTI_UART_RX          0x08
 +#define SHAKTI_UART_STATUS      0x0C
 +#define SHAKTI_UART_DELAY       0x10
 +#define SHAKTI_UART_CONTROL     0x14
 +#define SHAKTI_UART_INT_EN      0x18
 +#define SHAKTI_UART_IQ_CYCLES   0x1C
 +#define SHAKTI_UART_RX_THRES    0x20
 +
 +#define SHAKTI_UART_STATUS_TX_EMPTY     (1 << 0)
 +#define SHAKTI_UART_STATUS_TX_FULL      (1 << 1)
 +#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
 +#define SHAKTI_UART_STATUS_RX_FULL      (1 << 3)
 +/* 9600 8N1 is the default setting */
 +/* Reg value = (50000000 Hz)/(16 * 9600)*/
 +#define SHAKTI_UART_BAUD_DEFAULT    0x0145
 +#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
 +
 +#define TYPE_SHAKTI_UART "shakti-uart"
 +#define SHAKTI_UART(obj) \
 +    OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
 +
 +typedef struct {
 +    /* <private> */
 +    SysBusDevice parent_obj;
 +
 +    /* <public> */
 +    MemoryRegion mmio;
 +
 +    uint32_t uart_baud;
 +    uint32_t uart_tx;
 +    uint32_t uart_rx;
 +    uint32_t uart_status;
 +    uint32_t uart_delay;
 +    uint32_t uart_control;
 +    uint32_t uart_interrupt;
 +    uint32_t uart_iq_cycles;
 +    uint32_t uart_rx_threshold;
 +
 +    CharBackend chr;
 +} ShaktiUartState;
 +
 +#endif /* HW_SHAKTI_UART_H */
 diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/char/shakti_uart.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SHAKTI UART
 + *
 + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/char/shakti_uart.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/qdev-properties-system.h"
 +#include "qemu/log.h"
 +
 +static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
 +{
 +    ShaktiUartState *s = opaque;
 +
 +    switch (addr) {
 +    case SHAKTI_UART_BAUD:
 +        return s->uart_baud;
 +    case SHAKTI_UART_RX:
 +        qemu_chr_fe_accept_input(&s->chr);
 +        s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
 +        return s->uart_rx;
 +    case SHAKTI_UART_STATUS:
 +        return s->uart_status;
 +    case SHAKTI_UART_DELAY:
 +        return s->uart_delay;
 +    case SHAKTI_UART_CONTROL:
 +        return s->uart_control;
 +    case SHAKTI_UART_INT_EN:
 +        return s->uart_interrupt;
 +    case SHAKTI_UART_IQ_CYCLES:
 +        return s->uart_iq_cycles;
 +    case SHAKTI_UART_RX_THRES:
 +        return s->uart_rx_threshold;
 +    default:
 +        /* Also handles TX REG which is write only */
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 +    }
 +
 +    return 0;
 +}
 +
 +static void shakti_uart_write(void *opaque, hwaddr addr,
 +                              uint64_t data, unsigned size)
 +{
 +    ShaktiUartState *s = opaque;
 +    uint32_t value = data;
 +    uint8_t ch;
 +
 +    switch (addr) {
 +    case SHAKTI_UART_BAUD:
 +        s->uart_baud = value;
 +        break;
 +    case SHAKTI_UART_TX:
 +        ch = value;
 +        qemu_chr_fe_write_all(&s->chr, &ch, 1);
 +        s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
 +        break;
 +    case SHAKTI_UART_STATUS:
 +        s->uart_status = value;
 +        break;
 +    case SHAKTI_UART_DELAY:
 +        s->uart_delay = value;
 +        break;
 +    case SHAKTI_UART_CONTROL:
 +        s->uart_control = value;
 +        break;
 +    case SHAKTI_UART_INT_EN:
 +        s->uart_interrupt = value;
 +        break;
 +    case SHAKTI_UART_IQ_CYCLES:
 +        s->uart_iq_cycles = value;
 +        break;
 +    case SHAKTI_UART_RX_THRES:
 +        s->uart_rx_threshold = value;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 +    }
 +}
 +
 +static const MemoryRegionOps shakti_uart_ops = {
 +    .read = shakti_uart_read,
 +    .write = shakti_uart_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .impl = {.min_access_size = 1, .max_access_size = 4},
 +    .valid = {.min_access_size = 1, .max_access_size = 4},
 +};
 +
 +static void shakti_uart_reset(DeviceState *dev)
 +{
 +    ShaktiUartState *s = SHAKTI_UART(dev);
 +
 +    s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
 +    s->uart_tx = 0x0;
 +    s->uart_rx = 0x0;
 +    s->uart_status = 0x0000;
 +    s->uart_delay = 0x0000;
 +    s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
 +    s->uart_interrupt = 0x0000;
 +    s->uart_iq_cycles = 0x00;
 +    s->uart_rx_threshold = 0x00;
 +}
 +
 +static int shakti_uart_can_receive(void *opaque)
 +{
 +    ShaktiUartState *s = opaque;
 +
 +    return !(s->uart_status & SHAKTI_UART_STATUS_RX_NOT_EMPTY);
 +}
 +
 +static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
 +{
 +    ShaktiUartState *s = opaque;
 +
 +    s->uart_rx = *buf;
 +    s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
 +}
 +
 +static void shakti_uart_realize(DeviceState *dev, Error **errp)
 +{
 +    ShaktiUartState *sus = SHAKTI_UART(dev);
 +    qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
 +                             shakti_uart_receive, NULL, NULL, sus, NULL, true);
 +}
 +
 +static void shakti_uart_instance_init(Object *obj)
 +{
 +    ShaktiUartState *sus = SHAKTI_UART(obj);
 +    memory_region_init_io(&sus->mmio,
 +                          obj,
 +                          &shakti_uart_ops,
 +                          sus,
 +                          TYPE_SHAKTI_UART,
 +                          0x1000);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
 +}
 +
 +static Property shakti_uart_properties[] = {
 +    DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void shakti_uart_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    dc->reset = shakti_uart_reset;
 +    dc->realize = shakti_uart_realize;
 +    device_class_set_props(dc, shakti_uart_properties);
 +}
 +
 +static const TypeInfo shakti_uart_info = {
 +    .name = TYPE_SHAKTI_UART,
 +    .parent = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(ShaktiUartState),
 +    .class_init = shakti_uart_class_init,
 +    .instance_init = shakti_uart_instance_init,
 +};
 +
 +static void shakti_uart_register_types(void)
 +{
 +    type_register_static(&shakti_uart_info);
 +}
 +type_init(shakti_uart_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/disas/riscv.c
+--- a/MAINTAINERS
-+++ b/disas/riscv.c
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
+@@ -XXX,XX +XXX,XX @@ M: Vijai Kumar K <vijai@behindbytes.com>
-     case 0x0383: return "mibound";
+ L: qemu-riscv@nongnu.org
-     case 0x0384: return "mdbase";
+ S: Supported
-     case 0x0385: return "mdbound";
+ F: hw/riscv/shakti_c.c
--    case 0x03a0: return "pmpcfg3";
++F: hw/char/shakti_uart.c
-+    case 0x03a0: return "pmpcfg0";
+ F: include/hw/riscv/shakti_c.h
-+    case 0x03a1: return "pmpcfg1";
++F: include/hw/char/shakti_uart.h
-+    case 0x03a2: return "pmpcfg2";
-+    case 0x03a3: return "pmpcfg3";
+ SiFive Machines
-+    case 0x03a4: return "pmpcfg4";
+ M: Alistair Francis <Alistair.Francis@wdc.com>
-+    case 0x03a5: return "pmpcfg5";
+diff --git a/hw/char/meson.build b/hw/char/meson.build
-+    case 0x03a6: return "pmpcfg6";
+index XXXXXXX..XXXXXXX 100644
-+    case 0x03a7: return "pmpcfg7";
+--- a/hw/char/meson.build
-+    case 0x03a8: return "pmpcfg8";
++++ b/hw/char/meson.build
-+    case 0x03a9: return "pmpcfg9";
+@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
-+    case 0x03aa: return "pmpcfg10";
+ softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
-+    case 0x03ab: return "pmpcfg11";
+ softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
-+    case 0x03ac: return "pmpcfg12";
+ softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
-+    case 0x03ad: return "pmpcfg13";
++softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
-+    case 0x03ae: return "pmpcfg14";
+ softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
-+    case 0x03af: return "pmpcfg15";
+ softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
-     case 0x03b0: return "pmpaddr0";
+ softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
-     case 0x03b1: return "pmpaddr1";
+diff --git a/hw/char/trace-events b/hw/char/trace-events
-     case 0x03b2: return "pmpaddr2";
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
+--- a/hw/char/trace-events
-     case 0x03bd: return "pmpaddr13";
++++ b/hw/char/trace-events
-     case 0x03be: return "pmpaddr14";
+@@ -XXX,XX +XXX,XX @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
-     case 0x03bf: return "pmpaddr15";
+ nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
-+    case 0x03c0: return "pmpaddr16";
+ nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
-+    case 0x03c1: return "pmpaddr17";
-+    case 0x03c2: return "pmpaddr18";
++# shakti_uart.c
-+    case 0x03c3: return "pmpaddr19";
++shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
-+    case 0x03c4: return "pmpaddr20";
++shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
-+    case 0x03c5: return "pmpaddr21";
++
-+    case 0x03c6: return "pmpaddr22";
+ # exynos4210_uart.c
-+    case 0x03c7: return "pmpaddr23";
+ exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
-+    case 0x03c8: return "pmpaddr24";
+ exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
 +    case 0x03c9: return "pmpaddr25";
 +    case 0x03ca: return "pmpaddr26";
 +    case 0x03cb: return "pmpaddr27";
 +    case 0x03cc: return "pmpaddr28";
 +    case 0x03cd: return "pmpaddr29";
 +    case 0x03ce: return "pmpaddr30";
 +    case 0x03cf: return "pmpaddr31";
 +    case 0x03d0: return "pmpaddr32";
 +    case 0x03d1: return "pmpaddr33";
 +    case 0x03d2: return "pmpaddr34";
 +    case 0x03d3: return "pmpaddr35";
 +    case 0x03d4: return "pmpaddr36";
 +    case 0x03d5: return "pmpaddr37";
 +    case 0x03d6: return "pmpaddr38";
 +    case 0x03d7: return "pmpaddr39";
 +    case 0x03d8: return "pmpaddr40";
 +    case 0x03d9: return "pmpaddr41";
 +    case 0x03da: return "pmpaddr42";
 +    case 0x03db: return "pmpaddr43";
 +    case 0x03dc: return "pmpaddr44";
 +    case 0x03dd: return "pmpaddr45";
 +    case 0x03de: return "pmpaddr46";
 +    case 0x03df: return "pmpaddr47";
 +    case 0x03e0: return "pmpaddr48";
 +    case 0x03e1: return "pmpaddr49";
 +    case 0x03e2: return "pmpaddr50";
 +    case 0x03e3: return "pmpaddr51";
 +    case 0x03e4: return "pmpaddr52";
 +    case 0x03e5: return "pmpaddr53";
 +    case 0x03e6: return "pmpaddr54";
 +    case 0x03e7: return "pmpaddr55";
 +    case 0x03e8: return "pmpaddr56";
 +    case 0x03e9: return "pmpaddr57";
 +    case 0x03ea: return "pmpaddr58";
 +    case 0x03eb: return "pmpaddr59";
 +    case 0x03ec: return "pmpaddr60";
 +    case 0x03ed: return "pmpaddr61";
 +    case 0x03ee: return "pmpaddr62";
 +    case 0x03ef: return "pmpaddr63";
      case 0x0780: return "mtohost";
      case 0x0781: return "mfromhost";
      case 0x0782: return "mreset";
 --
-.45.1
+.31.1

-[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+[PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform
-From: Max Chou <max.chou@sifive.com>
+From: Vijai Kumar K <vijai@behindbytes.com>
-If the checking functions check both the single and double width
+Connect one shakti uart to the shakti_c machine.
 operators at the same time, then the single width operator checking
 functions (require_rvf[min]) will check whether the SEW is 8.
-Signed-off-by: Max Chou <max.chou@sifive.com>
+Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-id: 20210401181457.73039-5-vijai@behindbytes.com
 Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
+ include/hw/riscv/shakti_c.h | 2 ++
-file changed, 4 insertions(+), 12 deletions(-)
+ hw/riscv/shakti_c.c         | 8 ++++++++
 files changed, 10 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
+--- a/include/hw/riscv/shakti_c.h
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/include/hw/riscv/shakti_c.h
-@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+@@ -XXX,XX +XXX,XX @@
-     return require_rvv(s) &&
-            require_rvf(s) &&
+ #include "hw/riscv/riscv_hart.h"
-            require_scale_rvf(s) &&
+ #include "hw/boards.h"
--           (s->sew != MO_8) &&
++#include "hw/char/shakti_uart.h"
-            vext_check_isa_ill(s) &&
-            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+ #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
- }
+ #define RISCV_SHAKTI_SOC(obj) \
-@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
+@@ -XXX,XX +XXX,XX @@ typedef struct ShaktiCSoCState {
-     return require_rvv(s) &&
+     /*< public >*/
-            require_rvf(s) &&
+     RISCVHartArrayState cpus;
-            require_scale_rvf(s) &&
+     DeviceState *plic;
--           (s->sew != MO_8) &&
++    ShaktiUartState uart;
-            vext_check_isa_ill(s) &&
+     MemoryRegion rom;
-            vext_check_ds(s, a->rd, a->rs2, a->vm);
- }
+ } ShaktiCSoCState;
-@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
+diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
-     return require_rvv(s) &&
+index XXXXXXX..XXXXXXX 100644
-            require_rvf(s) &&
+--- a/hw/riscv/shakti_c.c
-            require_scale_rvf(s) &&
++++ b/hw/riscv/shakti_c.c
--           (s->sew != MO_8) &&
+@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
-            vext_check_isa_ill(s) &&
+         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
+         SIFIVE_CLINT_TIMEBASE_FREQ, false);
- }
-@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
++    qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
-     return require_rvv(s) &&
++    if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
-            require_rvf(s) &&
++        return;
-            require_scale_rvf(s) &&
++    }
--           (s->sew != MO_8) &&
++    sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
-            vext_check_isa_ill(s) &&
++                    shakti_c_memmap[SHAKTI_C_UART].base);
-            vext_check_dd(s, a->rd, a->rs2, a->vm);
++
- }
+     /* ROM */
-@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
+     memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
- {
+                            shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
-     return opfv_widen_check(s, a) &&
+@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_instance_init(Object *obj)
-            require_rvfmin(s) &&
+     ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
--           require_scale_rvfmin(s) &&
--           (s->sew != MO_8);
+     object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
-+           require_scale_rvfmin(s);
++    object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
- }
+     /*
- #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
+      * CPU type is fixed and we are not supporting passing from commandline yet.
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_narrow_check(s, a) &&
             require_rvfmin(s) &&
 -           require_scale_rvfmin(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvfmin(s);
  }
  static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_narrow_check(s, a) &&
             require_rvf(s) &&
 -           require_scale_rvf(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
  #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
             require_rvf(s) &&
 -           require_scale_rvf(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
  GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
 --
-.45.1
+.31.1

-[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
+[PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum
-From: Clément Léger <cleger@rivosinc.com>
-The current semihost exception number (16) is a reserved number (range
-[16-17]). The upcoming double trap specification uses that number for
-the double trap exception. Since the privileged spec (Table 22) defines
-ranges for custom uses change the semihosting exception number to 63
-which belongs to the range [48-63] in order to avoid any future
-collisions with reserved exception.
-Signed-off-by: Clément Léger <cleger@rivosinc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
 ---
- target/riscv/cpu_bits.h | 2 +-
+ target/riscv/cpu_bits.h   | 44 ++++++++++++++++++++-------------------
-file changed, 1 insertion(+), 1 deletion(-)
+ target/riscv/cpu.c        |  2 +-
  target/riscv/cpu_helper.c |  4 ++--
 files changed, 26 insertions(+), 24 deletions(-)
 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_bits.h
 +++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
+@@ -XXX,XX +XXX,XX @@
-     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
+ #define DEFAULT_RSTVEC      0x1000
-     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
-     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
+ /* Exception causes */
--    RISCV_EXCP_SEMIHOST = 0x10,
+-#define EXCP_NONE                                -1 /* sentinel value */
-     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
+-#define RISCV_EXCP_INST_ADDR_MIS                 0x0
-     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
+-#define RISCV_EXCP_INST_ACCESS_FAULT             0x1
-     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
+-#define RISCV_EXCP_ILLEGAL_INST                  0x2
-     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+-#define RISCV_EXCP_BREAKPOINT                    0x3
-+    RISCV_EXCP_SEMIHOST = 0x3f,
+-#define RISCV_EXCP_LOAD_ADDR_MIS                 0x4
- } RISCVException;
+-#define RISCV_EXCP_LOAD_ACCESS_FAULT             0x5
 -#define RISCV_EXCP_STORE_AMO_ADDR_MIS            0x6
 -#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT        0x7
 -#define RISCV_EXCP_U_ECALL                       0x8
 -#define RISCV_EXCP_S_ECALL                      0x9
 -#define RISCV_EXCP_VS_ECALL                      0xa
 -#define RISCV_EXCP_M_ECALL                       0xb
 -#define RISCV_EXCP_INST_PAGE_FAULT               0xc /* since: priv-1.10.0 */
 -#define RISCV_EXCP_LOAD_PAGE_FAULT               0xd /* since: priv-1.10.0 */
 -#define RISCV_EXCP_STORE_PAGE_FAULT              0xf /* since: priv-1.10.0 */
 -#define RISCV_EXCP_SEMIHOST                      0x10
 -#define RISCV_EXCP_INST_GUEST_PAGE_FAULT         0x14
 -#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT       0x15
 -#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT        0x16
 -#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT  0x17
 +typedef enum RISCVException {
 +    RISCV_EXCP_NONE = -1, /* sentinel value */
 +    RISCV_EXCP_INST_ADDR_MIS = 0x0,
 +    RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
 +    RISCV_EXCP_ILLEGAL_INST = 0x2,
 +    RISCV_EXCP_BREAKPOINT = 0x3,
 +    RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
 +    RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
 +    RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
 +    RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
 +    RISCV_EXCP_U_ECALL = 0x8,
 +    RISCV_EXCP_S_ECALL = 0x9,
 +    RISCV_EXCP_VS_ECALL = 0xa,
 +    RISCV_EXCP_M_ECALL = 0xb,
 +    RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
 +    RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
 +    RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
 +    RISCV_EXCP_SEMIHOST = 0x10,
 +    RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
 +    RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
 +    RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
 +    RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
 +} RISCVException;
  #define RISCV_EXCP_INT_FLAG                0x80000000
+ #define RISCV_EXCP_INT_MASK                0x7fffffff
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+     env->pc = env->resetvec;
+     env->two_stage_lookup = false;
+ #endif
+-    cs->exception_index = EXCP_NONE;
++    cs->exception_index = RISCV_EXCP_NONE;
+     env->load_res = -1;
+     set_default_nan_mode(1, &env->fp_status);
+ }
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
+     if (irqs) {
+         return ctz64(irqs); /* since non-zero */
+     } else {
+-        return EXCP_NONE; /* indicates no pending interrupt */
++        return RISCV_EXCP_NONE; /* indicates no pending interrupt */
+     }
+ }
+ #endif
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+     env->two_stage_lookup = false;
+ #endif
+-    cs->exception_index = EXCP_NONE; /* mark handled to qemu */
++    cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
+ }
 --
-.45.1
+.31.1

-[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
+[PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: 187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com
 ---
  target/riscv/cpu.h |  3 +-
  target/riscv/csr.c | 80 +++++++++++++++++++++++++---------------------
 files changed, 46 insertions(+), 37 deletions(-)
-The th.sxstatus CSR can be used to identify available custom extension
-on T-Head CPUs. The CSR is documented here:
-  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
-An important property of this patch is, that the th.sxstatus MAEE field
-is not set (indicating that XTheadMae is not available).
-XTheadMae is a memory attribute extension (similar to Svpbmt) which is
-implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
-in PTEs that are marked as reserved. QEMU maintainers prefer to not
-implement XTheadMae, so we need give kernels a mechanism to identify
-if XTheadMae is available in a system or not. And this patch introduces
-this mechanism in QEMU in a way that's compatible with real HW
-(i.e., probing the th.sxstatus.MAEE bit).
-Further context can be found on the list:
-https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
-Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- MAINTAINERS              |  1 +
- target/riscv/cpu.h       |  3 ++
- target/riscv/cpu.c       |  1 +
- target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
- target/riscv/meson.build |  1 +
-files changed, 85 insertions(+)
- create mode 100644 target/riscv/th_csr.c
-diff --git a/MAINTAINERS b/MAINTAINERS
-index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
- S: Supported
- F: target/riscv/insn_trans/trans_xthead.c.inc
- F: target/riscv/xthead*.decode
-+F: target/riscv/th_*
- F: disas/riscv-xthead*
- RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
+@@ -XXX,XX +XXX,XX @@ static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
- uint8_t satp_mode_max_from_map(uint32_t map);
+     return val;
- const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
+ }
-+/* Implemented in th_csr.c */
+-typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
-+void th_register_custom_csrs(RISCVCPU *cpu);
++typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
-+
++                                                 int csrno);
- #endif /* RISCV_CPU_H */
+ typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+     target_ulong *ret_value);
  typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/target/riscv/csr.c
-+++ b/target/riscv/cpu.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
-     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
+ }
- #ifndef CONFIG_USER_ONLY
-     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+ /* Predicates */
-+    th_register_custom_csrs(cpu);
+-static int fs(CPURISCVState *env, int csrno)
 +static RISCVException fs(CPURISCVState *env, int csrno)
  {
  #if !defined(CONFIG_USER_ONLY)
      /* loose check condition for fcsr in vector extension */
      if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
 -        return 0;
 +        return RISCV_EXCP_NONE;
      }
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
  #endif
+-    return 0;
-     /* inherited from parent obj via riscv_cpu_init() */
++    return RISCV_EXCP_NONE;
-diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
+ }
-new file mode 100644
-index XXXXXXX..XXXXXXX
+-static int vs(CPURISCVState *env, int csrno)
---- /dev/null
++static RISCVException vs(CPURISCVState *env, int csrno)
-+++ b/target/riscv/th_csr.c
+ {
-@@ -XXX,XX +XXX,XX @@
+     if (env->misa & RVV) {
-+/*
+-        return 0;
-+ * T-Head-specific CSRs.
++        return RISCV_EXCP_NONE;
-+ *
+     }
-+ * Copyright (c) 2024 VRULL GmbH
+-    return -RISCV_EXCP_ILLEGAL_INST;
-+ *
++    return RISCV_EXCP_ILLEGAL_INST;
-+ * This program is free software; you can redistribute it and/or modify it
+ }
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2 or later, as published by the Free Software Foundation.
+-static int ctr(CPURISCVState *env, int csrno)
-+ *
++static RISCVException ctr(CPURISCVState *env, int csrno)
-+ * This program is distributed in the hope it will be useful, but WITHOUT
+ {
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ #if !defined(CONFIG_USER_ONLY)
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+     CPUState *cs = env_cpu(env);
-+ * more details.
+@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
-+ *
-+ * You should have received a copy of the GNU General Public License along with
+     if (!cpu->cfg.ext_counters) {
-+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+         /* The Counters extensions is not enabled */
-+ */
+-        return -RISCV_EXCP_ILLEGAL_INST;
-+
++        return RISCV_EXCP_ILLEGAL_INST;
-+#include "qemu/osdep.h"
+     }
-+#include "cpu.h"
-+#include "cpu_vendorid.h"
+     if (riscv_cpu_virt_enabled(env)) {
-+
+@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
-+#define CSR_TH_SXSTATUS 0x5c0
+         case CSR_CYCLE:
-+
+             if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
-+/* TH_SXSTATUS bits */
+                 get_field(env->mcounteren, HCOUNTEREN_CY)) {
-+#define TH_SXSTATUS_UCME        BIT(16)
+-                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-+#define TH_SXSTATUS_MAEE        BIT(21)
++                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+             }
-+
+             break;
-+typedef struct {
+         case CSR_TIME:
-+    int csrno;
+             if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
-+    int (*insertion_test)(RISCVCPU *cpu);
+                 get_field(env->mcounteren, HCOUNTEREN_TM)) {
-+    riscv_csr_operations csr_ops;
+-                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-+} riscv_csr;
++                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-+
+             }
              break;
          case CSR_INSTRET:
              if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
                  get_field(env->mcounteren, HCOUNTEREN_IR)) {
 -                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
              }
              break;
          case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
              if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
                  get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
 -                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
              }
              break;
          }
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
              case CSR_CYCLEH:
                  if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
                      get_field(env->mcounteren, HCOUNTEREN_CY)) {
 -                    return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +                    return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                  }
                  break;
              case CSR_TIMEH:
                  if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
                      get_field(env->mcounteren, HCOUNTEREN_TM)) {
 -                    return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +                    return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                  }
                  break;
              case CSR_INSTRETH:
                  if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
                      get_field(env->mcounteren, HCOUNTEREN_IR)) {
 -                    return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +                    return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                  }
                  break;
              case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
                  if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
                      get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 -                    return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +                    return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                  }
                  break;
              }
          }
      }
  #endif
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int ctr32(CPURISCVState *env, int csrno)
 +static RISCVException ctr32(CPURISCVState *env, int csrno)
  {
      if (!riscv_cpu_is_32bit(env)) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      return ctr(env, csrno);
  }
  #if !defined(CONFIG_USER_ONLY)
 -static int any(CPURISCVState *env, int csrno)
 +static RISCVException any(CPURISCVState *env, int csrno)
  {
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int any32(CPURISCVState *env, int csrno)
 +static RISCVException any32(CPURISCVState *env, int csrno)
  {
      if (!riscv_cpu_is_32bit(env)) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      return any(env, csrno);
  }
 -static int smode(CPURISCVState *env, int csrno)
 +static RISCVException smode(CPURISCVState *env, int csrno)
-+{
+ {
 -    return -!riscv_has_ext(env, RVS);
 +    if (riscv_has_ext(env, RVS)) {
 +        return RISCV_EXCP_NONE;
 +    }
 +
 +    return RISCV_EXCP_ILLEGAL_INST;
-+}
+ }
-+
-+static int test_thead_mvendorid(RISCVCPU *cpu)
+-static int hmode(CPURISCVState *env, int csrno)
-+{
++static RISCVException hmode(CPURISCVState *env, int csrno)
-+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+ {
-+        return -1;
+     if (riscv_has_ext(env, RVS) &&
          riscv_has_ext(env, RVH)) {
          /* Hypervisor extension is supported */
          if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
              env->priv == PRV_M) {
 -            return 0;
 +            return RISCV_EXCP_NONE;
          } else {
 -            return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
          }
      }
 -    return -RISCV_EXCP_ILLEGAL_INST;
 +    return RISCV_EXCP_ILLEGAL_INST;
  }
 -static int hmode32(CPURISCVState *env, int csrno)
 +static RISCVException hmode32(CPURISCVState *env, int csrno)
  {
      if (!riscv_cpu_is_32bit(env)) {
 -        return 0;
 +        return RISCV_EXCP_NONE;
      }
      return hmode(env, csrno);
  }
 -static int pmp(CPURISCVState *env, int csrno)
 +static RISCVException pmp(CPURISCVState *env, int csrno)
  {
 -    return -!riscv_feature(env, RISCV_FEATURE_PMP);
 +    if (riscv_feature(env, RISCV_FEATURE_PMP)) {
 +        return RISCV_EXCP_NONE;
 +    }
 +
-+    return 0;
++    return RISCV_EXCP_ILLEGAL_INST;
-+}
+ }
-+
+ #endif
-+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
-+                                       target_ulong *val)
+@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
-+{
+         return -RISCV_EXCP_ILLEGAL_INST;
-+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+     }
-+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+     ret = csr_ops[csrno].predicate(env, csrno);
-+    return RISCV_EXCP_NONE;
+-    if (ret < 0) {
-+}
+-        return ret;
-+
++    if (ret != RISCV_EXCP_NONE) {
-+static riscv_csr th_csr_list[] = {
++        return -ret;
-+    {
+     }
-+        .csrno = CSR_TH_SXSTATUS,
-+        .insertion_test = test_thead_mvendorid,
+     /* execute combined read/write operation if it exists */
 +        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
 +    }
 +};
 +
 +void th_register_custom_csrs(RISCVCPU *cpu)
 +{
 +    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
 +        int csrno = th_csr_list[i].csrno;
 +        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
 +        if (!th_csr_list[i].insertion_test(cpu)) {
 +            riscv_set_csr_ops(csrno, csr_ops);
 +        }
 +    }
 +}
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
    'monitor.c',
    'machine.c',
    'pmu.c',
 +  'th_csr.c',
    'time_helper.c',
    'riscv-qmp-cmds.c',
  ))
 --
-.45.1
+.31.1

-New patch
+[PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
+---
+ target/riscv/csr.c | 6 +++++-
+file changed, 5 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException hmode(CPURISCVState *env, int csrno)
+ static RISCVException hmode32(CPURISCVState *env, int csrno)
+ {
+     if (!riscv_cpu_is_32bit(env)) {
+-        return RISCV_EXCP_NONE;
++        if (riscv_cpu_virt_enabled(env)) {
++            return RISCV_EXCP_ILLEGAL_INST;
++        } else {
++            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++        }
+     }
+     return hmode(env, csrno);
+--
+.31.1

-[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
+[PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations
-From: Andrew Jones <ajones@ventanamicro.com>
-The Zkr extension may only be exposed to KVM guests if the VMM
-implements the SEED CSR. Use the same implementation as TCG.
-Without this patch, running with a KVM which does not forward the
-SEED CSR access to QEMU will result in an ILL exception being
-injected into the guest (this results in Linux guests crashing on
-boot). And, when running with a KVM which does forward the access,
-QEMU will crash, since QEMU doesn't know what to do with the exit.
-Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
-Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
 ---
- target/riscv/cpu.h         |  3 +++
+ target/riscv/cpu.h |  14 +-
- target/riscv/csr.c         | 18 ++++++++++++++----
+ target/riscv/csr.c | 629 +++++++++++++++++++++++++++------------------
- target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
+files changed, 382 insertions(+), 261 deletions(-)
 files changed, 42 insertions(+), 4 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
+@@ -XXX,XX +XXX,XX @@ static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
- void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
+ typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
+                                                  int csrno);
-+target_ulong riscv_new_csr_seed(target_ulong new_value,
+-typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
-+                                target_ulong write_mask);
+-    target_ulong *ret_value);
-+
+-typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
- uint8_t satp_mode_max_from_map(uint32_t map);
+-    target_ulong new_value);
- const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
+-typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+-    target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
 +typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 +                                            target_ulong *ret_value);
 +typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 +                                             target_ulong new_value);
 +typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 +                                          target_ulong *ret_value,
 +                                          target_ulong new_value,
 +                                          target_ulong write_mask);
  typedef struct {
      const char *name;
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
  #endif
- /* Crypto Extension */
+ /* User Floating-Point CSRs */
--static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+-static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
--                               target_ulong *ret_value,
++static RISCVException read_fflags(CPURISCVState *env, int csrno,
--                               target_ulong new_value,
++                                  target_ulong *val)
--                               target_ulong write_mask)
+ {
-+target_ulong riscv_new_csr_seed(target_ulong new_value,
+ #if !defined(CONFIG_USER_ONLY)
-+                                target_ulong write_mask)
+     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- {
+-        return -RISCV_EXCP_ILLEGAL_INST;
-     uint16_t random_v;
++        return RISCV_EXCP_ILLEGAL_INST;
-     Error *random_e = NULL;
+     }
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+ #endif
-         rval = random_v | SEED_OPST_ES16;
+     *val = riscv_cpu_get_fflags(env);
-     }
+-    return 0;
++    return RISCV_EXCP_NONE;
-+    return rval;
+ }
-+}
-+
+-static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
-+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
++static RISCVException write_fflags(CPURISCVState *env, int csrno,
 +                                   target_ulong val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      env->mstatus |= MSTATUS_FS;
  #endif
      riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_frm(CPURISCVState *env, int csrno,
 +                               target_ulong *val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
  #endif
      *val = env->frm;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_frm(CPURISCVState *env, int csrno,
 +                                target_ulong val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      env->mstatus |= MSTATUS_FS;
  #endif
      env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_fcsr(CPURISCVState *env, int csrno,
 +                                target_ulong *val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
  #endif
      *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
@@ -XXX,XX +XXX,XX @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
          *val |= (env->vxrm << FSR_VXRM_SHIFT)
                  | (env->vxsat << FSR_VXSAT_SHIFT);
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_fcsr(CPURISCVState *env, int csrno,
 +                                 target_ulong val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      env->mstatus |= MSTATUS_FS;
  #endif
@@ -XXX,XX +XXX,XX @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
          env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
      }
      riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vtype(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->vtype;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vl(CPURISCVState *env, int csrno,
 +                              target_ulong *val)
  {
      *val = env->vl;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vxrm(CPURISCVState *env, int csrno,
 +                                target_ulong *val)
  {
      *val = env->vxrm;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vxrm(CPURISCVState *env, int csrno,
 +                                 target_ulong val)
  {
      env->vxrm = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vxsat(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->vxsat;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vxsat(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      env->vxsat = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vstart(CPURISCVState *env, int csrno,
 +                                  target_ulong *val)
  {
      *val = env->vstart;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vstart(CPURISCVState *env, int csrno,
 +                                   target_ulong val)
  {
      env->vstart = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /* User Timers and Counters */
 -static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_instret(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (icount_enabled()) {
@@ -XXX,XX +XXX,XX @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
  #else
      *val = cpu_get_host_ticks();
  #endif
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_instreth(CPURISCVState *env, int csrno,
 +                                    target_ulong *val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (icount_enabled()) {
@@ -XXX,XX +XXX,XX @@ static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
  #else
      *val = cpu_get_host_ticks() >> 32;
  #endif
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  #if defined(CONFIG_USER_ONLY)
 -static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_time(CPURISCVState *env, int csrno,
 +                                target_ulong *val)
  {
      *val = cpu_get_host_ticks();
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_timeh(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = cpu_get_host_ticks() >> 32;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  #else /* CONFIG_USER_ONLY */
 -static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_time(CPURISCVState *env, int csrno,
 +                                target_ulong *val)
  {
      uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
      if (!env->rdtime_fn) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_timeh(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
      if (!env->rdtime_fn) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /* Machine constants */
@@ -XXX,XX +XXX,XX @@ static const char valid_vm_1_10_64[16] = {
  };
  /* Machine Information Registers */
 -static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_zero(CPURISCVState *env, int csrno,
 +                                target_ulong *val)
  {
 -    return *val = 0;
 +    *val = 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mhartid(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      *val = env->mhartid;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /* Machine Trap Setup */
 -static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mstatus(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      *val = env->mstatus;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  static int validate_vm(CPURISCVState *env, target_ulong vm)
@@ -XXX,XX +XXX,XX @@ static int validate_vm(CPURISCVState *env, target_ulong vm)
      }
  }
 -static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 +                                    target_ulong val)
  {
      uint64_t mstatus = env->mstatus;
      uint64_t mask = 0;
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
      mstatus = set_field(mstatus, MSTATUS_SD, dirty);
      env->mstatus = mstatus;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mstatush(CPURISCVState *env, int csrno,
 +                                    target_ulong *val)
  {
      *val = env->mstatus >> 32;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mstatush(CPURISCVState *env, int csrno,
 +                                     target_ulong val)
  {
      uint64_t valh = (uint64_t)val << 32;
      uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
@@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
      env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_misa(CPURISCVState *env, int csrno,
 +                                target_ulong *val)
  {
      *val = env->misa;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_misa(CPURISCVState *env, int csrno,
 +                                 target_ulong val)
  {
      if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
          /* drop write to misa */
 -        return 0;
 +        return RISCV_EXCP_NONE;
      }
      /* 'I' or 'E' must be present */
      if (!(val & (RVI | RVE))) {
          /* It is not, drop write to misa */
 -        return 0;
 +        return RISCV_EXCP_NONE;
      }
      /* 'E' excludes all other extensions */
@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
          /* when we support 'E' we can do "val = RVE;" however
           * for now we just drop writes if 'E' is present.
           */
 -        return 0;
 +        return RISCV_EXCP_NONE;
      }
      /* Mask extensions that are not supported by this hart */
@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
      env->misa = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_medeleg(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      *val = env->medeleg;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_medeleg(CPURISCVState *env, int csrno,
 +                                    target_ulong val)
  {
      env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mideleg(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      *val = env->mideleg;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mideleg(CPURISCVState *env, int csrno,
 +                                    target_ulong val)
  {
      env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
      if (riscv_has_ext(env, RVH)) {
          env->mideleg |= VS_MODE_INTERRUPTS;
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mie(CPURISCVState *env, int csrno,
 +                               target_ulong *val)
  {
      *val = env->mie;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mie(CPURISCVState *env, int csrno,
 +                                target_ulong val)
  {
      env->mie = (env->mie & ~all_ints) | (val & all_ints);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mtvec(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->mtvec;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mtvec(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
      if ((val & 3) < 2) {
@@ -XXX,XX +XXX,XX @@ static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
      } else {
          qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
 +                                      target_ulong *val)
  {
      *val = env->mcounteren;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
 +                                       target_ulong val)
  {
      env->mcounteren = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /* Machine Trap Handling */
 -static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mscratch(CPURISCVState *env, int csrno,
 +                                    target_ulong *val)
  {
      *val = env->mscratch;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mscratch(CPURISCVState *env, int csrno,
 +                                     target_ulong val)
  {
      env->mscratch = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mepc(CPURISCVState *env, int csrno,
 +                                     target_ulong *val)
  {
      *val = env->mepc;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mepc(CPURISCVState *env, int csrno,
 +                                     target_ulong val)
  {
      env->mepc = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mcause(CPURISCVState *env, int csrno,
 +                                     target_ulong *val)
  {
      *val = env->mcause;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mcause(CPURISCVState *env, int csrno,
 +                                     target_ulong val)
  {
      env->mcause = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mtval(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->mtval;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mtval(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      env->mtval = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 -                   target_ulong new_value, target_ulong write_mask)
 +static RISCVException rmw_mip(CPURISCVState *env, int csrno,
 +                              target_ulong *ret_value,
 +                              target_ulong new_value, target_ulong write_mask)
  {
      RISCVCPU *cpu = env_archcpu(env);
      /* Allow software control of delegable interrupts not claimed by hardware */
@@ -XXX,XX +XXX,XX @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
          *ret_value = old_mip;
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /* Supervisor Trap Setup */
 -static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_sstatus(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      target_ulong mask = (sstatus_v1_10_mask);
      *val = env->mstatus & mask;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_sstatus(CPURISCVState *env, int csrno,
 +                                    target_ulong val)
  {
      target_ulong mask = (sstatus_v1_10_mask);
      target_ulong newval = (env->mstatus & ~mask) | (val & mask);
      return write_mstatus(env, CSR_MSTATUS, newval);
  }
 -static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vsie(CPURISCVState *env, int csrno,
 +                                target_ulong *val)
  {
      /* Shift the VS bits to their S bit location in vsie */
      *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_sie(CPURISCVState *env, int csrno,
 +                               target_ulong *val)
  {
      if (riscv_cpu_virt_enabled(env)) {
          read_vsie(env, CSR_VSIE, val);
      } else {
          *val = env->mie & env->mideleg;
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vsie(CPURISCVState *env, int csrno,
 +                                 target_ulong val)
  {
      /* Shift the S bits to their VS bit location in mie */
      target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
@@ -XXX,XX +XXX,XX @@ static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
          write_mie(env, CSR_MIE, newval);
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_stvec(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->stvec;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_stvec(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
      if ((val & 3) < 2) {
@@ -XXX,XX +XXX,XX @@ static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
      } else {
          qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_scounteren(CPURISCVState *env, int csrno,
 +                                      target_ulong *val)
  {
      *val = env->scounteren;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_scounteren(CPURISCVState *env, int csrno,
 +                                       target_ulong val)
  {
      env->scounteren = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /* Supervisor Trap Handling */
 -static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_sscratch(CPURISCVState *env, int csrno,
 +                                    target_ulong *val)
  {
      *val = env->sscratch;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_sscratch(CPURISCVState *env, int csrno,
 +                                     target_ulong val)
  {
      env->sscratch = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_sepc(CPURISCVState *env, int csrno,
 +                                target_ulong *val)
  {
      *val = env->sepc;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_sepc(CPURISCVState *env, int csrno,
 +                                 target_ulong val)
  {
      env->sepc = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_scause(CPURISCVState *env, int csrno,
 +                                  target_ulong *val)
  {
      *val = env->scause;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_scause(CPURISCVState *env, int csrno,
 +                                   target_ulong val)
  {
      env->scause = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_stval(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->stval;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_stval(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      env->stval = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 -                    target_ulong new_value, target_ulong write_mask)
 +static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
 +                               target_ulong *ret_value,
-+                               target_ulong new_value,
++                               target_ulong new_value, target_ulong write_mask)
-+                               target_ulong write_mask)
+ {
-+{
+     /* Shift the S bits to their VS bit location in mip */
-+    target_ulong rval;
+     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
-+
+@@ -XXX,XX +XXX,XX @@ static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 +    rval = riscv_new_csr_seed(new_value, write_mask);
 +
      if (ret_value) {
          *ret_value = rval;
      }
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
      return ret;
  }
-+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+-static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-+{
+-                   target_ulong new_value, target_ulong write_mask)
-+    target_ulong csr_num = run->riscv_csr.csr_num;
++static RISCVException rmw_sip(CPURISCVState *env, int csrno,
-+    target_ulong new_value = run->riscv_csr.new_value;
++                              target_ulong *ret_value,
-+    target_ulong write_mask = run->riscv_csr.write_mask;
++                              target_ulong new_value, target_ulong write_mask)
-+    int ret = 0;
+ {
-+
+     int ret;
-+    switch (csr_num) {
-+    case CSR_SEED:
+@@ -XXX,XX +XXX,XX @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+ }
-+        break;
-+    default:
+ /* Supervisor Protection and Translation */
-+        qemu_log_mask(LOG_UNIMP,
+-static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
-+                      "%s: un-handled CSR EXIT for CSR %lx\n",
++static RISCVException read_satp(CPURISCVState *env, int csrno,
-+                      __func__, csr_num);
++                                target_ulong *val)
-+        ret = -1;
+ {
-+        break;
+     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
-+    }
+         *val = 0;
-+
+-        return 0;
-+    return ret;
++        return RISCV_EXCP_NONE;
-+}
+     }
-+
- int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- {
+-        return -RISCV_EXCP_ILLEGAL_INST;
-     int ret = 0;
++        return RISCV_EXCP_ILLEGAL_INST;
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+     } else {
-     case KVM_EXIT_RISCV_SBI:
+         *val = env->satp;
-         ret = kvm_riscv_handle_sbi(cs, run);
+     }
-         break;
-+    case KVM_EXIT_RISCV_CSR:
+-    return 0;
-+        ret = kvm_riscv_handle_csr(cs, run);
++    return RISCV_EXCP_NONE;
-+        break;
+ }
-     default:
-         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
+-static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
-                       __func__, run->exit_reason);
++static RISCVException write_satp(CPURISCVState *env, int csrno,
 +                                 target_ulong val)
  {
      if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 -        return 0;
 +        return RISCV_EXCP_NONE;
      }
      if (validate_vm(env, get_field(val, SATP_MODE)) &&
          ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
      {
          if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 -            return -RISCV_EXCP_ILLEGAL_INST;
 +            return RISCV_EXCP_ILLEGAL_INST;
          } else {
              if ((val ^ env->satp) & SATP_ASID) {
                  tlb_flush(env_cpu(env));
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
              env->satp = val;
          }
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /* Hypervisor Extensions */
 -static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_hstatus(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      *val = env->hstatus;
      if (!riscv_cpu_is_32bit(env)) {
@@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
      }
      /* We only support little endian */
      *val = set_field(*val, HSTATUS_VSBE, 0);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_hstatus(CPURISCVState *env, int csrno,
 +                                    target_ulong val)
  {
      env->hstatus = val;
      if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
@@ -XXX,XX +XXX,XX @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
      if (get_field(val, HSTATUS_VSBE) != 0) {
          qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      *val = env->hedeleg;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
 +                                    target_ulong val)
  {
      env->hedeleg = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_hideleg(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      *val = env->hideleg;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_hideleg(CPURISCVState *env, int csrno,
 +                                    target_ulong val)
  {
      env->hideleg = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 -                   target_ulong new_value, target_ulong write_mask)
 +static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
 +                               target_ulong *ret_value,
 +                               target_ulong new_value, target_ulong write_mask)
  {
      int ret = rmw_mip(env, 0, ret_value, new_value,
                        write_mask & hvip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
      return ret;
  }
 -static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 -                   target_ulong new_value, target_ulong write_mask)
 +static RISCVException rmw_hip(CPURISCVState *env, int csrno,
 +                              target_ulong *ret_value,
 +                              target_ulong new_value, target_ulong write_mask)
  {
      int ret = rmw_mip(env, 0, ret_value, new_value,
                        write_mask & hip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
      return ret;
  }
 -static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_hie(CPURISCVState *env, int csrno,
 +                               target_ulong *val)
  {
      *val = env->mie & VS_MODE_INTERRUPTS;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_hie(CPURISCVState *env, int csrno,
 +                                target_ulong val)
  {
      target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
      return write_mie(env, CSR_MIE, newval);
  }
 -static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
 +                                      target_ulong *val)
  {
      *val = env->hcounteren;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
 +                                       target_ulong val)
  {
      env->hcounteren = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_hgeie(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_hgeie(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_htval(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->htval;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_htval(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      env->htval = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_htinst(CPURISCVState *env, int csrno,
 +                                  target_ulong *val)
  {
      *val = env->htinst;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_htinst(CPURISCVState *env, int csrno,
 +                                   target_ulong val)
  {
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_hgeip(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_hgeip(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_hgatp(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->hgatp;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_hgatp(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      env->hgatp = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
 +                                      target_ulong *val)
  {
      if (!env->rdtime_fn) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      *val = env->htimedelta;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
 +                                       target_ulong val)
  {
      if (!env->rdtime_fn) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      if (riscv_cpu_is_32bit(env)) {
@@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
      } else {
          env->htimedelta = val;
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
 +                                       target_ulong *val)
  {
      if (!env->rdtime_fn) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      *val = env->htimedelta >> 32;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
 +                                        target_ulong val)
  {
      if (!env->rdtime_fn) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /* Virtual CSR Registers */
 -static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
 +                                    target_ulong *val)
  {
      *val = env->vsstatus;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
 +                                     target_ulong val)
  {
      uint64_t mask = (target_ulong)-1;
      env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
  {
      *val = env->vstvec;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vstvec(CPURISCVState *env, int csrno,
 +                                   target_ulong val)
  {
      env->vstvec = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
 +                                     target_ulong *val)
  {
      *val = env->vsscratch;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
 +                                      target_ulong val)
  {
      env->vsscratch = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vsepc(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->vsepc;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vsepc(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      env->vsepc = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vscause(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      *val = env->vscause;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vscause(CPURISCVState *env, int csrno,
 +                                    target_ulong val)
  {
      env->vscause = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vstval(CPURISCVState *env, int csrno,
 +                                  target_ulong *val)
  {
      *val = env->vstval;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vstval(CPURISCVState *env, int csrno,
 +                                   target_ulong val)
  {
      env->vstval = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_vsatp(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
  {
      *val = env->vsatp;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_vsatp(CPURISCVState *env, int csrno,
 +                                  target_ulong val)
  {
      env->vsatp = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mtval2(CPURISCVState *env, int csrno,
 +                                  target_ulong *val)
  {
      *val = env->mtval2;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mtval2(CPURISCVState *env, int csrno,
 +                                   target_ulong val)
  {
      env->mtval2 = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_mtinst(CPURISCVState *env, int csrno,
 +                                  target_ulong *val)
  {
      *val = env->mtinst;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_mtinst(CPURISCVState *env, int csrno,
 +                                   target_ulong val)
  {
      env->mtinst = val;
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /* Physical Memory Protection */
 -static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
 +                                  target_ulong *val)
  {
      *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
 +                                   target_ulong val)
  {
      pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
 +static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
  {
      *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
 -static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
 +static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
 +                                    target_ulong val)
  {
      pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  #endif
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
      /* execute combined read/write operation if it exists */
      if (csr_ops[csrno].op) {
 -        return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
 +        ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
 +        if (ret != RISCV_EXCP_NONE) {
 +            return -ret;
 +        }
 +        return 0;
      }
      /* if no accessor exists then return failure */
      if (!csr_ops[csrno].read) {
          return -RISCV_EXCP_ILLEGAL_INST;
      }
 -
      /* read old value */
      ret = csr_ops[csrno].read(env, csrno, &old_value);
 -    if (ret < 0) {
 -        return ret;
 +    if (ret != RISCV_EXCP_NONE) {
 +        return -ret;
      }
      /* write value if writable and write mask set, otherwise drop writes */
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
          new_value = (old_value & ~write_mask) | (new_value & write_mask);
          if (csr_ops[csrno].write) {
              ret = csr_ops[csrno].write(env, csrno, new_value);
 -            if (ret < 0) {
 -                return ret;
 +            if (ret != RISCV_EXCP_NONE) {
 +                return -ret;
              }
          }
      }
 --
-.45.1
+.31.1

-[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
+[PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
 ---
  target/riscv/cpu.h       | 11 +++++++----
  target/riscv/csr.c       | 37 ++++++++++++++++++-------------------
  target/riscv/gdbstub.c   |  8 ++++----
  target/riscv/op_helper.c | 18 +++++++++---------
 files changed, 38 insertions(+), 36 deletions(-)
-Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-in bytes, when in this context we want 'reg_width' as the length in
+index XXXXXXX..XXXXXXX 100644
-bits.
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
-Fix 'reg_width' back to the value in bits like 7cb59921c05a
+@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
+     *pflags = flags;
-beforehand.
+ }
-While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
+-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
-clarity about what the variable represents. 'bitsize' is also used in
+-                target_ulong new_value, target_ulong write_mask);
-riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
+-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
-gdb_feature_builder_append_reg().
+-                      target_ulong new_value, target_ulong write_mask);
++RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
-Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
++                           target_ulong *ret_value,
-Cc: Alex Bennée <alex.bennee@linaro.org>
++                           target_ulong new_value, target_ulong write_mask);
-Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
++RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
-Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
++                                 target_ulong *ret_value,
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
++                                 target_ulong new_value,
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
++                                 target_ulong write_mask);
-Acked-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
+ static inline void riscv_csr_write(CPURISCVState *env, int csrno,
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+                                    target_ulong val)
-Cc: qemu-stable <qemu-stable@nongnu.org>
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
-Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
+index XXXXXXX..XXXXXXX 100644
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+--- a/target/riscv/csr.c
----
++++ b/target/riscv/csr.c
- target/riscv/gdbstub.c | 6 +++---
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
-file changed, 3 insertions(+), 3 deletions(-)
+  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
+  */
 -int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 -                target_ulong new_value, target_ulong write_mask)
 +RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
 +                           target_ulong *ret_value,
 +                           target_ulong new_value, target_ulong write_mask)
  {
 -    int ret;
 +    RISCVException ret;
      target_ulong old_value;
      RISCVCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
      if ((write_mask && read_only) ||
          (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
  #endif
      /* ensure the CSR extension is enabled. */
      if (!cpu->cfg.ext_icsr) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      /* check predicate */
      if (!csr_ops[csrno].predicate) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      ret = csr_ops[csrno].predicate(env, csrno);
      if (ret != RISCV_EXCP_NONE) {
 -        return -ret;
 +        return ret;
      }
      /* execute combined read/write operation if it exists */
      if (csr_ops[csrno].op) {
 -        ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
 -        if (ret != RISCV_EXCP_NONE) {
 -            return -ret;
 -        }
 -        return 0;
 +        return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
      }
      /* if no accessor exists then return failure */
      if (!csr_ops[csrno].read) {
 -        return -RISCV_EXCP_ILLEGAL_INST;
 +        return RISCV_EXCP_ILLEGAL_INST;
      }
      /* read old value */
      ret = csr_ops[csrno].read(env, csrno, &old_value);
      if (ret != RISCV_EXCP_NONE) {
 -        return -ret;
 +        return ret;
      }
      /* write value if writable and write mask set, otherwise drop writes */
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
          if (csr_ops[csrno].write) {
              ret = csr_ops[csrno].write(env, csrno, new_value);
              if (ret != RISCV_EXCP_NONE) {
 -                return -ret;
 +                return ret;
              }
          }
      }
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
          *ret_value = old_value;
      }
 -    return 0;
 +    return RISCV_EXCP_NONE;
  }
  /*
   * Debugger support.  If not in user mode, set env->debugger before the
   * riscv_csrrw call and clear it after the call.
   */
 -int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
 -                target_ulong new_value, target_ulong write_mask)
 +RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
 +                                 target_ulong *ret_value,
 +                                 target_ulong new_value,
 +                                 target_ulong write_mask)
  {
 -    int ret;
 +    RISCVException ret;
  #if !defined(CONFIG_USER_ONLY)
      env->debugger = true;
  #endif
 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/gdbstub.c
 +++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
+@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
- static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
+          */
- {
+         result = riscv_csrrw_debug(env, n - 32, &val,
-     RISCVCPU *cpu = RISCV_CPU(cs);
+, 0);
--    int reg_width = cpu->cfg.vlenb;
+-        if (result == 0) {
-+    int bitsize = cpu->cfg.vlenb << 3;
++        if (result == RISCV_EXCP_NONE) {
-     GDBFeatureBuilder builder;
+             return gdb_get_regl(buf, val);
-     int i;
+         }
+     }
-@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
+@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+          */
-     /* First define types and totals in a whole VL */
+         result = riscv_csrrw_debug(env, n - 32, NULL,
-     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+                                    val, -1);
--        int count = reg_width / vec_lanes[i].size;
+-        if (result == 0) {
-+        int count = bitsize / vec_lanes[i].size;
++        if (result == RISCV_EXCP_NONE) {
-         gdb_feature_builder_append_tag(
+             return sizeof(target_ulong);
-             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
+         }
-             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
+     }
-@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
+@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
-     /* Define vector registers */
+         int result;
-     for (i = 0; i < 32; i++) {
-         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
+         result = riscv_csrrw_debug(env, n, &val, 0, 0);
--                                       reg_width, i, "riscv_vector", "vector");
+-        if (result == 0) {
-+                                       bitsize, i, "riscv_vector", "vector");
++        if (result == RISCV_EXCP_NONE) {
-     }
+             return gdb_get_regl(buf, val);
+         }
-     gdb_feature_builder_end(&builder);
+     }
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
          int result;
          result = riscv_csrrw_debug(env, n, NULL, val, -1);
 -        if (result == 0) {
 +        if (result == RISCV_EXCP_NONE) {
              return sizeof(target_ulong);
          }
      }
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
          target_ulong csr)
  {
      target_ulong val = 0;
 -    int ret = riscv_csrrw(env, csr, &val, src, -1);
 +    RISCVException ret = riscv_csrrw(env, csr, &val, src, -1);
 -    if (ret < 0) {
 -        riscv_raise_exception(env, -ret, GETPC());
 +    if (ret != RISCV_EXCP_NONE) {
 +        riscv_raise_exception(env, ret, GETPC());
      }
      return val;
  }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
          target_ulong csr, target_ulong rs1_pass)
  {
      target_ulong val = 0;
 -    int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
 +    RISCVException ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
 -    if (ret < 0) {
 -        riscv_raise_exception(env, -ret, GETPC());
 +    if (ret != RISCV_EXCP_NONE) {
 +        riscv_raise_exception(env, ret, GETPC());
      }
      return val;
  }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
          target_ulong csr, target_ulong rs1_pass)
  {
      target_ulong val = 0;
 -    int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
 +    RISCVException ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
 -    if (ret < 0) {
 -        riscv_raise_exception(env, -ret, GETPC());
 +    if (ret != RISCV_EXCP_NONE) {
 +        riscv_raise_exception(env, ret, GETPC());
      }
      return val;
  }
 --
-.45.1
+.31.1

-New patch
+[PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers
+Update the RISC-V maintainers by removing Sagar and Bastian who haven't
+been involved recently.
+Also add Bin who has been helping with reviews.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Acked-by: Bin Meng <bin.meng@windriver.com>
+Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
+---
+ MAINTAINERS | 5 ++---
+file changed, 2 insertions(+), 3 deletions(-)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: tests/acceptance/machine_ppc.py
+ RISC-V TCG CPUs
+ M: Palmer Dabbelt <palmer@dabbelt.com>
+-M: Alistair Francis <Alistair.Francis@wdc.com>
+-M: Sagar Karandikar <sagark@eecs.berkeley.edu>
+-M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
++M: Alistair Francis <alistair.francis@wdc.com>
++M: Bin Meng <bin.meng@windriver.com>
+ L: qemu-riscv@nongnu.org
+ S: Supported
+ F: target/riscv/
+--
+.31.1

-New patch
+[PULL v2 15/42] hw/opentitan: Update the interrupt layout
+Update the OpenTitan interrupt layout to match the latest OpenTitan
+bitstreams. This involves changing the Ibex PLIC memory layout and the
+UART interrupts.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
+---
+ include/hw/riscv/opentitan.h | 16 ++++++++--------
+ hw/intc/ibex_plic.c          | 20 ++++++++++----------
+ hw/riscv/opentitan.c         |  8 ++++----
+files changed, 22 insertions(+), 22 deletions(-)
+diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/riscv/opentitan.h
++++ b/include/hw/riscv/opentitan.h
+@@ -XXX,XX +XXX,XX @@ enum {
+ };
+ enum {
+-    IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
+-    IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
+-    IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
+-    IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
+-    IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
+-    IBEX_UART_TX_EMPTY_IRQ = 0x23,
+-    IBEX_UART_RX_WATERMARK_IRQ = 0x22,
+-    IBEX_UART_TX_WATERMARK_IRQ = 0x21,
++    IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
++    IBEX_UART0_RX_TIMEOUT_IRQ = 7,
++    IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
++    IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
++    IBEX_UART0_RX_OVERFLOW_IRQ = 4,
++    IBEX_UART0_TX_EMPTY_IRQ = 3,
++    IBEX_UART0_RX_WATERMARK_IRQ = 2,
++    IBEX_UART0_TX_WATERMARK_IRQ = 1,
+ };
+ #endif
+diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/ibex_plic.c
++++ b/hw/intc/ibex_plic.c
+@@ -XXX,XX +XXX,XX @@ static void ibex_plic_irq_request(void *opaque, int irq, int level)
+ static Property ibex_plic_properties[] = {
+     DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
+-    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
++    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
+     DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
+-    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
++    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
+-    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
+-    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
++    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
++    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
+-    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
+-    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
++    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
++    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
+-    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
+-    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
++    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
++    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
+-    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
++    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
+-    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
++    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
+     DEFINE_PROP_END_OF_LIST(),
+ };
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/opentitan.c
++++ b/hw/riscv/opentitan.c
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+, qdev_get_gpio_in(DEVICE(&s->plic),
+-                       IBEX_UART_TX_WATERMARK_IRQ));
++                       IBEX_UART0_TX_WATERMARK_IRQ));
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+, qdev_get_gpio_in(DEVICE(&s->plic),
+-                       IBEX_UART_RX_WATERMARK_IRQ));
++                       IBEX_UART0_RX_WATERMARK_IRQ));
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+, qdev_get_gpio_in(DEVICE(&s->plic),
+-                       IBEX_UART_TX_EMPTY_IRQ));
++                       IBEX_UART0_TX_EMPTY_IRQ));
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
+, qdev_get_gpio_in(DEVICE(&s->plic),
+-                       IBEX_UART_RX_OVERFLOW_IRQ));
++                       IBEX_UART0_RX_OVERFLOW_IRQ));
+     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
+         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
+--
+.31.1

-New patch
+[PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
+imply VIRTIO_VGA for the virt machine, this fixes the following error
+when specifying `-vga virtio` as a command line argument:
+qemu-system-riscv64: Virtio VGA not available
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 7ac26fafee8bd59d2a0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com
+---
+ hw/riscv/Kconfig | 1 +
+file changed, 1 insertion(+)
+diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/Kconfig
++++ b/hw/riscv/Kconfig
+@@ -XXX,XX +XXX,XX @@ config SHAKTI_C
+ config RISCV_VIRT
+     bool
+     imply PCI_DEVICES
++    imply VIRTIO_VGA
+     imply TEST_DEVICES
+     select GOLDFISH_RTC
+     select MSI_NONBROKEN
+--
+.31.1

-[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
+[PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context
-From: Alexei Filippov <alexei.filippov@syntacore.com>
+From: Jade Fink <qemu@jade.fyi>
-Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
+Previously the qemu monitor and gdbstub looked at SUM and refused to
-setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
+perform accesses to user memory if it is off, which was an impediment to
-translation part, mtval2 will be set in case of successes 2 stage translation but
+debugging.
 failed pmp check.
-In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
+Signed-off-by: Jade Fink <qemu@jade.fyi>
 riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
 page-fault is taken into M-mode, mtval2 is written with either zero or guest
 physical address that faulted, shifted by 2 bits. *For other traps, mtval2
 is set to zero...*
 Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
+Message-id: 20210406113109.1031033-1-qemu@jade.fyi
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 12 ++++++------
+ target/riscv/cpu_helper.c | 20 ++++++++++++--------
-file changed, 6 insertions(+), 6 deletions(-)
+file changed, 12 insertions(+), 8 deletions(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+  * @first_stage: Are we in first stage translation?
+  *               Second stage is used for hypervisor guest translation
+  * @two_stage: Are we going to perform two stage translation
++ * @is_debug: Is this access from a debugger or the monitor?
+  */
+ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+                                 int *prot, target_ulong addr,
+                                 target_ulong *fault_pte_addr,
+                                 int access_type, int mmu_idx,
+-                                bool first_stage, bool two_stage)
++                                bool first_stage, bool two_stage,
++                                bool is_debug)
+ {
+     /* NOTE: the env->pc value visible here will not be
+      * correct, but the value visible to the exception handler
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+         widened = 2;
+     }
+     /* status.SUM will be ignored if execute on background */
+-    sum = get_field(env->mstatus, MSTATUS_SUM) || use_background;
++    sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
+     switch (vm) {
+     case VM_1_10_SV32:
+       levels = 2; ptidxbits = 10; ptesize = 4; break;
+@@ -XXX,XX +XXX,XX @@ restart:
+             /* Do the second stage translation on the base PTE address. */
+             int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
+                                                  base, NULL, MMU_DATA_LOAD,
+-                                                 mmu_idx, false, true);
++                                                 mmu_idx, false, true,
++                                                 is_debug);
+             if (vbase_ret != TRANSLATE_SUCCESS) {
+                 if (fault_pte_addr) {
+@@ -XXX,XX +XXX,XX @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+     int mmu_idx = cpu_mmu_index(&cpu->env, false);
+     if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
+-                             true, riscv_cpu_virt_enabled(env))) {
++                             true, riscv_cpu_virt_enabled(env), true)) {
+         return -1;
+     }
+     if (riscv_cpu_virt_enabled(env)) {
+         if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
+-                                 0, mmu_idx, false, true)) {
++                                 0, mmu_idx, false, true, true)) {
+             return -1;
+         }
+     }
 @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                               __func__, pa, ret, prot_pmp, tlb_size);
+         /* Two stage lookup */
+         ret = get_physical_address(env, &pa, &prot, address,
-                 prot &= prot_pmp;
+                                    &env->guest_phys_fault_addr, access_type,
--            }
+-                                   mmu_idx, true, true);
--
++                                   mmu_idx, true, true, false);
--            if (ret != TRANSLATE_SUCCESS) {
-+            } else {
+         /*
-                 /*
+          * A G-stage exception may be triggered during two state lookup.
-                  * Guest physical address translation failed, this is a HS
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                  * level exception
+             im_address = pa;
-                  */
-                 first_stage_error = false;
+             ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
--                env->guest_phys_fault_addr = (im_address |
+-                                       access_type, mmu_idx, false, true);
--                                              (address &
++                                       access_type, mmu_idx, false, true,
--                                               (TARGET_PAGE_SIZE - 1))) >> 2;
++                                       false);
-+                if (ret != TRANSLATE_PMP_FAIL) {
-+                    env->guest_phys_fault_addr = (im_address |
+             qemu_log_mask(CPU_LOG_MMU,
-+                                                  (address &
+                     "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
-+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 +                }
              }
          }
      } else {
+         /* Single stage lookup */
+         ret = get_physical_address(env, &pa, &prot, address, NULL,
+-                                   access_type, mmu_idx, true, false);
++                                   access_type, mmu_idx, true, false, false);
+         qemu_log_mask(CPU_LOG_MMU,
+                       "%s address=%" VADDR_PRIx " ret %d physical "
 --
-.45.1
+.31.1

-[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
+[PULL v2 18/42] target/riscv: Fixup saturate subtract function
-From: "yang.zhang" <yang.zhang@hexintek.com>
+From: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Since only root APLICs can have hw IRQ lines, aplic->parent should
+The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
-be initialized first.
+However, when the predication is ture and a is 0, it should return maximum.
-Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
+Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com
 Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/intc/riscv_aplic.c | 8 ++++----
+ target/riscv/vector_helper.c | 8 ++++----
 file changed, 4 insertions(+), 4 deletions(-)
-diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/riscv_aplic.c
+--- a/target/riscv/vector_helper.c
-+++ b/hw/intc/riscv_aplic.c
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+@@ -XXX,XX +XXX,XX @@ static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
-     qdev_prop_set_bit(dev, "msimode", msimode);
+ {
-     qdev_prop_set_bit(dev, "mmode", mmode);
+     int8_t res = a - b;
+     if ((res ^ a) & (a ^ b) & INT8_MIN) {
-+    if (parent) {
+-        res = a > 0 ? INT8_MAX : INT8_MIN;
-+        riscv_aplic_add_child(parent, dev);
++        res = a >= 0 ? INT8_MAX : INT8_MIN;
-+    }
+         env->vxsat = 0x1;
 +
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      if (!is_kvm_aia(msimode)) {
          sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
      }
+     return res;
--    if (parent) {
+@@ -XXX,XX +XXX,XX @@ static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
--        riscv_aplic_add_child(parent, dev);
+ {
--    }
+     int16_t res = a - b;
--
+     if ((res ^ a) & (a ^ b) & INT16_MIN) {
-     if (!msimode) {
+-        res = a > 0 ? INT16_MAX : INT16_MIN;
-         for (i = 0; i < num_harts; i++) {
++        res = a >= 0 ? INT16_MAX : INT16_MIN;
-             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
+         env->vxsat = 0x1;
      }
      return res;
@@ -XXX,XX +XXX,XX @@ static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
  {
      int32_t res = a - b;
      if ((res ^ a) & (a ^ b) & INT32_MIN) {
 -        res = a > 0 ? INT32_MAX : INT32_MIN;
 +        res = a >= 0 ? INT32_MAX : INT32_MIN;
          env->vxsat = 0x1;
      }
      return res;
@@ -XXX,XX +XXX,XX @@ static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
  {
      int64_t res = a - b;
      if ((res ^ a) & (a ^ b) & INT64_MIN) {
 -        res = a > 0 ? INT64_MAX : INT64_MIN;
 +        res = a >= 0 ? INT64_MAX : INT64_MIN;
          env->vxsat = 0x1;
      }
      return res;
 --
-.45.1
+.31.1

-[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
+[PULL v2 19/42] docs: Add documentation for shakti_c machine
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Vijai Kumar K <vijai@behindbytes.com>
-Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
+Add documentation for Shakti C reference platform.
 enabled, will fail with a kernel oops SIGILL right at the start. The
 reason is that we can't expose zkr without implementing the SEED CSR.
 Disabling zkr in the guest would be a workaround, but if the KVM doesn't
 allow it we'll error out and never boot.
-In hindsight this is too strict. If we keep proceeding, despite not
+Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
-disabling the extension in the KVM vcpu, we'll not add the extension in
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-the riscv,isa. The guest kernel will be unaware of the extension, i.e.
+Message-id: 20210412174248.8668-1-vijai@behindbytes.com
-it doesn't matter if the KVM vcpu has it enabled underneath or not. So
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
-it's ok to keep booting in this case.
+[ Changes from Bin Meng:
+ - Add missing TOC
-Change our current logic to not error out if we fail to disable an
+ Message-id: 20210430070534.1487242-1-bmeng.cn@gmail.com
-extension in kvm_set_one_reg(), but show a warning and keep booting. It
+]
 is important to throw a warning because we must make the user aware that
 the extension is still available in the vcpu, meaning that an
 ill-behaved guest can ignore the riscv,isa settings and  use the
 extension.
 The case we're handling happens with an EINVAL error code. If we fail to
 disable the extension in KVM for any other reason, error out.
 We'll also keep erroring out when we fail to enable an extension in KVM,
 since adding the extension in riscv,isa at this point will cause a guest
 malfunction because the extension isn't enabled in the vcpu.
 Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
+ docs/system/riscv/shakti-c.rst | 82 ++++++++++++++++++++++++++++++++++
-file changed, 8 insertions(+), 4 deletions(-)
+ docs/system/target-riscv.rst   |  1 +
 files changed, 83 insertions(+)
  create mode 100644 docs/system/riscv/shakti-c.rst
-diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+diff --git a/docs/system/riscv/shakti-c.rst b/docs/system/riscv/shakti-c.rst
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/riscv/shakti-c.rst
@@ -XXX,XX +XXX,XX @@
 +Shakti C Reference Platform (``shakti_c``)
 +==========================================
 +
 +Shakti C Reference Platform is a reference platform based on arty a7 100t
 +for the Shakti SoC.
 +
 +Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
 +is a 64bit RV64GCSUN processor core.
 +
 +For more details on Shakti SoC, please see:
 +https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/README.rst
 +
 +For more info on the Shakti C-class core, please see:
 +https://c-class.readthedocs.io/en/latest/
 +
 +Supported devices
 +-----------------
 +
 +The ``shakti_c`` machine supports the following devices:
 +
 + * 1 C-class core
 + * Core Level Interruptor (CLINT)
 + * Platform-Level Interrupt Controller (PLIC)
 + * 1 UART
 +
 +Boot options
 +------------
 +
 +The ``shakti_c`` machine can start using the standard -bios
 +functionality for loading the baremetal application or opensbi.
 +
 +Boot the machine
 +----------------
 +
 +Shakti SDK
 +~~~~~~~~~~
 +Shakti SDK can be used to generate the baremetal example UART applications.
 +
 +.. code-block:: bash
 +
 +   $ git clone https://gitlab.com/behindbytes/shakti-sdk.git
 +   $ cd shakti-sdk
 +   $ make software PROGRAM=loopback TARGET=artix7_100t
 +
 +Binary would be generated in:
 +  software/examples/uart_applns/loopback/output/loopback.shakti
 +
 +You could also download the precompiled example applicatons using below
 +commands.
 +
 +.. code-block:: bash
 +
 +   $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/sdk/shakti_sdk_qemu.zip
 +   $ unzip shakti_sdk_qemu.zip
 +
 +Then we can run the UART example using:
 +
 +.. code-block:: bash
 +
 +   $ qemu-system-riscv64 -M shakti_c -nographic \
 +      -bios path/to/shakti_sdk_qemu/loopback.shakti
 +
 +OpenSBI
 +~~~~~~~
 +We can also run OpenSBI with Test Payload.
 +
 +.. code-block:: bash
 +
 +   $ git clone https://github.com/riscv/opensbi.git -b v0.9
 +   $ cd opensbi
 +   $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/dts/shakti.dtb
 +   $ export CROSS_COMPILE=riscv64-unknown-elf-
 +   $ export FW_FDT_PATH=./shakti.dtb
 +   $ make PLATFORM=generic
 +
 +fw_payload.elf would be generated in build/platform/generic/firmware/fw_payload.elf.
 +Boot it using the below qemu command.
 +
 +.. code-block:: bash
 +
 +   $ qemu-system-riscv64 -M shakti_c -nographic \
 +      -bios path/to/fw_payload.elf
 diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm/kvm-cpu.c
+--- a/docs/system/target-riscv.rst
-+++ b/target/riscv/kvm/kvm-cpu.c
++++ b/docs/system/target-riscv.rst
-@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
-         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
+    :maxdepth: 1
-         ret = kvm_set_one_reg(cs, id, &reg);
-         if (ret != 0) {
+    riscv/microchip-icicle-kit
--            error_report("Unable to %s extension %s in KVM, error %d",
++   riscv/shakti-c
--                         reg ? "enable" : "disable",
+    riscv/sifive_u
--                         multi_ext_cfg->name, ret);
--            exit(EXIT_FAILURE);
+ RISC-V CPU features
 +            if (!reg && ret == -EINVAL) {
 +                warn_report("KVM cannot disable extension %s",
 +                            multi_ext_cfg->name);
 +            } else {
 +                error_report("Unable to enable extension %s in KVM, error %d",
 +                             multi_ext_cfg->name, ret);
 +                exit(EXIT_FAILURE);
 +            }
          }
      }
  }
 --
-.45.1
+.31.1

-[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
+[PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+The RISC-V spec says:
     if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
     pmpaddri-1 are ignored.
-SBI defines a Debug Console extension "DBCN" that will, in time, replace
+The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
-the legacy console putchar and getchar SBI extensions.
+is incorrect.
-The appeal of the DBCN extension is that it allows multiple bytes to be
+Update the pmp_is_locked() function to not check the supporting fields
-read/written in the SBI console in a single SBI call.
+and instead enforce the lock functionality in the pmpaddr write operation.
-As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-module to userspace. But this will only happens if the KVM module
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-actually supports this SBI extension and we activate it.
+Message-id: 2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com
 ---
  target/riscv/pmp.c | 26 ++++++++++++++++----------
 file changed, 16 insertions(+), 10 deletions(-)
-We'll check for DBCN support during init time, checking if get-reg-list
+diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
 kvm_set_one_reg() during kvm_arch_init_vcpu().
 Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
 SBI_EXT_DBCN, reading and writing as required.
 A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/sbi_ecall_interface.h |  17 +++++
  target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 files changed, 128 insertions(+)
 diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/sbi_ecall_interface.h
+--- a/target/riscv/pmp.c
-+++ b/target/riscv/sbi_ecall_interface.h
++++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
+         return 0;
- /* clang-format off */
+     }
-+#define SBI_SUCCESS                      0
+-    /* In TOR mode, need to check the lock bit of the next pmp
-+#define SBI_ERR_FAILED                  -1
+-     * (if there is a next)
-+#define SBI_ERR_NOT_SUPPORTED           -2
+-     */
-+#define SBI_ERR_INVALID_PARAM           -3
+-    const uint8_t a_field =
-+#define SBI_ERR_DENIED                  -4
+-        pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
-+#define SBI_ERR_INVALID_ADDRESS         -5
+-    if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
-+#define SBI_ERR_ALREADY_AVAILABLE       -6
+-         (PMP_AMATCH_TOR == a_field)) {
-+#define SBI_ERR_ALREADY_STARTED         -7
+-        return 1;
-+#define SBI_ERR_ALREADY_STOPPED         -8
+-    }
-+#define SBI_ERR_NO_SHMEM                -9
+-
 +
  /* SBI Extension IDs */
  #define SBI_EXT_0_1_SET_TIMER           0x0
  #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_IPI                     0x735049
  #define SBI_EXT_RFENCE                  0x52464E43
  #define SBI_EXT_HSM                     0x48534D
 +#define SBI_EXT_DBCN                    0x4442434E
  /* SBI function IDs for BASE extension */
  #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_HSM_HART_STOP           0x1
  #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +/* SBI function IDs for DBCN extension */
 +#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
 +#define SBI_EXT_DBCN_CONSOLE_READ       0x1
 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
 +
  #define SBI_HSM_HART_STATUS_STARTED     0x0
  #define SBI_HSM_HART_STATUS_STOPPED     0x1
  #define SBI_HSM_HART_STATUS_START_PENDING   0x2
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                     KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
  };
 +static KVMCPUConfig kvm_sbi_dbcn = {
 +    .name = "sbi_dbcn",
 +    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
 +                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
 +};
 +
  static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
  {
      CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
      return 0;
  }
-+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
-+                                             KVMScratchCPU *kvmcpu,
+     target_ulong val)
-+                                             struct kvm_reg_list *reglist)
+ {
-+{
+     trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
 +    struct kvm_reg_list *reg_search;
 +
-+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+     if (addr_index < MAX_RISCV_PMPS) {
-+                         sizeof(uint64_t), uint64_cmp);
++        /*
 +         * In TOR mode, need to check the lock bit of the next pmp
 +         * (if there is a next).
 +         */
 +        if (addr_index + 1 < MAX_RISCV_PMPS) {
 +            uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
 +
-+    if (reg_search) {
++            if (pmp_cfg & PMP_LOCK &&
-+        kvm_sbi_dbcn.supported = true;
++                PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg)) {
-+    }
++                qemu_log_mask(LOG_GUEST_ERROR,
-+}
++                              "ignoring pmpaddr write - pmpcfg + 1 locked\n");
-+
++                return;
  static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                   struct kvm_reg_list *reglist)
  {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      if (riscv_has_ext(&cpu->env, RVV)) {
          kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
      }
 +
 +    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
  }
  static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
      return ret;
  }
 +static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
 +{
 +    target_ulong reg = 1;
 +
 +    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
 +    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +}
 +
  int kvm_arch_init_vcpu(CPUState *cs)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      kvm_riscv_update_cpu_misa_ext(cpu, cs);
      kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 +    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
 +
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
 +static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
 +{
 +    g_autofree uint8_t *buf = NULL;
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    target_ulong num_bytes;
 +    uint64_t addr;
 +    unsigned char ch;
 +    int ret;
 +
 +    switch (run->riscv_sbi.function_id) {
 +    case SBI_EXT_DBCN_CONSOLE_READ:
 +    case SBI_EXT_DBCN_CONSOLE_WRITE:
 +        num_bytes = run->riscv_sbi.args[0];
 +
 +        if (num_bytes == 0) {
 +            run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +            run->riscv_sbi.ret[1] = 0;
 +            break;
 +        }
 +
 +        addr = run->riscv_sbi.args[1];
 +
 +        /*
 +         * Handle the case where a 32 bit CPU is running in a
 +         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
 +            cpu_physical_memory_read(addr, buf, num_bytes);
 +
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
-+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+         if (!pmp_is_locked(env, addr_index)) {
-+        run->riscv_sbi.ret[1] = ret;
+             env->pmp_state.pmp[addr_index].addr_reg = val;
-+        break;
+             pmp_update_rule(env, addr_index);
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
 +        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +
 +        if (ret < 0) {
 +            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
 +                         "writing chardev");
 +            exit(1);
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
 +        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
 +    }
 +}
 +
  static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
          }
          ret = 0;
          break;
 +    case SBI_EXT_DBCN:
 +        kvm_riscv_handle_sbi_dbcn(cs, run);
 +        break;
      default:
          qemu_log_mask(LOG_UNIMP,
                        "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 --
-.45.1
+.31.1

-New patch
+[PULL v2 21/42] target/riscv: Define ePMP mseccfg
+From: Hou Weiying <weiying_hou@outlook.com>
+Use address 0x390 and 0x391 for the ePMP CSRs.
+Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
+Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
+Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
+[ Changes by AF:
+ - Tidy up commit message
+]
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+---
+ target/riscv/cpu_bits.h | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define CSR_MTINST          0x34a
+ #define CSR_MTVAL2          0x34b
++/* Enhanced Physical Memory Protection (ePMP) */
++#define CSR_MSECCFG         0x390
++#define CSR_MSECCFGH        0x391
+ /* Physical Memory Protection */
+ #define CSR_PMPCFG0         0x3a0
+ #define CSR_PMPCFG1         0x3a1
+--
+.31.1

-[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+[PULL v2 22/42] target/riscv: Add the ePMP feature
-From: Max Chou <max.chou@sifive.com>
+The spec is avaliable at:
 https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
-The opfv_narrow_check needs to check the single width float operator by
-require_rvf.
-Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 28c8855c80b0388a08c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 1 +
+ target/riscv/cpu.h | 1 +
 file changed, 1 insertion(+)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
+--- a/target/riscv/cpu.h
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+@@ -XXX,XX +XXX,XX @@
- static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
+ enum {
- {
+     RISCV_FEATURE_MMU,
-     return opfv_narrow_check(s, a) &&
+     RISCV_FEATURE_PMP,
-+           require_rvf(s) &&
++    RISCV_FEATURE_EPMP,
-            require_scale_rvf(s) &&
+     RISCV_FEATURE_MISA
-            (s->sew != MO_8);
+ };
- }
 --
-.45.1
+.31.1

-[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
+[PULL v2 23/42] target/riscv: Add ePMP CSR access functions
-From: Yu-Ming Chang <yumin686@andestech.com>
+From: Hou Weiying <weiying_hou@outlook.com>
-Both CSRRS and CSRRC always read the addressed CSR and cause any read side
+Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
-effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
+Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
-holding a zero value other than x0, the instruction will still attempt to write
+Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
 the unmodified value back to the CSR and will cause any attendant side effects.
 So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
 a register holding a zero value, an illegal instruction exception should be
 raised.
 Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com
+[ Changes by AF:
+ - Rebase on master
+ - Fix build errors
+ - Fix some style issues
+]
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 ---
- target/riscv/cpu.h       |  4 ++++
+ target/riscv/cpu.h        |  1 +
- target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
+ target/riscv/pmp.h        | 14 ++++++++++++++
- target/riscv/op_helper.c |  6 ++---
+ target/riscv/csr.c        | 24 ++++++++++++++++++++++++
-files changed, 53 insertions(+), 8 deletions(-)
+ target/riscv/pmp.c        | 34 ++++++++++++++++++++++++++++++++++
  target/riscv/trace-events |  3 +++
 files changed, 76 insertions(+)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
- void riscv_cpu_update_mask(CPURISCVState *env);
- bool riscv_cpu_is_32bit(RISCVCPU *cpu);
+     /* physical memory protection */
+     pmp_table_t pmp_state;
-+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
++    target_ulong mseccfg;
-+                          target_ulong *ret_value);
- RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+     /* machine specific rdtime callback */
-                            target_ulong *ret_value,
+     uint64_t (*rdtime_fn)(uint32_t);
-                            target_ulong new_value, target_ulong write_mask);
+diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
-@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+index XXXXXXX..XXXXXXX 100644
-                                           target_ulong new_value,
+--- a/target/riscv/pmp.h
-                                           target_ulong write_mask);
++++ b/target/riscv/pmp.h
+@@ -XXX,XX +XXX,XX @@ typedef enum {
-+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+     PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
-+                               Int128 *ret_value);
+ } pmp_am_t;
- RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
-                                 Int128 *ret_value,
++typedef enum {
-                                 Int128 new_value, Int128 write_mask);
++    MSECCFG_MML  = 1 << 0,
 +    MSECCFG_MMWP = 1 << 1,
 +    MSECCFG_RLB  = 1 << 2
 +} mseccfg_field_t;
 +
  typedef struct {
      target_ulong addr_reg;
      uint8_t  cfg_reg;
@@ -XXX,XX +XXX,XX @@ typedef struct {
  void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
      target_ulong val);
  target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
 +
 +void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
 +target_ulong mseccfg_csr_read(CPURISCVState *env);
 +
  void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
      target_ulong val);
  target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_nums(CPURISCVState *env);
  uint32_t pmp_get_num_rules(CPURISCVState *env);
  int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 +#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
 +#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
 +#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
 +
  #endif
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
- static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
+     return RISCV_EXCP_ILLEGAL_INST;
                                                 int csrno,
 -                                               bool write_mask)
 +                                               bool write)
  {
      /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
      bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
      }
      /* read / write check */
 -    if (write_mask && read_only) {
 +    if (write && read_only) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
++
-+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
++static RISCVException epmp(CPURISCVState *env, int csrno)
 +                           target_ulong *ret_value)
 +{
-+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
++    if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
-+    if (ret != RISCV_EXCP_NONE) {
++        return RISCV_EXCP_NONE;
 +        return ret;
 +    }
 +
-+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
++    return RISCV_EXCP_ILLEGAL_INST;
 +}
  #endif
  /* User Floating-Point CSRs */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtinst(CPURISCVState *env, int csrno,
  }
  /* Physical Memory Protection */
 +static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
 +{
 +    *val = mseccfg_csr_read(env);
 +    return RISCV_EXCP_NONE;
 +}
 +
- RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
++static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
-                            target_ulong *ret_value,
++                         target_ulong val)
-                            target_ulong new_value, target_ulong write_mask)
++{
 +    mseccfg_csr_write(env, val);
 +    return RISCV_EXCP_NONE;
 +}
 +
  static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
                                    target_ulong *val)
  {
--    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
-+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
+     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
-     if (ret != RISCV_EXCP_NONE) {
-         return ret;
+     /* Physical Memory Protection */
-     }
++    [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
-@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
+     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
-     return RISCV_EXCP_NONE;
+     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
      [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.c
 +++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
      return val;
  }
-+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
++/*
-+                               Int128 *ret_value)
++ * Handle a write to a mseccfg CSR
 + */
 +void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
 +{
-+    RISCVException ret;
++    int i;
 +
-+    ret = riscv_csrrw_check(env, csrno, false);
++    trace_mseccfg_csr_write(env->mhartid, val);
-+    if (ret != RISCV_EXCP_NONE) {
++
-+        return ret;
++    /* RLB cannot be enabled if it's already 0 and if any regions are locked */
 +    if (!MSECCFG_RLB_ISSET(env)) {
 +        for (i = 0; i < MAX_RISCV_PMPS; i++) {
 +            if (pmp_is_locked(env, i)) {
 +                val &= ~MSECCFG_RLB;
 +                break;
 +            }
 +        }
 +    }
 +
-+    if (csr_ops[csrno].read128) {
++    /* Sticky bits */
-+        return riscv_csrrw_do128(env, csrno, ret_value,
++    val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
 +                                 int128_zero(), int128_zero());
 +    }
 +
-+    /*
++    env->mseccfg = val;
 +     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
 +     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
 +    target_ulong old_value;
 +    ret = riscv_csrrw_do64(env, csrno, &old_value,
 +                           (target_ulong)0,
 +                           (target_ulong)0);
 +    if (ret == RISCV_EXCP_NONE && ret_value) {
 +        *ret_value = int128_make64(old_value);
 +    }
 +    return ret;
 +}
 +
- RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
++/*
-                                 Int128 *ret_value,
++ * Handle a read from a mseccfg CSR
-                                 Int128 new_value, Int128 write_mask)
++ */
- {
++target_ulong mseccfg_csr_read(CPURISCVState *env)
-     RISCVException ret;
++{
++    trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
--    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
++    return env->mseccfg;
-+    ret = riscv_csrrw_check(env, csrno, true);
++}
-     if (ret != RISCV_EXCP_NONE) {
++
-         return ret;
+ /*
-     }
+  * Calculate the TLB size if the start address or the end address of
-diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
+  * PMP entry is presented in thie TLB page.
 diff --git a/target/riscv/trace-events b/target/riscv/trace-events
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/op_helper.c
+--- a/target/riscv/trace-events
-+++ b/target/riscv/op_helper.c
++++ b/target/riscv/trace-events
-@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
+@@ -XXX,XX +XXX,XX @@ pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRI
-     }
+ pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
+ pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
-     target_ulong val = 0;
+ pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
--    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
++
-+    RISCVException ret = riscv_csrr(env, csr, &val);
++mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
++mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
  target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
  {
      Int128 rv = int128_zero();
 -    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
 -                                          int128_zero(),
 -                                          int128_zero());
 +    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
 --
-.45.1
+.31.1

-[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
+[PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP)
-From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
+From: Hou Weiying <weiying_hou@outlook.com>
-In AIA spec, each hart (or each hart within a group) has a unique hart
+This commit adds support for ePMP v0.9.1.
-number to locate the memory pages of interrupt files in the address
-space. The number of bits required to represent any hart number is equal
+The ePMP spec can be found in:
-to ceil(log2(hmax + 1)), where hmax is the largest hart number among
+https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
-groups.
+Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
-However, if the largest hart number among groups is a power of 2, QEMU
+Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
-will pass an inaccurate hart-index-bit setting to Linux. For example, when
+Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
-the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-to represent 4 harts, but we passes 3 to Linux. The code needs to be
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-updated to ensure accurate hart-index-bit settings.
+Message-id: fef23b885f9649a4d54e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com
+[ Changes by AF:
-Additionally, a Linux patch[1] is necessary to correctly recover the hart
+ - Rebase on master
-index when the guest OS has only 1 hart, where the hart-index-bit is 0.
+ - Update to latest spec
+ - Use a switch case to handle ePMP MML permissions
-[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
+ - Fix a few bugs
+]
 Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
+ target/riscv/pmp.c | 154 ++++++++++++++++++++++++++++++++++++++++++---
-file changed, 8 insertions(+), 1 deletion(-)
+file changed, 146 insertions(+), 8 deletions(-)
-diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm/kvm-cpu.c
+--- a/target/riscv/pmp.c
-+++ b/target/riscv/kvm/kvm-cpu.c
++++ b/target/riscv/pmp.c
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+@@ -XXX,XX +XXX,XX @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
  static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
  {
      if (pmp_index < MAX_RISCV_PMPS) {
 -        if (!pmp_is_locked(env, pmp_index)) {
 -            env->pmp_state.pmp[pmp_index].cfg_reg = val;
 -            pmp_update_rule(env, pmp_index);
 +        bool locked = true;
 +
 +        if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
 +            /* mseccfg.RLB is set */
 +            if (MSECCFG_RLB_ISSET(env)) {
 +                locked = false;
 +            }
 +
 +            /* mseccfg.MML is not set */
 +            if (!MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, pmp_index)) {
 +                locked = false;
 +            }
 +
 +            /* mseccfg.MML is set */
 +            if (MSECCFG_MML_ISSET(env)) {
 +                /* not adding execute bit */
 +                if ((val & PMP_LOCK) != 0 && (val & PMP_EXEC) != PMP_EXEC) {
 +                    locked = false;
 +                }
 +                /* shared region and not adding X bit */
 +                if ((val & PMP_LOCK) != PMP_LOCK &&
 +                    (val & 0x7) != (PMP_WRITE | PMP_EXEC)) {
 +                    locked = false;
 +                }
 +            }
          } else {
 +            if (!pmp_is_locked(env, pmp_index)) {
 +                locked = false;
 +            }
 +        }
 +
 +        if (locked) {
              qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
 +        } else {
 +            env->pmp_state.pmp[pmp_index].cfg_reg = val;
 +            pmp_update_rule(env, pmp_index);
          }
-     }
+     } else {
+         qemu_log_mask(LOG_GUEST_ERROR,
--    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+@@ -XXX,XX +XXX,XX @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
-+
+ {
-+    if (max_hart_per_socket > 1) {
+     bool ret;
-+        max_hart_per_socket--;
-+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
++    if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
-+    } else {
++        if (MSECCFG_MMWP_ISSET(env)) {
-+        hart_bits = 0;
++            /*
 +             * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
 +             * so we default to deny all, even for M-mode.
 +             */
 +            *allowed_privs = 0;
 +            return false;
 +        } else if (MSECCFG_MML_ISSET(env)) {
 +            /*
 +             * The Machine Mode Lockdown (mseccfg.MML) bit is set
 +             * so we can only execute code in M-mode with an applicable
 +             * rule. Other modes are disabled.
 +             */
 +            if (mode == PRV_M && !(privs & PMP_EXEC)) {
 +                ret = true;
 +                *allowed_privs = PMP_READ | PMP_WRITE;
 +            } else {
 +                ret = false;
 +                *allowed_privs = 0;
 +            }
 +
 +            return ret;
 +        }
 +    }
 +
-     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+     if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
-                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
+         /*
-                             &hart_bits, true, NULL);
+          * Privileged spec v1.10 states if HW doesn't implement any PMP entry
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
              pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
          /*
 -         * If the PMP entry is not off and the address is in range, do the priv
 -         * check
 +         * Convert the PMP permissions to match the truth table in the
 +         * ePMP spec.
           */
 +        const uint8_t epmp_operation =
 +            ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
 +            ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
 +            (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
 +            ((env->pmp_state.pmp[i].cfg_reg & PMP_EXEC) >> 2);
 +
          if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 -            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 -            if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 -                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +            /*
 +             * If the PMP entry is not off and the address is in range,
 +             * do the priv check
 +             */
 +            if (!MSECCFG_MML_ISSET(env)) {
 +                /*
 +                 * If mseccfg.MML Bit is not set, do pmp priv check
 +                 * This will always apply to regular PMP.
 +                 */
 +                *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +                if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 +                    *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 +                }
 +            } else {
 +                /*
 +                 * If mseccfg.MML Bit set, do the enhanced pmp priv check
 +                 */
 +                if (mode == PRV_M) {
 +                    switch (epmp_operation) {
 +                    case 0:
 +                    case 1:
 +                    case 4:
 +                    case 5:
 +                    case 6:
 +                    case 7:
 +                    case 8:
 +                        *allowed_privs = 0;
 +                        break;
 +                    case 2:
 +                    case 3:
 +                    case 14:
 +                        *allowed_privs = PMP_READ | PMP_WRITE;
 +                        break;
 +                    case 9:
 +                    case 10:
 +                        *allowed_privs = PMP_EXEC;
 +                        break;
 +                    case 11:
 +                    case 13:
 +                        *allowed_privs = PMP_READ | PMP_EXEC;
 +                        break;
 +                    case 12:
 +                    case 15:
 +                        *allowed_privs = PMP_READ;
 +                        break;
 +                    }
 +                } else {
 +                    switch (epmp_operation) {
 +                    case 0:
 +                    case 8:
 +                    case 9:
 +                    case 12:
 +                    case 13:
 +                    case 14:
 +                        *allowed_privs = 0;
 +                        break;
 +                    case 1:
 +                    case 10:
 +                    case 11:
 +                        *allowed_privs = PMP_EXEC;
 +                        break;
 +                    case 2:
 +                    case 4:
 +                    case 15:
 +                        *allowed_privs = PMP_READ;
 +                        break;
 +                    case 3:
 +                    case 6:
 +                        *allowed_privs = PMP_READ | PMP_WRITE;
 +                        break;
 +                    case 5:
 +                        *allowed_privs = PMP_READ | PMP_EXEC;
 +                        break;
 +                    case 7:
 +                        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 +                        break;
 +                    }
 +                }
              }
              ret = ((privs & *allowed_privs) == privs);
 --
-.45.1
+.31.1

-New patch
+[PULL v2 25/42] target/riscv: Add a config option for ePMP
+From: Hou Weiying <weiying_hou@outlook.com>
+Add a config option to enable experimental support for ePMP. This
+is disabled by default and can be enabled with 'x-epmp=true'.
+Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
+Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
+Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+---
+ target/riscv/cpu.h |  1 +
+ target/riscv/cpu.c | 10 ++++++++++
+files changed, 11 insertions(+)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
+         uint16_t elen;
+         bool mmu;
+         bool pmp;
++        bool epmp;
+         uint64_t resetvec;
+     } cfg;
+ };
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+     if (cpu->cfg.pmp) {
+         set_feature(env, RISCV_FEATURE_PMP);
++
++        /*
++         * Enhanced PMP should only be available
++         * on harts with PMP support
++         */
++        if (cpu->cfg.epmp) {
++            set_feature(env, RISCV_FEATURE_EPMP);
++        }
+     }
+     set_resetvec(env, cpu->cfg.resetvec);
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
++    DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
++
+     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+     DEFINE_PROP_END_OF_LIST(),
+ };
+--
+.31.1

-New patch
+[PULL v2 26/42] target/riscv/pmp: Remove outdated comment
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com
+---
+ target/riscv/pmp.c | 4 ----
+file changed, 4 deletions(-)
+diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/pmp.c
++++ b/target/riscv/pmp.c
+@@ -XXX,XX +XXX,XX @@
+  * this program.  If not, see <http://www.gnu.org/licenses/>.
+  */
+-/*
+- * PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
+- */
+-
+ #include "qemu/osdep.h"
+ #include "qemu/log.h"
+ #include "qapi/error.h"
+--
+.31.1

-[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
+[PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU
-From: Rob Bradford <rbradford@rivosinc.com>
+The physical Ibex CPU has ePMP support and it's enabled for the
 OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
-This extension has now been ratified:
-https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
-removed.
-Since this is now a ratified extension add it to the list of extensions
-included in the "max" CPU variant.
-Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com
 ---
- target/riscv/cpu.c         | 2 +-
+ target/riscv/cpu.c | 1 +
- target/riscv/tcg/tcg-cpu.c | 2 +-
+file changed, 1 insertion(+)
 files changed, 2 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
+@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
-     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
+     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
-     MISA_EXT_INFO(RVV, "v", "Vector operations"),
+     set_priv_version(env, PRIV_VERSION_1_10_0);
-     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
+     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
--    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
++    qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
-+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
+ }
- };
+ static void rv32_imafcu_nommu_cpu_init(Object *obj)
  static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
      const RISCVCPUMultiExtConfig *prop;
      /* Enable RVG, RVJ and RVV that are disabled by default */
 -    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
 +    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
      for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
          isa_ext_update_enabled(cpu, prop->offset, true);
 --
-.45.1
+.31.1

-[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
+[PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug
-From: Max Chou <max.chou@sifive.com>
+From: Frank Chang <frank.chang@sifive.com>
-The require_scale_rvf function only checks the double width operator for
+ETYPE may be type of uint64_t, thus index variable has to be declared as
-the vector floating point widen instructions, so most of the widen
+type of uint64_t, too. Otherwise the value read from vs1 register may be
-checking functions need to add require_rvf for single width operator.
+truncated to type of uint32_t.
-The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
-integer to double width float, so the opfxv_widen_check function doesn’t
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-need require_rvf for the single width operator(integer).
+Message-id: 20210419060302.14075-1-frank.chang@sifive.com
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
+ target/riscv/vector_helper.c | 6 ++++--
-file changed, 5 insertions(+)
+file changed, 4 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
+--- a/target/riscv/vector_helper.c
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
- static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+     uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
- {
+     uint32_t vm = vext_vm(desc);                                          \
-     return require_rvv(s) &&
+     uint32_t vl = env->vl;                                                \
-+           require_rvf(s) &&
+-    uint32_t index, i;                                                    \
-            require_scale_rvf(s) &&
++    uint64_t index;                                                       \
-            (s->sew != MO_8) &&
++    uint32_t i;                                                           \
-            vext_check_isa_ill(s) &&
+                                                                           \
-@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
+     for (i = 0; i < vl; i++) {                                            \
- static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
+         if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
- {
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
-     return require_rvv(s) &&
+     uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
-+           require_rvf(s) &&
+     uint32_t vm = vext_vm(desc);                                          \
-            require_scale_rvf(s) &&
+     uint32_t vl = env->vl;                                                \
-            (s->sew != MO_8) &&
+-    uint32_t index = s1, i;                                               \
-            vext_check_isa_ill(s) &&
++    uint64_t index = s1;                                                  \
-@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
++    uint32_t i;                                                           \
- static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
+                                                                           \
- {
+     for (i = 0; i < vl; i++) {                                            \
-     return require_rvv(s) &&
+         if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
 --
-.45.1
+.31.1

-[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
+[PULL v2 29/42] target/riscv: fix exception index on instruction access fault
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Emmanuel Blot <emmanuel.blot@sifive.com>
-We're not setting (s/m)tval when triggering breakpoints of type 2
+When no MMU is used and the guest code attempts to fetch an instruction
-(mcontrol) and 6 (mcontrol6). According to the debug spec section
+from an invalid memory location, the exception index defaults to a data
-.7.12, "Match Control Type 6":
+load access fault, rather an instruction access fault.
-"The Privileged Spec says that breakpoint exceptions that occur on
+Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
 instruction fetches, loads, or stores update the tval CSR with either
 zero or the faulting virtual address. The faulting virtual address for
 an mcontrol6 trigger with action = 0 is the address being accessed and
 which caused that trigger to fire."
 A similar text is also found in the Debug spec section 5.7.11 w.r.t.
 mcontrol.
 Note that what we're doing ATM is not violating the spec, but it's
 simple enough to set mtval/stval and it makes life easier for any
 software that relies on this info.
 Given that we always use action = 0, save the faulting address for the
 mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
 used as as scratch area for traps with address information. 'tval' is
 then set during riscv_cpu_do_interrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
 Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 1 +
+ target/riscv/cpu_helper.c | 4 +++-
- target/riscv/debug.c      | 3 +++
+file changed, 3 insertions(+), 1 deletion(-)
 files changed, 4 insertions(+)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
-             tval = env->bins;
-             break;
+     if (access_type == MMU_DATA_STORE) {
-         case RISCV_EXCP_BREAKPOINT:
+         cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
-+            tval = env->badaddr;
+-    } else {
-             if (cs->watchpoint_hit) {
++    } else if (access_type == MMU_DATA_LOAD) {
-                 tval = cs->watchpoint_hit->hitaddr;
+         cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
-                 cs->watchpoint_hit = NULL;
++    } else {
-diff --git a/target/riscv/debug.c b/target/riscv/debug.c
++        cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
-index XXXXXXX..XXXXXXX 100644
+     }
---- a/target/riscv/debug.c
-+++ b/target/riscv/debug.c
+     env->badaddr = addr;
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                  if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                      /* check U/S/M bit against current privilege level */
                      if ((ctrl >> 3) & BIT(env->priv)) {
 +                        env->badaddr = pc;
                          return true;
                      }
                  }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                      if (env->virt_enabled) {
                          /* check VU/VS bit against current privilege level */
                          if ((ctrl >> 23) & BIT(env->priv)) {
 +                            env->badaddr = pc;
                              return true;
                          }
                      } else {
                          /* check U/S/M bit against current privilege level */
                          if ((ctrl >> 3) & BIT(env->priv)) {
 +                            env->badaddr = pc;
                              return true;
                          }
                      }
 --
-.45.1
+.31.1

-[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
+[PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector
-From: Jason Chien <jason.chien@sifive.com>
+From: Alexander Wagner <alexander.wagner@ulal.de>
-In current implementation, the gdbstub allows reading vector registers
+The IBEX documentation [1] specifies the reset vector to be "the most
-only if V extension is supported. However, all vector extensions and
+significant 3 bytes of the boot address and the reset value (0x80) as
-vector crypto extensions have the vector registers and they all depend
+the least significant byte".
 on Zve32x. The gdbstub should check for Zve32x instead.
-Signed-off-by: Jason Chien <jason.chien@sifive.com>
+[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Max Chou <max.chou@sifive.com>
+Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
-Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/gdbstub.c | 2 +-
+ hw/riscv/opentitan.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/gdbstub.c
+--- a/hw/riscv/opentitan.c
-+++ b/target/riscv/gdbstub.c
++++ b/hw/riscv/opentitan.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
+                             &error_abort);
-);
+     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
-     }
+                             &error_abort);
--    if (env->misa_ext & RVV) {
+-    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
-+    if (cpu->cfg.ext_zve32x) {
++    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
-         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
+     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
-                                  riscv_gdb_set_vector,
-                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
+     /* Boot ROM */
 --
-.45.1
+.31.1

-[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
+[PULL v2 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Frank Chang <frank.chang@sifive.com>
-Privileged spec section 4.1.9 mentions:
+In IEEE 754-2008 spec:
   Invalid operation exception is signaled when doing:
   fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
   unless c is a quiet NaN; if c is a quiet NaN then it is
   implementation defined whether the invalid operation exception
   is signaled.
-"When a trap is taken into S-mode, stval is written with
+In RISC-V Unprivileged ISA spec:
-exception-specific information to assist software in handling the trap.
+  The fused multiply-add instructions must set the invalid
-(...)
+  operation exception flag when the multiplicands are Inf and
   zero, even when the addend is a quiet NaN.
-If stval is written with a nonzero value when a breakpoint,
+This commit set invalid operation execption flag for RISC-V when
-address-misaligned, access-fault, or page-fault exception occurs on an
+multiplicands of muladd instructions are Inf and zero.
 instruction fetch, load, or store, then stval will contain the faulting
 virtual address."
-A similar text is found for mtval in section 3.1.16.
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
 Setting mtval/stval in this scenario is optional, but some softwares read
 these regs when handling ebreaks.
 Write 'badaddr' in all ebreak breakpoints to write the appropriate
 'tval' during riscv_do_cpu_interrrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
+Message-id: 20210420013150.21992-1-frank.chang@sifive.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
+ fpu/softfloat-specialize.c.inc | 6 ++++++
-file changed, 2 insertions(+)
+file changed, 6 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
+diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_privileged.c.inc
+--- a/fpu/softfloat-specialize.c.inc
-+++ b/target/riscv/insn_trans/trans_privileged.c.inc
++++ b/fpu/softfloat-specialize.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
      if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
          generate_exception(ctx, RISCV_EXCP_SEMIHOST);
      } else {
-+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+         return 1;
 +                      offsetof(CPURISCVState, badaddr));
          generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
      }
-     return true;
++#elif defined(TARGET_RISCV)
 +    /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
 +    if (infzero) {
 +        float_raise(float_flag_invalid, status);
 +    }
 +    return 3; /* default NaN */
  #elif defined(TARGET_XTENSA)
      /*
       * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
 --
-.45.1
+.31.1

-[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
+[PULL v2 32/42] target/riscv: fix a typo with interrupt names
-From: Yangyu Chen <cyy@cyyself.name>
+From: Emmanuel Blot <emmanuel.blot@sifive.com>
-This code has a typo that writes zvkb to zvkg, causing users can't
+Interrupt names have been swapped in 205377f8 and do not follow
-enable zvkb through the config. This patch gets this fixed.
+IRQ_*_EXT definition order.
-Signed-off-by: Yangyu Chen <cyy@cyyself.name>
+Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
 Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Max Chou <max.chou@sifive.com>
+Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
 Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
 Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+@@ -XXX,XX +XXX,XX @@ const char * const riscv_intr_names[] = {
-     /* Vector cryptography extensions */
+     "vs_timer",
-     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
+     "m_timer",
-     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
+     "u_external",
--    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
++    "s_external",
-+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
+     "vs_external",
-     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
+-    "h_external",
-     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
+     "m_external",
-     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
+     "reserved",
      "reserved",
 --
-.45.1
+.31.1

-[PULL 11/28] target/riscv: Add support for Zve64x extension
+[PULL v2 33/42] target/riscv: Remove the hardcoded RVXLEN macro
-From: Jason Chien <jason.chien@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
 ---
  target/riscv/cpu.h | 6 ------
  target/riscv/cpu.c | 6 +++++-
 files changed, 5 insertions(+), 7 deletions(-)
-Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 enabling Zve64x enables Zve32x according to their dependency.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
 Signed-off-by: Jason Chien <jason.chien@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu_cfg.h     |  1 +
  target/riscv/cpu.c         |  2 ++
  target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 files changed, 14 insertions(+), 6 deletions(-)
 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_cfg.h
+--- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu_cfg.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@
-     bool ext_zve32x;
+ #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
-     bool ext_zve64f;
+ #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
-     bool ext_zve64d;
-+    bool ext_zve64x;
+-#if defined(TARGET_RISCV32)
-     bool ext_zvbb;
+-#define RVXLEN RV32
-     bool ext_zvbc;
+-#elif defined(TARGET_RISCV64)
-     bool ext_zvkb;
+-#define RVXLEN RV64
 -#endif
 -
  #define RV(x) ((target_ulong)1 << (x - 'A'))
  #define RVI RV('I')
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
+@@ -XXX,XX +XXX,XX @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
-     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
+ static void riscv_any_cpu_init(Object *obj)
-     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+ {
-     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
-+    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
+-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
++#if defined(TARGET_RISCV32)
-     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
++    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
++#elif defined(TARGET_RISCV64)
-@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
++    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-     MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
++#endif
-     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
+     set_priv_version(env, PRIV_VERSION_1_11_0);
-     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
+ }
 +    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
      MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
      MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      /* The Zve64d extension depends on the Zve64f extension */
      if (cpu->cfg.ext_zve64d) {
 +        if (!riscv_has_ext(env, RVD)) {
 +            error_setg(errp, "Zve64d/V extensions require D extension");
 +            return;
 +        }
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
      }
 -    /* The Zve64f extension depends on the Zve32f extension */
 +    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
      if (cpu->cfg.ext_zve64f) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
      }
 -    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
 -        error_setg(errp, "Zve64d/V extensions require D extension");
 -        return;
 +    /* The Zve64x extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve64x) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
      /* The Zve32f extension depends on the Zve32x extension */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
 -    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
          error_setg(
              errp,
 -            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
          return;
      }
 --
-.45.1
+.31.1

-[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+[PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro
-From: Max Chou <max.chou@sifive.com>
+This also ensures that the SD bit is not writable.
-According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-instructions will be affected by Zvfhmin extension.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-conversions of
+Message-id: 9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
 ---
  target/riscv/cpu_bits.h | 6 ------
  target/riscv/csr.c      | 9 ++++++++-
 files changed, 8 insertions(+), 7 deletions(-)
-* From 1*SEW(16/32) to 2*SEW(32/64)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 * From 2*SEW(32/64) to 1*SEW(16/32)
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 file changed, 18 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
+--- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@
-     }
+ #define SSTATUS32_SD        0x80000000
- }
+ #define SSTATUS64_SD        0x8000000000000000ULL
-+static bool require_rvfmin(DisasContext *s)
+-#if defined(TARGET_RISCV32)
-+{
+-#define SSTATUS_SD SSTATUS32_SD
-+    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
+-#elif defined(TARGET_RISCV64)
-+        return false;
+-#define SSTATUS_SD SSTATUS64_SD
 -#endif
 -
  /* hstatus CSR bits */
  #define HSTATUS_VSBE         0x00000020
  #define HSTATUS_GVA          0x00000040
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps =
      (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
  static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
      SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
 -    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 +    SSTATUS_SUM | SSTATUS_MXR;
  static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
  static const target_ulong hip_writable_mask = MIP_VSSIP;
  static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
                                     target_ulong *val)
  {
      target_ulong mask = (sstatus_v1_10_mask);
 +
 +    if (riscv_cpu_is_32bit(env)) {
 +        mask |= SSTATUS32_SD;
 +    } else {
 +        mask |= SSTATUS64_SD;
 +    }
 +
-+    switch (s->sew) {
+     *val = env->mstatus & mask;
-+    case MO_16:
+     return RISCV_EXCP_NONE;
 +        return s->cfg_ptr->ext_zvfhmin;
 +    case MO_32:
 +        return s->cfg_ptr->ext_zve32f;
 +    default:
 +        return false;
 +    }
 +}
 +
  static bool require_scale_rvf(DisasContext *s)
  {
      if (s->mstatus_fs == EXT_STATUS_DISABLED) {
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
      }
      switch (s->sew) {
 -    case MO_8:
 -        return s->cfg_ptr->ext_zvfhmin;
      case MO_16:
          return s->cfg_ptr->ext_zve32f;
      case MO_32:
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_widen_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
  static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_narrow_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
 --
-.45.1
+.31.1

-[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
+[PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: 665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
 ---
  target/riscv/cpu_bits.h   | 11 -----------
  target/riscv/cpu_helper.c | 24 +++++++++++++++---------
 files changed, 15 insertions(+), 20 deletions(-)
-raise_mmu_exception(), as is today, is prioritizing guest page faults by
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
-checking first if virt_enabled && !first_stage, and then considering the
+index XXXXXXX..XXXXXXX 100644
-regular inst/load/store faults.
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
-There's no mention in the spec about guest page fault being a higher
+@@ -XXX,XX +XXX,XX @@
-priority that PMP faults. In fact, privileged spec section 3.7.1 says:
+ #define CSR_HTIMEDELTA      0x605
+ #define CSR_HTIMEDELTAH     0x615
-"Attempting to fetch an instruction from a PMP region that does not have
-execute permissions raises an instruction access-fault exception.
+-#if defined(TARGET_RISCV32)
-Attempting to execute a load or load-reserved instruction which accesses
+-#define HGATP_MODE           SATP32_MODE
-a physical address within a PMP region without read permissions raises a
+-#define HGATP_VMID           SATP32_ASID
-load access-fault exception. Attempting to execute a store,
+-#define HGATP_PPN            SATP32_PPN
-store-conditional, or AMO instruction which accesses a physical address
+-#endif
-within a PMP region without write permissions raises a store
+-#if defined(TARGET_RISCV64)
-access-fault exception."
+-#define HGATP_MODE           SATP64_MODE
+-#define HGATP_VMID           SATP64_ASID
-So, in fact, we're doing it wrong - PMP faults should always be thrown,
+-#define HGATP_PPN            SATP64_PPN
-regardless of also being a first or second stage fault.
+-#endif
+-
-The way riscv_cpu_tlb_fill() and get_physical_address() work is
+ /* Virtual CSRs */
-adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
+ #define CSR_VSSTATUS        0x200
-reflected in the 'pmp_violation' flag. What we need is to change
+ #define CSR_VSIE            0x204
 raise_mmu_exception() to prioritize it.
 Reported-by: Joseph Chan <jchan@ventanamicro.com>
 Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu_helper.c | 22 ++++++++++++----------
 file changed, 12 insertions(+), 10 deletions(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
+         }
+         widened = 0;
+     } else {
+-        base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
+-        vm = get_field(env->hgatp, HGATP_MODE);
++        if (riscv_cpu_is_32bit(env)) {
++            base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
++            vm = get_field(env->hgatp, SATP32_MODE);
++        } else {
++            base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
++            vm = get_field(env->hgatp, SATP64_MODE);
++        }
+         widened = 2;
+     }
+     /* status.SUM will be ignored if execute on background */
 @@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+                                 bool first_stage, bool two_stage)
  {
      CPUState *cs = env_cpu(env);
 -    int page_fault_exceptions;
 +    int page_fault_exceptions, vm;
 +
      if (first_stage) {
 -        page_fault_exceptions =
 -            get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
 -            !pmp_violation;
 +        vm = get_field(env->satp, SATP_MODE);
 +    } else if (riscv_cpu_is_32bit(env)) {
 +        vm = get_field(env->hgatp, SATP32_MODE);
      } else {
 -        page_fault_exceptions =
 -            get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
 -            !pmp_violation;
 +        vm = get_field(env->hgatp, SATP64_MODE);
      }
 +    page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
 +
      switch (access_type) {
      case MMU_INST_FETCH:
--        if (env->virt_enabled && !first_stage) {
+         if (riscv_cpu_virt_enabled(env) && !first_stage) {
 +        if (pmp_violation) {
 +            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
 +        } else if (env->virt_enabled && !first_stage) {
              cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
          }
          break;
      case MMU_DATA_LOAD:
 -        if (two_stage && !first_stage) {
 +        if (pmp_violation) {
 +            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
          }
          break;
      case MMU_DATA_STORE:
 -        if (two_stage && !first_stage) {
 +        if (pmp_violation) {
 +            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
 -                RISCV_EXCP_STORE_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
          }
          break;
      default:
 --
-.45.1
+.31.1

-New patch
+[PULL v2 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu_bits.h  | 10 ----------
+ target/riscv/csr.c       | 12 ++++++++++--
+ target/riscv/translate.c | 19 +++++++++++++++++--
+files changed, 27 insertions(+), 14 deletions(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define MXL_RV64            2
+ #define MXL_RV128           3
+-#if defined(TARGET_RISCV32)
+-#define MSTATUS_SD MSTATUS32_SD
+-#define MISA_MXL MISA32_MXL
+-#define MXL_VAL MXL_RV32
+-#elif defined(TARGET_RISCV64)
+-#define MSTATUS_SD MSTATUS64_SD
+-#define MISA_MXL MISA64_MXL
+-#define MXL_VAL MXL_RV64
+-#endif
+-
+ /* sstatus CSR bits */
+ #define SSTATUS_UIE         0x00000001
+ #define SSTATUS_SIE         0x00000002
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
+     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
+             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
+-    mstatus = set_field(mstatus, MSTATUS_SD, dirty);
++    if (riscv_cpu_is_32bit(env)) {
++        mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
++    } else {
++        mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
++    }
+     env->mstatus = mstatus;
+     return RISCV_EXCP_NONE;
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
+     }
+     /* misa.MXL writes are not supported by QEMU */
+-    val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
++    if (riscv_cpu_is_32bit(env)) {
++        val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
++    } else {
++        val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
++    }
+     /* flush translation cache */
+     if (val != env->misa) {
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+     return ctx->misa & ext;
+ }
++#ifdef TARGET_RISCV32
++# define is_32bit(ctx)  true
++#elif defined(CONFIG_USER_ONLY)
++# define is_32bit(ctx)  false
++#else
++static inline bool is_32bit(DisasContext *ctx)
++{
++    return (ctx->misa & RV32) == RV32;
++}
++#endif
++
+ /*
+  * RISC-V requires NaN-boxing of narrower width floating point values.
+  * This applies when a 32-bit value is assigned to a 64-bit FP register.
+@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+ static void mark_fs_dirty(DisasContext *ctx)
+ {
+     TCGv tmp;
++    target_ulong sd;
++
+     if (ctx->mstatus_fs == MSTATUS_FS) {
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
+     ctx->mstatus_fs = MSTATUS_FS;
+     tmp = tcg_temp_new();
++    sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
++
+     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+-    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
++    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+     if (ctx->virt_enabled) {
+         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
++        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+     }
+     tcg_temp_free(tmp);
+--
+.31.1

-[PULL 10/28] target/riscv: Add support for Zve32x extension
+[PULL v2 37/42] target/riscv: Remove the hardcoded SATP_MODE macro
-From: Jason Chien <jason.chien@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
 ---
  target/riscv/cpu_bits.h   | 11 -----------
  target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++--------
  target/riscv/csr.c        | 19 +++++++++++++++----
  target/riscv/monitor.c    | 22 +++++++++++++++++-----
 files changed, 56 insertions(+), 28 deletions(-)
-Add support for Zve32x extension and replace some checks for Zve32f with
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 Zve32x, since Zve32f depends on Zve32x.
 Signed-off-by: Jason Chien <jason.chien@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu_cfg.h                  |  1 +
  target/riscv/cpu.c                      |  2 ++
  target/riscv/cpu_helper.c               |  2 +-
  target/riscv/csr.c                      |  2 +-
  target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
  target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 files changed, 15 insertions(+), 12 deletions(-)
 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_cfg.h
+--- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/cpu_cfg.h
++++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@
-     bool ext_zhinx;
+ #define SATP64_ASID         0x0FFFF00000000000ULL
-     bool ext_zhinxmin;
+ #define SATP64_PPN          0x00000FFFFFFFFFFFULL
-     bool ext_zve32f;
-+    bool ext_zve32x;
+-#if defined(TARGET_RISCV32)
-     bool ext_zve64f;
+-#define SATP_MODE           SATP32_MODE
-     bool ext_zve64d;
+-#define SATP_ASID           SATP32_ASID
-     bool ext_zvbb;
+-#define SATP_PPN            SATP32_PPN
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+-#endif
-index XXXXXXX..XXXXXXX 100644
+-#if defined(TARGET_RISCV64)
---- a/target/riscv/cpu.c
+-#define SATP_MODE           SATP64_MODE
-+++ b/target/riscv/cpu.c
+-#define SATP_ASID           SATP64_ASID
-@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
+-#define SATP_PPN            SATP64_PPN
-     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
+-#endif
-     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
+-
-     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+ /* VM modes (mstatus.vm) privileged ISA 1.9.1 */
-+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
+ #define VM_1_09_MBARE       0
-     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+ #define VM_1_09_MBB         1
      ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
      ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
      MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
      MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
-     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
-     *cs_base = 0;
+     if (first_stage == true) {
+         if (use_background) {
--    if (cpu->cfg.ext_zve32f) {
+-            base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
-+    if (cpu->cfg.ext_zve32x) {
+-            vm = get_field(env->vsatp, SATP_MODE);
-         /*
++            if (riscv_cpu_is_32bit(env)) {
-          * If env->vl equals to VLMAX, we can use generic vector operation
++                base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
-          * expanders (GVEC) to accerlate the vector operations.
++                vm = get_field(env->vsatp, SATP32_MODE);
 +            } else {
 +                base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
 +                vm = get_field(env->vsatp, SATP64_MODE);
 +            }
          } else {
 -            base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
 -            vm = get_field(env->satp, SATP_MODE);
 +            if (riscv_cpu_is_32bit(env)) {
 +                base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
 +                vm = get_field(env->satp, SATP32_MODE);
 +            } else {
 +                base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
 +                vm = get_field(env->satp, SATP64_MODE);
 +            }
          }
          widened = 0;
      } else {
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
  {
      CPUState *cs = env_cpu(env);
      int page_fault_exceptions, vm;
 +    uint64_t stap_mode;
 +
 +    if (riscv_cpu_is_32bit(env)) {
 +        stap_mode = SATP32_MODE;
 +    } else {
 +        stap_mode = SATP64_MODE;
 +    }
      if (first_stage) {
 -        vm = get_field(env->satp, SATP_MODE);
 -    } else if (riscv_cpu_is_32bit(env)) {
 -        vm = get_field(env->hgatp, SATP32_MODE);
 +        vm = get_field(env->satp, stap_mode);
      } else {
 -        vm = get_field(env->hgatp, SATP64_MODE);
 +        vm = get_field(env->hgatp, stap_mode);
      }
 +
      page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
      switch (access_type) {
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
+ static RISCVException write_satp(CPURISCVState *env, int csrno,
- static RISCVException vs(CPURISCVState *env, int csrno)
+                                  target_ulong val)
  {
--    if (riscv_cpu_cfg(env)->ext_zve32f) {
++    int vm, mask, asid;
-+    if (riscv_cpu_cfg(env)->ext_zve32x) {
++
- #if !defined(CONFIG_USER_ONLY)
+     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
-         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+         return RISCV_EXCP_NONE;
      }
 -    if (validate_vm(env, get_field(val, SATP_MODE)) &&
 -        ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
 -    {
 +
 +    if (riscv_cpu_is_32bit(env)) {
 +        vm = validate_vm(env, get_field(val, SATP32_MODE));
 +        mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
 +        asid = (val ^ env->satp) & SATP32_ASID;
 +    } else {
 +        vm = validate_vm(env, get_field(val, SATP64_MODE));
 +        mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
 +        asid = (val ^ env->satp) & SATP64_ASID;
 +    }
 +
 +    if (vm && mask) {
          if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
              return RISCV_EXCP_ILLEGAL_INST;
-diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+         } else {
 -            if ((val ^ env->satp) & SATP_ASID) {
 +            if (asid) {
                  tlb_flush(env_cpu(env));
              }
              env->satp = val;
 diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/tcg/tcg-cpu.c
+--- a/target/riscv/monitor.c
-+++ b/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/monitor.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
      target_ulong last_size;
      int last_attr;
 -    base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
 +    if (riscv_cpu_is_32bit(env)) {
 +        base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
 +        vm = get_field(env->satp, SATP32_MODE);
 +    } else {
 +        base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
 +        vm = get_field(env->satp, SATP64_MODE);
 +    }
 -    vm = get_field(env->satp, SATP_MODE);
      switch (vm) {
      case VM_1_10_SV32:
          levels = 2;
@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
          return;
      }
--    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
+-    if (!(env->satp & SATP_MODE)) {
--        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+-        monitor_printf(mon, "No translation or protection\n");
 -        return;
-+    /* The Zve32f extension depends on the Zve32x extension */
++    if (riscv_cpu_is_32bit(env)) {
-+    if (cpu->cfg.ext_zve32f) {
++        if (!(env->satp & SATP32_MODE)) {
-+        if (!riscv_has_ext(env, RVF)) {
++            monitor_printf(mon, "No translation or protection\n");
 +            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +            return;
 +        }
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
++    } else {
 +        if (!(env->satp & SATP64_MODE)) {
 +            monitor_printf(mon, "No translation or protection\n");
 +            return;
 +        }
      }
-     if (cpu->cfg.ext_zvfh) {
+     mem_info_svxx(mon, env);
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
      }
 -    /*
 -     * In principle Zve*x would also suffice here, were they supported
 -     * in qemu
 -     */
      if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
           cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
 -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
 +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
  {
      TCGv s1, dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
  {
      TCGv dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
 --
-.45.1
+.31.1

-New patch
+[PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/cpu_bits.h | 6 ------
+file changed, 6 deletions(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@
+ #define HSTATUS32_WPRI       0xFF8FF87E
+ #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
+-#if defined(TARGET_RISCV32)
+-#define HSTATUS_WPRI HSTATUS32_WPRI
+-#elif defined(TARGET_RISCV64)
+-#define HSTATUS_WPRI HSTATUS64_WPRI
+-#endif
+-
+ #define HCOUNTEREN_CY        (1 << 0)
+ #define HCOUNTEREN_TM        (1 << 1)
+ #define HCOUNTEREN_IR        (1 << 2)
+--
+.31.1

-New patch
+[PULL v2 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/translate.c | 6 ------
+file changed, 6 deletions(-)
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+     CPUState *cs;
+ } DisasContext;
+-#ifdef TARGET_RISCV64
+-#define CASE_OP_32_64(X) case X: case glue(X, W)
+-#else
+-#define CASE_OP_32_64(X) case X
+-#endif
+-
+ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+ {
+     return ctx->misa & ext;
+--
+.31.1

-[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
+[PULL v2 40/42] target/riscv: Consolidate RV32/64 32-bit instructions
-From: Alistair Francis <alistair23@gmail.com>
+This patch removes the insn32-64.decode decode file and consolidates the
 instructions into the general RISC-V insn32.decode decode tree.
-When running the instruction
+This means that all of the instructions are avaliable in both the 32-bit
+and 64-bit builds. This also means that we run a check to ensure we are
-```
+running a 64-bit softmmu before we execute the 64-bit only instructions.
-    cbo.flush 0(x0)
+This allows us to include the 32-bit instructions in the 64-bit build,
-```
+while also ensuring that 32-bit only software can not execute the
+instructions.
 QEMU would segfault.
 The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
 allocated.
 In order to fix this let's use the existing get_address()
 helper. This also has the benefit of performing pointer mask
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
-Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
 Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
+ target/riscv/helper.h                   | 18 +++--
-file changed, 12 insertions(+), 4 deletions(-)
+ target/riscv/insn32-64.decode           | 88 -------------------------
  target/riscv/insn32.decode              | 67 ++++++++++++++++++-
  target/riscv/fpu_helper.c               | 16 ++---
  target/riscv/translate.c                |  9 ++-
  target/riscv/vector_helper.c            |  4 --
  target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
  target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
  target/riscv/insn_trans/trans_rvf.c.inc |  6 +-
  target/riscv/insn_trans/trans_rvh.c.inc |  8 ++-
  target/riscv/insn_trans/trans_rvi.c.inc | 16 +++--
  target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
  target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
  target/riscv/meson.build                |  2 +-
 files changed, 166 insertions(+), 150 deletions(-)
  delete mode 100644 target/riscv/insn32-64.decode
-diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+--- a/target/riscv/helper.h
-+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
++++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
  DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
  DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
  DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
 -DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
 -DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
 +DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
 +DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
  DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
  DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
 -DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
 -DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
 +DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
 +DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
  DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
  /* Floating Point - Double Precision */
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
  DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
  DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
  DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
 -DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
 -DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
 +DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
 +DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
  DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
  DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
 -DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
 -DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
 +DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
 +DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
  DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
  /* Special functions */
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
  DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
  DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
  DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
 -#ifdef TARGET_RISCV64
  DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vamoaddw_v_d,  void, ptr, ptr, tl, ptr, env, i32)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
 -#endif
  DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vamoaddw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
  DEF_HELPER_6(vamoxorw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
 diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/target/riscv/insn32-64.decode
 +++ /dev/null
 @@ -XXX,XX +XXX,XX @@
- static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
+-#
- {
+-# RISC-V translation routines for the RV Instruction Set.
-     REQUIRE_ZICBOM(ctx);
+-#
--    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-+    TCGv src = get_address(ctx, a->rs1, 0);
+-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-+
+-#
-+    gen_helper_cbo_clean_flush(tcg_env, src);
+-# This program is free software; you can redistribute it and/or modify it
 -# under the terms and conditions of the GNU General Public License,
 -# version 2 or later, as published by the Free Software Foundation.
 -#
 -# This program is distributed in the hope it will be useful, but WITHOUT
 -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 -# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 -# more details.
 -#
 -# You should have received a copy of the GNU General Public License along with
 -# this program.  If not, see <http://www.gnu.org/licenses/>.
 -
 -# This is concatenated with insn32.decode for risc64 targets.
 -# Most of the fields and formats are there.
 -
 -%sh5    20:5
 -
 -@sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
 -
 -# *** RV64I Base Instruction Set (in addition to RV32I) ***
 -lwu      ............   ..... 110 ..... 0000011 @i
 -ld       ............   ..... 011 ..... 0000011 @i
 -sd       ....... .....  ..... 011 ..... 0100011 @s
 -addiw    ............   ..... 000 ..... 0011011 @i
 -slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
 -srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
 -sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
 -addw     0000000 .....  ..... 000 ..... 0111011 @r
 -subw     0100000 .....  ..... 000 ..... 0111011 @r
 -sllw     0000000 .....  ..... 001 ..... 0111011 @r
 -srlw     0000000 .....  ..... 101 ..... 0111011 @r
 -sraw     0100000 .....  ..... 101 ..... 0111011 @r
 -
 -# *** RV64M Standard Extension (in addition to RV32M) ***
 -mulw     0000001 .....  ..... 000 ..... 0111011 @r
 -divw     0000001 .....  ..... 100 ..... 0111011 @r
 -divuw    0000001 .....  ..... 101 ..... 0111011 @r
 -remw     0000001 .....  ..... 110 ..... 0111011 @r
 -remuw    0000001 .....  ..... 111 ..... 0111011 @r
 -
 -# *** RV64A Standard Extension (in addition to RV32A) ***
 -lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
 -sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
 -amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
 -amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
 -amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
 -amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
 -amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
 -amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
 -amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
 -amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
 -amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
 -
 -#*** Vector AMO operations (in addition to Zvamo) ***
 -vamoswapd_v     00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
 -vamoaddd_v      00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 -vamoxord_v      00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 -vamoandd_v      01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 -vamoord_v       01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 -vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 -vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 -vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 -vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 -
 -# *** RV64F Standard Extension (in addition to RV32F) ***
 -fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
 -fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
 -fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
 -fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
 -
 -# *** RV64D Standard Extension (in addition to RV32D) ***
 -fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
 -fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
 -fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
 -fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
 -fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
 -fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
 -
 -# *** RV32H Base Instruction Set ***
 -hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
 -hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
 -hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
  %rs2       20:5
  %rs1       15:5
  %rd        7:5
 +%sh5       20:5
  %sh10    20:10
  %csr    20:12
@@ -XXX,XX +XXX,XX @@
  @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
  @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
 +# Formats 64:
 +@sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
  # *** Privileged Instructions ***
  ecall       000000000000     00000 000 00000 1110011
@@ -XXX,XX +XXX,XX @@ csrrwi   ............     ..... 101 ..... 1110011 @csr
  csrrsi   ............     ..... 110 ..... 1110011 @csr
  csrrci   ............     ..... 111 ..... 1110011 @csr
 +# *** RV64I Base Instruction Set (in addition to RV32I) ***
 +lwu      ............   ..... 110 ..... 0000011 @i
 +ld       ............   ..... 011 ..... 0000011 @i
 +sd       ....... .....  ..... 011 ..... 0100011 @s
 +addiw    ............   ..... 000 ..... 0011011 @i
 +slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
 +srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
 +sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
 +addw     0000000 .....  ..... 000 ..... 0111011 @r
 +subw     0100000 .....  ..... 000 ..... 0111011 @r
 +sllw     0000000 .....  ..... 001 ..... 0111011 @r
 +srlw     0000000 .....  ..... 101 ..... 0111011 @r
 +sraw     0100000 .....  ..... 101 ..... 0111011 @r
 +
  # *** RV32M Standard Extension ***
  mul      0000001 .....  ..... 000 ..... 0110011 @r
  mulh     0000001 .....  ..... 001 ..... 0110011 @r
@@ -XXX,XX +XXX,XX @@ divu     0000001 .....  ..... 101 ..... 0110011 @r
  rem      0000001 .....  ..... 110 ..... 0110011 @r
  remu     0000001 .....  ..... 111 ..... 0110011 @r
 +# *** RV64M Standard Extension (in addition to RV32M) ***
 +mulw     0000001 .....  ..... 000 ..... 0111011 @r
 +divw     0000001 .....  ..... 100 ..... 0111011 @r
 +divuw    0000001 .....  ..... 101 ..... 0111011 @r
 +remw     0000001 .....  ..... 110 ..... 0111011 @r
 +remuw    0000001 .....  ..... 111 ..... 0111011 @r
 +
  # *** RV32A Standard Extension ***
  lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
  sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
@@ -XXX,XX +XXX,XX @@ amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
  amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
  amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
 +# *** RV64A Standard Extension (in addition to RV32A) ***
 +lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
 +sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
 +amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
 +amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
 +amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
 +amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
 +amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
 +amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
 +amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
 +amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
 +amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
 +
  # *** RV32F Standard Extension ***
  flw        ............   ..... 010 ..... 0000111 @i
  fsw        .......  ..... ..... 010 ..... 0100111 @s
@@ -XXX,XX +XXX,XX @@ fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
  fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
  fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
 +# *** RV64F Standard Extension (in addition to RV32F) ***
 +fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
 +fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
 +fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
 +fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
 +
  # *** RV32D Standard Extension ***
  fld        ............   ..... 011 ..... 0000111 @i
  fsd        ....... .....  ..... 011 ..... 0100111 @s
@@ -XXX,XX +XXX,XX @@ fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
  fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
  fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
 +# *** RV64D Standard Extension (in addition to RV32D) ***
 +fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
 +fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
 +fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
 +fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
 +fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
 +fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
 +
  # *** RV32H Base Instruction Set ***
  hlv_b       0110000  00000  ..... 100 ..... 1110011 @r2
  hlv_bu      0110000  00001  ..... 100 ..... 1110011 @r2
@@ -XXX,XX +XXX,XX @@ hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
  hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
  hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
 -# *** RV32V Extension ***
 +# *** RV32H Base Instruction Set ***
 +hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
 +hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
 +hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
  # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
  vlb_v      ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
@@ -XXX,XX +XXX,XX @@ vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
  vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
  vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 +
 +#*** Vector AMO operations (in addition to Zvamo) ***
 +vamoswapd_v     00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
 +vamoaddd_v      00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 +vamoxord_v      00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 +vamoandd_v      01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 +vamoord_v       01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 +vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 +vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 +vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
 +vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
 diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/fpu_helper.c
 +++ b/target/riscv/fpu_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
      return (int32_t)float32_to_uint32(frs1, &env->fp_status);
  }
 -uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
 +target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
  {
      float32 frs1 = check_nanbox_s(rs1);
      return float32_to_int64(frs1, &env->fp_status);
  }
 -uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
 +target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
  {
      float32 frs1 = check_nanbox_s(rs1);
      return float32_to_uint64(frs1, &env->fp_status);
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
      return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
  }
 -uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
 +uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
  {
      return nanbox_s(int64_to_float32(rs1, &env->fp_status));
  }
 -uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
 +uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
  {
      return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
  }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
      return (int32_t)float64_to_uint32(frs1, &env->fp_status);
  }
 -uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
 +target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
  {
      return float64_to_int64(frs1, &env->fp_status);
  }
 -uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
 +target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
  {
      return float64_to_uint64(frs1, &env->fp_status);
  }
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
      return uint32_to_float64((uint32_t)rs1, &env->fp_status);
  }
 -uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
 +uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
  {
      return int64_to_float64(rs1, &env->fp_status);
  }
 -uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
 +uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
  {
      return uint64_to_float64(rs1, &env->fp_status);
  }
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
      }                              \
  } while (0)
 +#define REQUIRE_64BIT(ctx) do { \
 +    if (is_32bit(ctx)) {        \
 +        return false;           \
 +    }                           \
 +} while (0)
 +
  static int ex_rvc_register(DisasContext *ctx, int reg)
  {
      return 8 + reg;
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
      return true;
  }
- static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
+-#ifdef TARGET_RISCV64
- {
+ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
-     REQUIRE_ZICBOM(ctx);
+ {
--    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+     tcg_gen_add_tl(ret, arg1, arg2);
-+    TCGv src = get_address(ctx, a->rs1, 0);
+@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
 +
 +    gen_helper_cbo_clean_flush(tcg_env, src);
      return true;
  }
- static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
+-#endif
- {
+-
-     REQUIRE_ZICBOM(ctx);
+ static bool gen_arith(DisasContext *ctx, arg_r *a,
--    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+                       void(*func)(TCGv, TCGv, TCGv))
-+    TCGv src = get_address(ctx, a->rs1, 0);
+ {
-+
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
-+    gen_helper_cbo_inval(tcg_env, src);
+index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/vector_helper.c
 +++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w,  32, 32, H4, DO_MIN,  l)
  GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w,  32, 32, H4, DO_MAX,  l)
  GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
  GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
 -#ifdef TARGET_RISCV64
  GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
  GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
  GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d,  64, 32, H8, DO_ADD,  l)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
  GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
  GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
  GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
 -#endif
  static inline void
  vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong base,       \
                        GETPC());                                 \
  }
 -#ifdef TARGET_RISCV64
  GEN_VEXT_AMO(vamoswapw_v_d, int32_t,  int64_t,  idx_d, clearq)
  GEN_VEXT_AMO(vamoswapd_v_d, int64_t,  int64_t,  idx_d, clearq)
  GEN_VEXT_AMO(vamoaddw_v_d,  int32_t,  int64_t,  idx_d, clearq)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
  GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
  GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
  GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
 -#endif
  GEN_VEXT_AMO(vamoswapw_v_w, int32_t,  int32_t,  idx_w, clearl)
  GEN_VEXT_AMO(vamoaddw_v_w,  int32_t,  int32_t,  idx_w, clearl)
  GEN_VEXT_AMO(vamoxorw_v_w,  int32_t,  int32_t,  idx_w, clearl)
 diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rva.c.inc
 +++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
      return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
  }
 -#ifdef TARGET_RISCV64
 -
  static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
  }
  static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
  }
  static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
  }
  static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
  }
  static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
  }
  static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
  }
  static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
  }
  static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
  }
  static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
  }
  static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
  }
  static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
  }
 -#endif
 diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvd.c.inc
 +++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
      return true;
  }
- static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
+-#ifdef TARGET_RISCV64
- {
+-
-     REQUIRE_ZICBOZ(ctx);
+ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
--    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+ {
-+    TCGv src = get_address(ctx, a->rs1, 0);
++    REQUIRE_64BIT(ctx);
-+
+     REQUIRE_FPU;
-+    gen_helper_cbo_zero(tcg_env, src);
+     REQUIRE_EXT(ctx, RVD);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
  static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
  static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 +#ifdef TARGET_RISCV64
      gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
      return true;
- }
++#else
 +    qemu_build_not_reached();
 +#endif
  }
  static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
  static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
  static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 +#ifdef TARGET_RISCV64
      TCGv t0 = tcg_temp_new();
      gen_get_gpr(t0, a->rs1);
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
      tcg_temp_free(t0);
      mark_fs_dirty(ctx);
      return true;
 -}
 +#else
 +    qemu_build_not_reached();
  #endif
 +}
 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvf.c.inc
 +++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
      return true;
  }
 -#ifdef TARGET_RISCV64
  static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
  static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
  static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
  static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
      tcg_temp_free(t0);
      return true;
  }
 -#endif
 diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvh.c.inc
 +++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
  #endif
  }
 -#ifdef TARGET_RISCV64
  static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVH);
 +
  #ifndef CONFIG_USER_ONLY
      TCGv t0 = tcg_temp_new();
      TCGv t1 = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
  static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVH);
 +
  #ifndef CONFIG_USER_ONLY
      TCGv t0 = tcg_temp_new();
      TCGv t1 = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
  static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVH);
 +
  #ifndef CONFIG_USER_ONLY
      TCGv t0 = tcg_temp_new();
      TCGv dat = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
      return false;
  #endif
  }
 -#endif
  static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
  {
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
      return gen_store(ctx, a, MO_TESL);
  }
 -#ifdef TARGET_RISCV64
  static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_load(ctx, a, MO_TEUL);
  }
  static bool trans_ld(DisasContext *ctx, arg_ld *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_load(ctx, a, MO_TEQ);
  }
  static bool trans_sd(DisasContext *ctx, arg_sd *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_store(ctx, a, MO_TEQ);
  }
 -#endif
  static bool trans_addi(DisasContext *ctx, arg_addi *a)
  {
@@ -XXX,XX +XXX,XX @@ static bool trans_and(DisasContext *ctx, arg_and *a)
      return gen_arith(ctx, a, &tcg_gen_and_tl);
  }
 -#ifdef TARGET_RISCV64
  static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_arith_imm_tl(ctx, a, &gen_addw);
  }
  static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
  {
 +    REQUIRE_64BIT(ctx);
      TCGv source1;
      source1 = tcg_temp_new();
      gen_get_gpr(source1, a->rs1);
@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
  static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
  {
 +    REQUIRE_64BIT(ctx);
      TCGv t = tcg_temp_new();
      gen_get_gpr(t, a->rs1);
      tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
  static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
  {
 +    REQUIRE_64BIT(ctx);
      TCGv t = tcg_temp_new();
      gen_get_gpr(t, a->rs1);
      tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -XXX,XX +XXX,XX @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
  static bool trans_addw(DisasContext *ctx, arg_addw *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_arith(ctx, a, &gen_addw);
  }
  static bool trans_subw(DisasContext *ctx, arg_subw *a)
  {
 +    REQUIRE_64BIT(ctx);
      return gen_arith(ctx, a, &gen_subw);
  }
  static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
  {
 +    REQUIRE_64BIT(ctx);
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
  static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
  {
 +    REQUIRE_64BIT(ctx);
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
  static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
  {
 +    REQUIRE_64BIT(ctx);
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
      return true;
  }
 -#endif
  static bool trans_fence(DisasContext *ctx, arg_fence *a)
  {
 diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvm.c.inc
 +++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
      return gen_arith(ctx, a, &gen_remu);
  }
 -#ifdef TARGET_RISCV64
  static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 +
      return gen_arith(ctx, a, &gen_mulw);
  }
  static bool trans_divw(DisasContext *ctx, arg_divw *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 +
      return gen_arith_div_w(ctx, a, &gen_div);
  }
  static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 +
      return gen_arith_div_uw(ctx, a, &gen_divu);
  }
  static bool trans_remw(DisasContext *ctx, arg_remw *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 +
      return gen_arith_div_w(ctx, a, &gen_rem);
  }
  static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
  {
 +    REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 +
      return gen_arith_div_uw(ctx, a, &gen_remu);
  }
 -#endif
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
          gen_helper_vamominuw_v_w,
          gen_helper_vamomaxuw_v_w
      };
 -#ifdef TARGET_RISCV64
      static gen_helper_amo *const fnsd[18] = {
          gen_helper_vamoswapw_v_d,
          gen_helper_vamoaddw_v_d,
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
          gen_helper_vamominud_v_d,
          gen_helper_vamomaxud_v_d
      };
 -#endif
      if (tb_cflags(s->base.tb) & CF_PARALLEL) {
          gen_helper_exit_atomic(cpu_env);
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
          return true;
      } else {
          if (s->sew == 3) {
 -#ifdef TARGET_RISCV64
 -            fn = fnsd[seq];
 -#else
 -            /* Check done in amo_check(). */
 -            g_assert_not_reached();
 -#endif
 +            if (!is_32bit(s)) {
 +                fn = fnsd[seq];
 +            } else {
 +                /* Check done in amo_check(). */
 +                g_assert_not_reached();
 +            }
          } else {
              assert(seq < ARRAY_SIZE(fnsw));
              fn = fnsw[seq];
@@ -XXX,XX +XXX,XX @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
              ((1 << s->sew) >= 4));
  }
 +static bool amo_check64(DisasContext *s, arg_rwdvm* a)
 +{
 +    return !is_32bit(s) && amo_check(s, a);
 +}
 +
  GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
  GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
  GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
  GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
  GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
  GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
 -#ifdef TARGET_RISCV64
 -GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
 -GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
 -GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
 -GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
 -GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
 -GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
 -GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
 -GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
 -GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
 -#endif
 +GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64)
 +GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64)
 +GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64)
 +GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64)
 +GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64)
 +GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64)
 +GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64)
 +GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64)
 +GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64)
  /*
   *** Vector Integer Arithmetic Instructions
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ gen32 = [
  gen64 = [
    decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
 -  decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
 +  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
  ]
  riscv_ss = ss.source_set()
 --
-.45.1
+.31.1

-[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
+[PULL v2 41/42] target/riscv: Consolidate RV32/64 16-bit instructions
-From: Andrew Jones <ajones@ventanamicro.com>
+This patch removes the insn16-32.decode and insn16-64.decode decode
 files and consolidates the instructions into the general RISC-V
 insn16.decode decode tree.
-Implementing wrs.nto to always just return is consistent with the
+This means that all of the instructions are avaliable in both the 32-bit
-specification, as the instruction is permitted to terminate the
+and 64-bit builds. This also means that we run a check to ensure we are
-stall for any reason, but it's not useful for virtualization, where
+running a 64-bit softmmu before we execute the 64-bit only instructions.
-we'd like the guest to trap to the hypervisor in order to allow
+This allows us to include the 32-bit instructions in the 64-bit build,
-scheduling of the lock holding VCPU. Change to always immediately
+while also ensuring that 32-bit only software can not execute the
-raise exceptions when the appropriate conditions are present,
+instructions.
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
 ---
- target/riscv/helper.h                       |  1 +
+ target/riscv/insn16-32.decode           | 28 -------------------
- target/riscv/op_helper.c                    | 11 ++++++++
+ target/riscv/insn16-64.decode           | 36 -------------------------
- target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
+ target/riscv/insn16.decode              | 30 +++++++++++++++++++++
-files changed, 32 insertions(+), 9 deletions(-)
+ target/riscv/insn_trans/trans_rvi.c.inc |  6 +++++
  target/riscv/meson.build                | 11 +++-----
 files changed, 39 insertions(+), 72 deletions(-)
  delete mode 100644 target/riscv/insn16-32.decode
  delete mode 100644 target/riscv/insn16-64.decode
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
+diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/target/riscv/insn16-32.decode
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -#
 -# RISC-V translation routines for the RVXI Base Integer Instruction Set.
 -#
 -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
 -#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
 -#
 -# This program is free software; you can redistribute it and/or modify it
 -# under the terms and conditions of the GNU General Public License,
 -# version 2 or later, as published by the Free Software Foundation.
 -#
 -# This program is distributed in the hope it will be useful, but WITHOUT
 -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 -# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 -# more details.
 -#
 -# You should have received a copy of the GNU General Public License along with
 -# this program.  If not, see <http://www.gnu.org/licenses/>.
 -
 -# *** RV32C Standard Extension (Quadrant 0) ***
 -flw               011  ... ... .. ... 00 @cl_w
 -fsw               111  ... ... .. ... 00 @cs_w
 -
 -# *** RV32C Standard Extension (Quadrant 1) ***
 -jal               001     ........... 01 @cj    rd=1  # C.JAL
 -
 -# *** RV32C Standard Extension (Quadrant 2) ***
 -flw               011 .  .....  ..... 10 @c_lwsp
 -fsw               111 .  .....  ..... 10 @c_swsp
 diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/target/riscv/insn16-64.decode
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -#
 -# RISC-V translation routines for the RVXI Base Integer Instruction Set.
 -#
 -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
 -#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
 -#
 -# This program is free software; you can redistribute it and/or modify it
 -# under the terms and conditions of the GNU General Public License,
 -# version 2 or later, as published by the Free Software Foundation.
 -#
 -# This program is distributed in the hope it will be useful, but WITHOUT
 -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 -# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 -# more details.
 -#
 -# You should have received a copy of the GNU General Public License along with
 -# this program.  If not, see <http://www.gnu.org/licenses/>.
 -
 -# *** RV64C Standard Extension (Quadrant 0) ***
 -ld                011  ... ... .. ... 00 @cl_d
 -sd                111  ... ... .. ... 00 @cs_d
 -
 -# *** RV64C Standard Extension (Quadrant 1) ***
 -{
 -  illegal         001 -  00000  ----- 01 # c.addiw, RES rd=0
 -  addiw           001 .  .....  ..... 01 @ci
 -}
 -subw              100 1 11 ... 00 ... 01 @cs_2
 -addw              100 1 11 ... 01 ... 01 @cs_2
 -
 -# *** RV64C Standard Extension (Quadrant 2) ***
 -{
 -  illegal         011 -  00000  ----- 10 # c.ldsp, RES rd=0
 -  ld              011 .  .....  ..... 10 @c_ldsp
 -}
 -sd                111 .  .....  ..... 10 @c_sdsp
 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
+--- a/target/riscv/insn16.decode
-+++ b/target/riscv/helper.h
++++ b/target/riscv/insn16.decode
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
+@@ -XXX,XX +XXX,XX @@ lw                010  ... ... .. ... 00 @cl_w
- DEF_HELPER_1(sret, tl, env)
+ fsd               101  ... ... .. ... 00 @cs_d
- DEF_HELPER_1(mret, tl, env)
+ sw                110  ... ... .. ... 00 @cs_w
- DEF_HELPER_1(wfi, void, env)
-+DEF_HELPER_1(wrs_nto, void, env)
++# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
  DEF_HELPER_1(tlb_flush, void, env)
  DEF_HELPER_1(tlb_flush_all, void, env)
  /* Native Debug */
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
      }
  }
 +void helper_wrs_nto(CPURISCVState *env)
 +{
-+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
++  ld              011  ... ... .. ... 00 @cl_d
-+        get_field(env->hstatus, HSTATUS_VTW) &&
++  flw             011  ... ... .. ... 00 @cl_w
-+        !get_field(env->mstatus, MSTATUS_TW)) {
++}
-+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
++{
-+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
++  sd              111  ... ... .. ... 00 @cs_d
-+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
++  fsw             111  ... ... .. ... 00 @cs_w
 +    }
 +}
 +
- void helper_tlb_flush(CPURISCVState *env)
+ # *** RV32/64C Standard Extension (Quadrant 1) ***
- {
+ addi              000 .  .....  ..... 01 @ci
-     CPUState *cs = env_cpu(env);
+ addi              010 .  .....  ..... 01 @c_li
-diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
+@@ -XXX,XX +XXX,XX @@ jal               101     ........... 01 @cj    rd=0  # C.J
  beq               110  ... ...  ..... 01 @cb_z
  bne               111  ... ...  ..... 01 @cb_z
 +# *** RV64C and RV32C specific Standard Extension (Quadrant 1) ***
 +{
 +  c64_illegal     001 -  00000  ----- 01 # c.addiw, RES rd=0
 +  addiw           001 .  .....  ..... 01 @ci
 +  jal             001     ........... 01 @cj    rd=1  # C.JAL
 +}
 +subw              100 1 11 ... 00 ... 01 @cs_2
 +addw              100 1 11 ... 01 ... 01 @cs_2
 +
  # *** RV32/64C Standard Extension (Quadrant 2) ***
  slli              000 .  .....  ..... 10 @c_shift2
  fld               001 .  .....  ..... 10 @c_ldsp
@@ -XXX,XX +XXX,XX @@ fld               001 .  .....  ..... 10 @c_ldsp
  }
  fsd               101   ......  ..... 10 @c_sdsp
  sw                110 .  .....  ..... 10 @c_swsp
 +
 +# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
 +{
 +  c64_illegal     011 -  00000  ----- 10 # c.ldsp, RES rd=0
 +  ld              011 .  .....  ..... 10 @c_ldsp
 +  flw             011 .  .....  ..... 10 @c_lwsp
 +}
 +{
 +  sd              111 .  .....  ..... 10 @c_sdsp
 +  fsw             111 .  .....  ..... 10 @c_swsp
 +}
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+--- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
++++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
 -static bool trans_wrs(DisasContext *ctx)
 +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
  {
      if (!ctx->cfg_ptr->ext_zawrs) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      return true;
  }
--#define GEN_TRANS_WRS(insn)                                     \
++static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
 -static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
 -{                                                               \
 -    (void)a;                                                    \
 -    return trans_wrs(ctx);                                      \
 -}
 +static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
 +{
-+    if (!ctx->cfg_ptr->ext_zawrs) {
++     REQUIRE_64BIT(ctx);
-+        return false;
++     return trans_illegal(ctx, a);
-+    }
++}
 -GEN_TRANS_WRS(wrs_nto)
 -GEN_TRANS_WRS(wrs_sto)
 +    /*
 +     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
 +     * should raise an exception when the implementation-specific bounded time
 +     * limit has expired. Our time limit is zero, so we either return
 +     * immediately, as does our implementation of wrs.sto, or raise an
 +     * exception, as handled by the wrs.nto helper.
 +     */
 +#ifndef CONFIG_USER_ONLY
 +    gen_helper_wrs_nto(tcg_env);
 +#endif
 +
-+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+ static bool trans_lui(DisasContext *ctx, arg_lui *a)
-+    return trans_wrs_sto(ctx, NULL);
+ {
-+}
+     if (a->rd != 0) {
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@
  # FIXME extra_args should accept files()
  dir = meson.current_source_dir()
 -gen32 = [
 -  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
 -  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
 -]
 -gen64 = [
 -  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
 +gen = [
 +  decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
    decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
  ]
  riscv_ss = ss.source_set()
 -riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
 -riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
 +riscv_ss.add(gen)
  riscv_ss.add(files(
    'cpu.c',
    'cpu_helper.c',
 --
-.45.1
+.31.1

-New patch
+[PULL v2 42/42] target/riscv: Fix the RV64H decode comment
+BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
+---
+ target/riscv/insn32.decode | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn32.decode
++++ b/target/riscv/insn32.decode
+@@ -XXX,XX +XXX,XX @@ hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
+ hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
+ hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
+-# *** RV32H Base Instruction Set ***
++# *** RV64H Base Instruction Set ***
+ hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
+ hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
+ hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
+--
+.31.1

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1

The following changes since commit d45a5270d075ea589f0b0ddcf963a5fea1f500ac:

Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging (2021-05-05 13:52:00 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210506

for you to fetch changes up to d9e1a4683bc52ff218dcc133f73017bc4c496346:

target/riscv: Fix the RV64H decode comment (2021-05-06 08:59:59 +1000)

----------------------------------------------------------------
A large collection of RISC-V fixes, improvements and features

- Clenaup some left over v1.9 code
 - Documentation improvements
 - Support for the shakti_c machine
 - Internal cleanup of the CSR accesses
 - Updates to the OpenTitan platform
 - Support for the virtio-vga
 - Fix for the saturate subtract in vector extensions
 - Experimental support for the ePMP spec
 - A range of other internal code cleanups and bug fixes

----------------------------------------------------------------
Alexander Wagner (1):
      hw/riscv: Fix OT IBEX reset vector

Alistair Francis (22):
      target/riscv: Convert the RISC-V exceptions to an enum
      target/riscv: Use the RISCVException enum for CSR predicates
      target/riscv: Fix 32-bit HS mode access permissions
      target/riscv: Use the RISCVException enum for CSR operations
      target/riscv: Use RISCVException enum for CSR access
      MAINTAINERS: Update the RISC-V CPU Maintainers
      hw/opentitan: Update the interrupt layout
      hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
      target/riscv: Fix the PMP is locked check when using TOR
      target/riscv: Add the ePMP feature
      target/riscv/pmp: Remove outdated comment
      target/riscv: Add ePMP support for the Ibex CPU
      target/riscv: Remove the hardcoded RVXLEN macro
      target/riscv: Remove the hardcoded SSTATUS_SD macro
      target/riscv: Remove the hardcoded HGATP_MODE macro
      target/riscv: Remove the hardcoded MSTATUS_SD macro
      target/riscv: Remove the hardcoded SATP_MODE macro
      target/riscv: Remove the unused HSTATUS_WPRI macro
      target/riscv: Remove an unused CASE_OP_32_64 macro
      target/riscv: Consolidate RV32/64 32-bit instructions
      target/riscv: Consolidate RV32/64 16-bit instructions
      target/riscv: Fix the RV64H decode comment

Atish Patra (1):
      target/riscv: Remove privilege v1.9 specific CSR related code

Axel Heider (1):
      docs/system/generic-loader.rst: Fix style

Bin Meng (1):
      hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]

Dylan Jhong (1):
      target/riscv: Align the data type of reset vector address

Emmanuel Blot (2):
      target/riscv: fix exception index on instruction access fault
      target/riscv: fix a typo with interrupt names

Frank Chang (2):
      target/riscv: fix vrgather macro index variable type bug
      fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

Hou Weiying (4):
      target/riscv: Define ePMP mseccfg
      target/riscv: Add ePMP CSR access functions
      target/riscv: Implementation of enhanced PMP (ePMP)
      target/riscv: Add a config option for ePMP

Jade Fink (1):
      riscv: don't look at SUM when accessing memory from a debugger context

LIU Zhiwei (1):
      target/riscv: Fixup saturate subtract function

Vijai Kumar K (5):
      target/riscv: Add Shakti C class CPU
      riscv: Add initial support for Shakti C machine
      hw/char: Add Shakti UART emulation
      hw/riscv: Connect Shakti UART to Shakti platform
      docs: Add documentation for shakti_c machine

docs/system/generic-loader.rst              |   9 +-
 docs/system/riscv/shakti-c.rst              |  82 +++
 docs/system/target-riscv.rst                |   1 +
 default-configs/devices/riscv64-softmmu.mak |   1 +
 include/hw/char/shakti_uart.h               |  74 +++
 include/hw/riscv/opentitan.h                |  16 +-
 include/hw/riscv/shakti_c.h                 |  75 +++
 target/riscv/cpu.h                          |  42 +-
 target/riscv/cpu_bits.h                     | 114 +---
 target/riscv/helper.h                       |  18 +-
 target/riscv/pmp.h                          |  14 +
 target/riscv/insn16-32.decode               |  28 -
 target/riscv/insn16-64.decode               |  36 --
 target/riscv/insn16.decode                  |  30 +
 target/riscv/insn32-64.decode               |  88 ---
 target/riscv/insn32.decode                  |  67 ++-
 hw/char/shakti_uart.c                       | 185 +++++++
 hw/intc/ibex_plic.c                         |  20 +-
 hw/riscv/opentitan.c                        |  10 +-
 hw/riscv/shakti_c.c                         | 178 ++++++
 hw/riscv/sifive_e.c                         |   2 +-
 target/riscv/cpu.c                          |  26 +-
 target/riscv/cpu_helper.c                   |  88 ++-
 target/riscv/csr.c                          | 824 +++++++++++++++++-----------
 target/riscv/fpu_helper.c                   |  16 +-
 target/riscv/gdbstub.c                      |   8 +-
 target/riscv/machine.c                      |   8 +-
 target/riscv/monitor.c                      |  22 +-
 target/riscv/op_helper.c                    |  18 +-
 target/riscv/pmp.c                          | 218 +++++++-
 target/riscv/translate.c                    |  38 +-
 target/riscv/vector_helper.c                |  18 +-
 fpu/softfloat-specialize.c.inc              |   6 +
 target/riscv/insn_trans/trans_rva.c.inc     |  14 +-
 target/riscv/insn_trans/trans_rvd.c.inc     |  17 +-
 target/riscv/insn_trans/trans_rvf.c.inc     |   6 +-
 target/riscv/insn_trans/trans_rvh.c.inc     |   8 +-
 target/riscv/insn_trans/trans_rvi.c.inc     |  22 +-
 target/riscv/insn_trans/trans_rvm.c.inc     |  12 +-
 target/riscv/insn_trans/trans_rvv.c.inc     |  39 +-
 MAINTAINERS                                 |  14 +-
 hw/char/meson.build                         |   1 +
 hw/char/trace-events                        |   4 +
 hw/riscv/Kconfig                            |  11 +
 hw/riscv/meson.build                        |   1 +
 target/riscv/meson.build                    |  13 +-
 target/riscv/trace-events                   |   3 +
 47 files changed, 1756 insertions(+), 789 deletions(-)
 create mode 100644 docs/system/riscv/shakti-c.rst
 create mode 100644 include/hw/char/shakti_uart.h
 create mode 100644 include/hw/riscv/shakti_c.h
 delete mode 100644 target/riscv/insn16-32.decode
 delete mode 100644 target/riscv/insn16-64.decode
 delete mode 100644 target/riscv/insn32-64.decode
 create mode 100644 hw/char/shakti_uart.c
 create mode 100644 hw/riscv/shakti_c.c

From: Atish Patra <atish.patra@wdc.com>

Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com>
[Changes by AF:
 - Rebase on latest patches
 - Bump the vmstate_riscv_cpu version_id and minimum_version_id
 ]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  4 +---
 target/riscv/cpu_bits.h   | 23 ---------------------
 target/riscv/cpu.c        |  2 +-
 target/riscv/cpu_helper.c | 12 +++++------
 target/riscv/csr.c        | 42 ++++++++++-----------------------------
 target/riscv/machine.c    |  8 +++-----
 target/riscv/translate.c  |  4 ++--
 7 files changed, 23 insertions(+), 72 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong mie;
     target_ulong mideleg;
 
-    target_ulong sptbr;  /* until: priv-1.9.1 */
     target_ulong satp;   /* since: priv-1.10.0 */
-    target_ulong sbadaddr;
-    target_ulong mbadaddr;
+    target_ulong stval;
     target_ulong medeleg;
 
     target_ulong stvec;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 /* 32-bit only */
 #define CSR_MSTATUSH        0x310
 
-/* Legacy Counter Setup (priv v1.9.1) */
-/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
-#define CSR_MUCOUNTEREN     0x320
-#define CSR_MSCOUNTEREN     0x321
-#define CSR_MHCOUNTEREN     0x322
-
 /* Machine Trap Handling */
 #define CSR_MSCRATCH        0x340
 #define CSR_MEPC            0x341
@@ -XXX,XX +XXX,XX @@
 #define CSR_MTVAL           0x343
 #define CSR_MIP             0x344
 
-/* Legacy Machine Trap Handling (priv v1.9.1) */
-#define CSR_MBADADDR        0x343
-
 /* Supervisor Trap Setup */
 #define CSR_SSTATUS         0x100
 #define CSR_SEDELEG         0x102
@@ -XXX,XX +XXX,XX @@
 #define CSR_STVAL           0x143
 #define CSR_SIP             0x144
 
-/* Legacy Supervisor Trap Handling (priv v1.9.1) */
-#define CSR_SBADADDR        0x143
-
 /* Supervisor Protection and Translation */
 #define CSR_SPTBR           0x180
 #define CSR_SATP            0x180
@@ -XXX,XX +XXX,XX @@
 #define CSR_MHPMCOUNTER30H  0xb9e
 #define CSR_MHPMCOUNTER31H  0xb9f
 
-/* Legacy Machine Protection and Translation (priv v1.9.1) */
-#define CSR_MBASE           0x380
-#define CSR_MBOUND          0x381
-#define CSR_MIBASE          0x382
-#define CSR_MIBOUND         0x383
-#define CSR_MDBASE          0x384
-#define CSR_MDBOUND         0x385
-
 /* mstatus CSR bits */
 #define MSTATUS_UIE         0x00000001
 #define MSTATUS_SIE         0x00000002
@@ -XXX,XX +XXX,XX @@
 #define MSTATUS_FS          0x00006000
 #define MSTATUS_XS          0x00018000
 #define MSTATUS_MPRV        0x00020000
-#define MSTATUS_PUM         0x00040000 /* until: priv-1.9.1 */
 #define MSTATUS_SUM         0x00040000 /* since: priv-1.10 */
 #define MSTATUS_MXR         0x00080000
-#define MSTATUS_VM          0x1F000000 /* until: priv-1.9.1 */
 #define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */
 #define MSTATUS_TW          0x00200000 /* since: priv-1.10 */
 #define MSTATUS_TSR         0x00400000 /* since: priv-1.10 */
@@ -XXX,XX +XXX,XX @@
 #define SSTATUS_SPP         0x00000100
 #define SSTATUS_FS          0x00006000
 #define SSTATUS_XS          0x00018000
-#define SSTATUS_PUM         0x00040000 /* until: priv-1.9.1 */
 #define SSTATUS_SUM         0x00040000 /* since: priv-1.10 */
 #define SSTATUS_MXR         0x00080000
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
     }
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
     if (riscv_has_ext(env, RVH)) {
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
         env->vscause = env->scause;
         env->scause = env->scause_hs;
 
-        env->vstval = env->sbadaddr;
-        env->sbadaddr = env->stval_hs;
+        env->vstval = env->stval;
+        env->stval = env->stval_hs;
 
         env->vsatp = env->satp;
         env->satp = env->satp_hs;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
         env->scause_hs = env->scause;
         env->scause = env->vscause;
 
-        env->stval_hs = env->sbadaddr;
-        env->sbadaddr = env->vstval;
+        env->stval_hs = env->stval;
+        env->stval = env->vstval;
 
         env->satp_hs = env->satp;
         env->satp = env->vsatp;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         env->mstatus = s;
         env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
         env->sepc = env->pc;
-        env->sbadaddr = tval;
+        env->stval = tval;
         env->htval = htval;
         env->pc = (env->stvec >> 2 << 2) +
             ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         env->mstatus = s;
         env->mcause = cause | ~(((target_ulong)-1) >> async);
         env->mepc = env->pc;
-        env->mbadaddr = tval;
+        env->mtval = tval;
         env->mtval2 = mtval2;
         env->pc = (env->mtvec >> 2 << 2) +
             ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
-static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
-{
-    if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
-    *val = env->mcounteren;
-    return 0;
-}
-
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
-static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
-{
-    if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return -RISCV_EXCP_ILLEGAL_INST;
-    }
-    env->mcounteren = val;
-    return 0;
-}
-
 /* Machine Trap Handling */
 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
+static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
 {
-    *val = env->mbadaddr;
+    *val = env->mtval;
     return 0;
 }
 
-static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
+static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
 {
-    env->mbadaddr = val;
+    env->mtval = val;
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
+static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
 {
-    *val = env->sbadaddr;
+    *val = env->stval;
     return 0;
 }
 
-static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
+static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
 {
-    env->sbadaddr = val;
+    env->stval = val;
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
 
     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
 
-    [CSR_MSCOUNTEREN] = { "msounteren", any,   read_mscounteren, write_mscounteren },
-
     /* Machine Trap Handling */
     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch },
     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
-    [CSR_MBADADDR] = { "mbadaddr", any,  read_mbadaddr, write_mbadaddr },
+    [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
 
     /* Supervisor Trap Setup */
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
-    [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
+    [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
 
     /* Supervisor Protection and Translation */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
 
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         VMSTATE_UINT32(env.miclaim, RISCVCPU),
         VMSTATE_UINTTL(env.mie, RISCVCPU),
         VMSTATE_UINTTL(env.mideleg, RISCVCPU),
-        VMSTATE_UINTTL(env.sptbr, RISCVCPU),
         VMSTATE_UINTTL(env.satp, RISCVCPU),
-        VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
-        VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
+        VMSTATE_UINTTL(env.stval, RISCVCPU),
         VMSTATE_UINTTL(env.medeleg, RISCVCPU),
         VMSTATE_UINTTL(env.stvec, RISCVCPU),
         VMSTATE_UINTTL(env.sepc, RISCVCPU),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void generate_exception(DisasContext *ctx, int excp)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
+static void generate_exception_mtval(DisasContext *ctx, int excp)
 {
     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
 
 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 {
-    generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
+    generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
 }
 
 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
-- 
2.31.1

From: Axel Heider <axelheider@gmx.de>

Fix style to have a proper description of the parameter 'force-raw'.

Signed-off-by: Axel Heider <axelheider@gmx.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a659ac@gmx.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/generic-loader.rst | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/generic-loader.rst
+++ b/docs/system/generic-loader.rst
@@ -XXX,XX +XXX,XX @@ shown below:
   specified in the executable format header. This option should only
   be used for the boot image. This will also cause the image to be
   written to the specified CPU's address space. If not specified, the
-  default is CPU 0. <force-raw> - Setting force-raw=on forces the file
-  to be treated as a raw image. This can be used to load supported
-  executable formats as if they were raw.
+  default is CPU 0.
+
+``<force-raw>``
+  Setting 'force-raw=on' forces the file to be treated as a raw image.
+  This can be used to load supported executable formats as if they
+  were raw.
 
 All values are parsed using the standard QemuOpts parsing. This allows the user
 to specify any values in any format supported. By default the values
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

This was accidentally dropped before. Add it back.

Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
Reported-by: Emmanuel Blot <eblot.ml@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210331103612.654261-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_e.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/arch_init.h"
 #include "sysemu/sysemu.h"
 
-static MemMapEntry sifive_e_memmap[] = {
+static const MemMapEntry sifive_e_memmap[] = {
     [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
     [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
     [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

C-Class is a member of the SHAKTI family of processors from IIT-M.

It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 1 +
 target/riscv/cpu.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
 #endif
 };
 
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.

https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-3-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/devices/riscv64-softmmu.mak |   1 +
 include/hw/riscv/shakti_c.h                 |  73 +++++++++
 hw/riscv/shakti_c.c                         | 170 ++++++++++++++++++++
 MAINTAINERS                                 |   7 +
 hw/riscv/Kconfig                            |  10 ++
 hw/riscv/meson.build                        |   1 +
 6 files changed, 262 insertions(+)
 create mode 100644 include/hw/riscv/shakti_c.h
 create mode 100644 hw/riscv/shakti_c.c

diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/devices/riscv64-softmmu.mak
+++ b/default-configs/devices/riscv64-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_SIFIVE_E=y
 CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
 CONFIG_MICROCHIP_PFSOC=y
+CONFIG_SHAKTI_C=y
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/riscv/shakti_c.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SHAKTI_H
+#define HW_SHAKTI_H
+
+#include "hw/riscv/riscv_hart.h"
+#include "hw/boards.h"
+
+#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
+#define RISCV_SHAKTI_SOC(obj) \
+    OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
+
+typedef struct ShaktiCSoCState {
+    /*< private >*/
+    DeviceState parent_obj;
+
+    /*< public >*/
+    RISCVHartArrayState cpus;
+    DeviceState *plic;
+    MemoryRegion rom;
+
+} ShaktiCSoCState;
+
+#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
+#define RISCV_SHAKTI_MACHINE(obj) \
+    OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
+typedef struct ShaktiCMachineState {
+    /*< private >*/
+    MachineState parent_obj;
+
+    /*< public >*/
+    ShaktiCSoCState soc;
+} ShaktiCMachineState;
+
+enum {
+    SHAKTI_C_ROM,
+    SHAKTI_C_RAM,
+    SHAKTI_C_UART,
+    SHAKTI_C_GPIO,
+    SHAKTI_C_PLIC,
+    SHAKTI_C_CLINT,
+    SHAKTI_C_I2C,
+};
+
+#define SHAKTI_C_PLIC_HART_CONFIG "MS"
+/* Including Interrupt ID 0 (no interrupt)*/
+#define SHAKTI_C_PLIC_NUM_SOURCES 28
+/* Excluding Priority 0 */
+#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
+#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
+#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
+#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
+#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
+#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
+#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
+
+#endif
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/riscv/shakti_c.h"
+#include "qapi/error.h"
+#include "hw/intc/sifive_plic.h"
+#include "hw/intc/sifive_clint.h"
+#include "sysemu/sysemu.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "hw/riscv/boot.h"
+
+
+static const struct MemmapEntry {
+    hwaddr base;
+    hwaddr size;
+} shakti_c_memmap[] = {
+    [SHAKTI_C_ROM]   =  {  0x00001000,  0x2000   },
+    [SHAKTI_C_RAM]   =  {  0x80000000,  0x0      },
+    [SHAKTI_C_UART]  =  {  0x00011300,  0x00040  },
+    [SHAKTI_C_GPIO]  =  {  0x020d0000,  0x00100  },
+    [SHAKTI_C_PLIC]  =  {  0x0c000000,  0x20000  },
+    [SHAKTI_C_CLINT] =  {  0x02000000,  0xc0000  },
+    [SHAKTI_C_I2C]   =  {  0x20c00000,  0x00100  },
+};
+
+static void shakti_c_machine_state_init(MachineState *mstate)
+{
+    ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+
+    /* Allow only Shakti C CPU for this platform */
+    if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
+        error_report("This board can only be used with Shakti C CPU");
+        exit(1);
+    }
+
+    /* Initialize SoC */
+    object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
+                            TYPE_RISCV_SHAKTI_SOC);
+    qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
+
+    /* register RAM */
+    memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
+                           mstate->ram_size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                shakti_c_memmap[SHAKTI_C_RAM].base,
+                                main_mem);
+
+    /* ROM reset vector */
+    riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
+                              shakti_c_memmap[SHAKTI_C_RAM].base,
+                              shakti_c_memmap[SHAKTI_C_ROM].base,
+                              shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
+                              NULL);
+    riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].base,
+                        NULL);
+}
+
+static void shakti_c_machine_instance_init(Object *obj)
+{
+}
+
+static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(klass);
+    mc->desc = "RISC-V Board compatible with Shakti SDK";
+    mc->init = shakti_c_machine_state_init;
+    mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
+}
+
+static const TypeInfo shakti_c_machine_type_info = {
+    .name = TYPE_RISCV_SHAKTI_MACHINE,
+    .parent = TYPE_MACHINE,
+    .class_init = shakti_c_machine_class_init,
+    .instance_init = shakti_c_machine_instance_init,
+    .instance_size = sizeof(ShaktiCMachineState),
+};
+
+static void shakti_c_machine_type_info_register(void)
+{
+    type_register_static(&shakti_c_machine_type_info);
+}
+type_init(shakti_c_machine_type_info_register)
+
+static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
+{
+    ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
+    MemoryRegion *system_memory = get_system_memory();
+
+    sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
+
+    sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
+        (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
+        SHAKTI_C_PLIC_NUM_SOURCES,
+        SHAKTI_C_PLIC_NUM_PRIORITIES,
+        SHAKTI_C_PLIC_PRIORITY_BASE,
+        SHAKTI_C_PLIC_PENDING_BASE,
+        SHAKTI_C_PLIC_ENABLE_BASE,
+        SHAKTI_C_PLIC_ENABLE_STRIDE,
+        SHAKTI_C_PLIC_CONTEXT_BASE,
+        SHAKTI_C_PLIC_CONTEXT_STRIDE,
+        shakti_c_memmap[SHAKTI_C_PLIC].size);
+
+    sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
+        shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+        SIFIVE_CLINT_TIMEBASE_FREQ, false);
+
+    /* ROM */
+    memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
+                           shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+        shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
+}
+
+static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    dc->realize = shakti_c_soc_state_realize;
+}
+
+static void shakti_c_soc_instance_init(Object *obj)
+{
+    ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
+
+    object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+
+    /*
+     * CPU type is fixed and we are not supporting passing from commandline yet.
+     * So let it be in instance_init. When supported should use ms->cpu_type
+     * instead of TYPE_RISCV_CPU_SHAKTI_C
+     */
+    object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
+                            TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
+    object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
+                            &error_abort);
+}
+
+static const TypeInfo shakti_c_type_info = {
+    .name = TYPE_RISCV_SHAKTI_SOC,
+    .parent = TYPE_DEVICE,
+    .class_init = shakti_c_soc_class_init,
+    .instance_init = shakti_c_soc_instance_init,
+    .instance_size = sizeof(ShaktiCSoCState),
+};
+
+static void shakti_c_type_info_register(void)
+{
+    type_register_static(&shakti_c_type_info);
+}
+type_init(shakti_c_type_info_register)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/mchp_pfsoc_dmc.h
 F: include/hw/misc/mchp_pfsoc_ioscb.h
 F: include/hw/misc/mchp_pfsoc_sysreg.h
 
+Shakti C class SoC
+M: Vijai Kumar K <vijai@behindbytes.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: hw/riscv/shakti_c.c
+F: include/hw/riscv/shakti_c.h
+
 SiFive Machines
 M: Alistair Francis <Alistair.Francis@wdc.com>
 M: Bin Meng <bin.meng@windriver.com>
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config OPENTITAN
     select IBEX
     select UNIMP
 
+config SHAKTI
+    bool
+
+config SHAKTI_C
+    bool
+    select UNIMP
+    select SHAKTI
+    select SIFIVE_CLINT
+    select SIFIVE_PLIC
+
 config RISCV_VIRT
     bool
     imply PCI_DEVICES
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
+riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

This is the initial implementation of Shakti UART.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-4-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/shakti_uart.h |  74 ++++++++++++++
 hw/char/shakti_uart.c         | 185 ++++++++++++++++++++++++++++++++++
 MAINTAINERS                   |   2 +
 hw/char/meson.build           |   1 +
 hw/char/trace-events          |   4 +
 5 files changed, 266 insertions(+)
 create mode 100644 include/hw/char/shakti_uart.h
 create mode 100644 hw/char/shakti_uart.c

diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/char/shakti_uart.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SHAKTI UART
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_SHAKTI_UART_H
+#define HW_SHAKTI_UART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+
+#define SHAKTI_UART_BAUD        0x00
+#define SHAKTI_UART_TX          0x04
+#define SHAKTI_UART_RX          0x08
+#define SHAKTI_UART_STATUS      0x0C
+#define SHAKTI_UART_DELAY       0x10
+#define SHAKTI_UART_CONTROL     0x14
+#define SHAKTI_UART_INT_EN      0x18
+#define SHAKTI_UART_IQ_CYCLES   0x1C
+#define SHAKTI_UART_RX_THRES    0x20
+
+#define SHAKTI_UART_STATUS_TX_EMPTY     (1 << 0)
+#define SHAKTI_UART_STATUS_TX_FULL      (1 << 1)
+#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
+#define SHAKTI_UART_STATUS_RX_FULL      (1 << 3)
+/* 9600 8N1 is the default setting */
+/* Reg value = (50000000 Hz)/(16 * 9600)*/
+#define SHAKTI_UART_BAUD_DEFAULT    0x0145
+#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
+
+#define TYPE_SHAKTI_UART "shakti-uart"
+#define SHAKTI_UART(obj) \
+    OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
+
+typedef struct {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion mmio;
+
+    uint32_t uart_baud;
+    uint32_t uart_tx;
+    uint32_t uart_rx;
+    uint32_t uart_status;
+    uint32_t uart_delay;
+    uint32_t uart_control;
+    uint32_t uart_interrupt;
+    uint32_t uart_iq_cycles;
+    uint32_t uart_rx_threshold;
+
+    CharBackend chr;
+} ShaktiUartState;
+
+#endif /* HW_SHAKTI_UART_H */
diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/char/shakti_uart.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SHAKTI UART
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/shakti_uart.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "qemu/log.h"
+
+static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
+{
+    ShaktiUartState *s = opaque;
+
+    switch (addr) {
+    case SHAKTI_UART_BAUD:
+        return s->uart_baud;
+    case SHAKTI_UART_RX:
+        qemu_chr_fe_accept_input(&s->chr);
+        s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
+        return s->uart_rx;
+    case SHAKTI_UART_STATUS:
+        return s->uart_status;
+    case SHAKTI_UART_DELAY:
+        return s->uart_delay;
+    case SHAKTI_UART_CONTROL:
+        return s->uart_control;
+    case SHAKTI_UART_INT_EN:
+        return s->uart_interrupt;
+    case SHAKTI_UART_IQ_CYCLES:
+        return s->uart_iq_cycles;
+    case SHAKTI_UART_RX_THRES:
+        return s->uart_rx_threshold;
+    default:
+        /* Also handles TX REG which is write only */
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+
+    return 0;
+}
+
+static void shakti_uart_write(void *opaque, hwaddr addr,
+                              uint64_t data, unsigned size)
+{
+    ShaktiUartState *s = opaque;
+    uint32_t value = data;
+    uint8_t ch;
+
+    switch (addr) {
+    case SHAKTI_UART_BAUD:
+        s->uart_baud = value;
+        break;
+    case SHAKTI_UART_TX:
+        ch = value;
+        qemu_chr_fe_write_all(&s->chr, &ch, 1);
+        s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
+        break;
+    case SHAKTI_UART_STATUS:
+        s->uart_status = value;
+        break;
+    case SHAKTI_UART_DELAY:
+        s->uart_delay = value;
+        break;
+    case SHAKTI_UART_CONTROL:
+        s->uart_control = value;
+        break;
+    case SHAKTI_UART_INT_EN:
+        s->uart_interrupt = value;
+        break;
+    case SHAKTI_UART_IQ_CYCLES:
+        s->uart_iq_cycles = value;
+        break;
+    case SHAKTI_UART_RX_THRES:
+        s->uart_rx_threshold = value;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+}
+
+static const MemoryRegionOps shakti_uart_ops = {
+    .read = shakti_uart_read,
+    .write = shakti_uart_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {.min_access_size = 1, .max_access_size = 4},
+    .valid = {.min_access_size = 1, .max_access_size = 4},
+};
+
+static void shakti_uart_reset(DeviceState *dev)
+{
+    ShaktiUartState *s = SHAKTI_UART(dev);
+
+    s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
+    s->uart_tx = 0x0;
+    s->uart_rx = 0x0;
+    s->uart_status = 0x0000;
+    s->uart_delay = 0x0000;
+    s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
+    s->uart_interrupt = 0x0000;
+    s->uart_iq_cycles = 0x00;
+    s->uart_rx_threshold = 0x00;
+}
+
+static int shakti_uart_can_receive(void *opaque)
+{
+    ShaktiUartState *s = opaque;
+
+    return !(s->uart_status & SHAKTI_UART_STATUS_RX_NOT_EMPTY);
+}
+
+static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
+{
+    ShaktiUartState *s = opaque;
+
+    s->uart_rx = *buf;
+    s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
+}
+
+static void shakti_uart_realize(DeviceState *dev, Error **errp)
+{
+    ShaktiUartState *sus = SHAKTI_UART(dev);
+    qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
+                             shakti_uart_receive, NULL, NULL, sus, NULL, true);
+}
+
+static void shakti_uart_instance_init(Object *obj)
+{
+    ShaktiUartState *sus = SHAKTI_UART(obj);
+    memory_region_init_io(&sus->mmio,
+                          obj,
+                          &shakti_uart_ops,
+                          sus,
+                          TYPE_SHAKTI_UART,
+                          0x1000);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
+}
+
+static Property shakti_uart_properties[] = {
+    DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void shakti_uart_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    dc->reset = shakti_uart_reset;
+    dc->realize = shakti_uart_realize;
+    device_class_set_props(dc, shakti_uart_properties);
+}
+
+static const TypeInfo shakti_uart_info = {
+    .name = TYPE_SHAKTI_UART,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(ShaktiUartState),
+    .class_init = shakti_uart_class_init,
+    .instance_init = shakti_uart_instance_init,
+};
+
+static void shakti_uart_register_types(void)
+{
+    type_register_static(&shakti_uart_info);
+}
+type_init(shakti_uart_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Vijai Kumar K <vijai@behindbytes.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: hw/riscv/shakti_c.c
+F: hw/char/shakti_uart.c
 F: include/hw/riscv/shakti_c.h
+F: include/hw/char/shakti_uart.h
 
 SiFive Machines
 M: Alistair Francis <Alistair.Francis@wdc.com>
diff --git a/hw/char/meson.build b/hw/char/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
 softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
 softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
 softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
+softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
 softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
 softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
 softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
diff --git a/hw/char/trace-events b/hw/char/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
 nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
 nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
 
+# shakti_uart.c
+shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
+shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+
 # exynos4210_uart.c
 exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
 exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

Connect one shakti uart to the shakti_c machine.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/shakti_c.h | 2 ++
 hw/riscv/shakti_c.c         | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/shakti_c.h
+++ b/include/hw/riscv/shakti_c.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/riscv/riscv_hart.h"
 #include "hw/boards.h"
+#include "hw/char/shakti_uart.h"
 
 #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
 #define RISCV_SHAKTI_SOC(obj) \
@@ -XXX,XX +XXX,XX @@ typedef struct ShaktiCSoCState {
     /*< public >*/
     RISCVHartArrayState cpus;
     DeviceState *plic;
+    ShaktiUartState uart;
     MemoryRegion rom;
 
 } ShaktiCSoCState;
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
         SIFIVE_CLINT_TIMEBASE_FREQ, false);
 
+    qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
+    if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
+                    shakti_c_memmap[SHAKTI_C_UART].base);
+
     /* ROM */
     memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
                            shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_instance_init(Object *obj)
     ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
 
     object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+    object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
 
     /*
      * CPU type is fixed and we are not supporting passing from commandline yet.
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h   | 44 ++++++++++++++++++++-------------------
 target/riscv/cpu.c        |  2 +-
 target/riscv/cpu_helper.c |  4 ++--
 3 files changed, 26 insertions(+), 24 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define DEFAULT_RSTVEC      0x1000
 
 /* Exception causes */
-#define EXCP_NONE                                -1 /* sentinel value */
-#define RISCV_EXCP_INST_ADDR_MIS                 0x0
-#define RISCV_EXCP_INST_ACCESS_FAULT             0x1
-#define RISCV_EXCP_ILLEGAL_INST                  0x2
-#define RISCV_EXCP_BREAKPOINT                    0x3
-#define RISCV_EXCP_LOAD_ADDR_MIS                 0x4
-#define RISCV_EXCP_LOAD_ACCESS_FAULT             0x5
-#define RISCV_EXCP_STORE_AMO_ADDR_MIS            0x6
-#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT        0x7
-#define RISCV_EXCP_U_ECALL                       0x8
-#define RISCV_EXCP_S_ECALL                      0x9
-#define RISCV_EXCP_VS_ECALL                      0xa
-#define RISCV_EXCP_M_ECALL                       0xb
-#define RISCV_EXCP_INST_PAGE_FAULT               0xc /* since: priv-1.10.0 */
-#define RISCV_EXCP_LOAD_PAGE_FAULT               0xd /* since: priv-1.10.0 */
-#define RISCV_EXCP_STORE_PAGE_FAULT              0xf /* since: priv-1.10.0 */
-#define RISCV_EXCP_SEMIHOST                      0x10
-#define RISCV_EXCP_INST_GUEST_PAGE_FAULT         0x14
-#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT       0x15
-#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT        0x16
-#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT  0x17
+typedef enum RISCVException {
+    RISCV_EXCP_NONE = -1, /* sentinel value */
+    RISCV_EXCP_INST_ADDR_MIS = 0x0,
+    RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
+    RISCV_EXCP_ILLEGAL_INST = 0x2,
+    RISCV_EXCP_BREAKPOINT = 0x3,
+    RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
+    RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
+    RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
+    RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
+    RISCV_EXCP_U_ECALL = 0x8,
+    RISCV_EXCP_S_ECALL = 0x9,
+    RISCV_EXCP_VS_ECALL = 0xa,
+    RISCV_EXCP_M_ECALL = 0xb,
+    RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
+    RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
+    RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
+    RISCV_EXCP_SEMIHOST = 0x10,
+    RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
+    RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
+    RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
+    RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+} RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
 #define RISCV_EXCP_INT_MASK                0x7fffffff
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->pc = env->resetvec;
     env->two_stage_lookup = false;
 #endif
-    cs->exception_index = EXCP_NONE;
+    cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
 }
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
     if (irqs) {
         return ctz64(irqs); /* since non-zero */
     } else {
-        return EXCP_NONE; /* indicates no pending interrupt */
+        return RISCV_EXCP_NONE; /* indicates no pending interrupt */
     }
 }
 #endif
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
 
     env->two_stage_lookup = false;
 #endif
-    cs->exception_index = EXCP_NONE; /* mark handled to qemu */
+    cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com
---
 target/riscv/cpu.h |  3 +-
 target/riscv/csr.c | 80 +++++++++++++++++++++++++---------------------
 2 files changed, 46 insertions(+), 37 deletions(-)

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
---
 target/riscv/cpu.h |  14 +-
 target/riscv/csr.c | 629 +++++++++++++++++++++++++++------------------
 2 files changed, 382 insertions(+), 261 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 
 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
                                                  int csrno);
-typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
-    target_ulong *ret_value);
-typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
-    target_ulong new_value);
-typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
-    target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
+typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
+                                            target_ulong *ret_value);
+typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
+                                             target_ulong new_value);
+typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+                                          target_ulong *ret_value,
+                                          target_ulong new_value,
+                                          target_ulong write_mask);
 
 typedef struct {
     const char *name;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
 #endif
 
 /* User Floating-Point CSRs */
-static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_fflags(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     *val = riscv_cpu_get_fflags(env);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_fflags(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     env->mstatus |= MSTATUS_FS;
 #endif
     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_frm(CPURISCVState *env, int csrno,
+                               target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     *val = env->frm;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_frm(CPURISCVState *env, int csrno,
+                                target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     env->mstatus |= MSTATUS_FS;
 #endif
     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_fcsr(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
@@ -XXX,XX +XXX,XX @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
         *val |= (env->vxrm << FSR_VXRM_SHIFT)
                 | (env->vxsat << FSR_VXSAT_SHIFT);
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_fcsr(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     env->mstatus |= MSTATUS_FS;
 #endif
@@ -XXX,XX +XXX,XX @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
         env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
     }
     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vtype(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->vtype;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vl(CPURISCVState *env, int csrno,
+                              target_ulong *val)
 {
     *val = env->vl;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vxrm(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     *val = env->vxrm;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vxrm(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     env->vxrm = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vxsat(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->vxsat;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vxsat(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->vxsat = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vstart(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->vstart;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vstart(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->vstart = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* User Timers and Counters */
-static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_instret(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (icount_enabled()) {
@@ -XXX,XX +XXX,XX @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
 #else
     *val = cpu_get_host_ticks();
 #endif
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_instreth(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (icount_enabled()) {
@@ -XXX,XX +XXX,XX @@ static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
 #else
     *val = cpu_get_host_ticks() >> 32;
 #endif
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 #if defined(CONFIG_USER_ONLY)
-static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_time(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     *val = cpu_get_host_ticks();
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_timeh(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = cpu_get_host_ticks() >> 32;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 #else /* CONFIG_USER_ONLY */
 
-static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_time(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_timeh(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Machine constants */
@@ -XXX,XX +XXX,XX @@ static const char valid_vm_1_10_64[16] = {
 };
 
 /* Machine Information Registers */
-static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_zero(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
-    return *val = 0;
+    *val = 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mhartid(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->mhartid;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Machine Trap Setup */
-static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mstatus(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->mstatus;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 static int validate_vm(CPURISCVState *env, target_ulong vm)
@@ -XXX,XX +XXX,XX @@ static int validate_vm(CPURISCVState *env, target_ulong vm)
     }
 }
 
-static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mstatus(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     uint64_t mstatus = env->mstatus;
     uint64_t mask = 0;
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
     env->mstatus = mstatus;
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mstatush(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
     *val = env->mstatus >> 32;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mstatush(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     uint64_t valh = (uint64_t)val << 32;
     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
@@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
 
     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_misa(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     *val = env->misa;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_misa(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
         /* drop write to misa */
-        return 0;
+        return RISCV_EXCP_NONE;
     }
 
     /* 'I' or 'E' must be present */
     if (!(val & (RVI | RVE))) {
         /* It is not, drop write to misa */
-        return 0;
+        return RISCV_EXCP_NONE;
     }
 
     /* 'E' excludes all other extensions */
@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
         /* when we support 'E' we can do "val = RVE;" however
          * for now we just drop writes if 'E' is present.
          */
-        return 0;
+        return RISCV_EXCP_NONE;
     }
 
     /* Mask extensions that are not supported by this hart */
@@ -XXX,XX +XXX,XX @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
 
     env->misa = val;
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_medeleg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->medeleg;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_medeleg(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mideleg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->mideleg;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mideleg(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
     if (riscv_has_ext(env, RVH)) {
         env->mideleg |= VS_MODE_INTERRUPTS;
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mie(CPURISCVState *env, int csrno,
+                               target_ulong *val)
 {
     *val = env->mie;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mie(CPURISCVState *env, int csrno,
+                                target_ulong val)
 {
     env->mie = (env->mie & ~all_ints) | (val & all_ints);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mtvec(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->mtvec;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mtvec(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
     if ((val & 3) < 2) {
@@ -XXX,XX +XXX,XX @@ static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
     } else {
         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
 {
     *val = env->mcounteren;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
+                                       target_ulong val)
 {
     env->mcounteren = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Machine Trap Handling */
-static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mscratch(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
     *val = env->mscratch;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mscratch(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     env->mscratch = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mepc(CPURISCVState *env, int csrno,
+                                     target_ulong *val)
 {
     *val = env->mepc;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mepc(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     env->mepc = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mcause(CPURISCVState *env, int csrno,
+                                     target_ulong *val)
 {
     *val = env->mcause;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mcause(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     env->mcause = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mtval(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->mtval;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mtval(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->mtval = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                   target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_mip(CPURISCVState *env, int csrno,
+                              target_ulong *ret_value,
+                              target_ulong new_value, target_ulong write_mask)
 {
     RISCVCPU *cpu = env_archcpu(env);
     /* Allow software control of delegable interrupts not claimed by hardware */
@@ -XXX,XX +XXX,XX @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
         *ret_value = old_mip;
     }
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Supervisor Trap Setup */
-static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_sstatus(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
     *val = env->mstatus & mask;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_sstatus(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
     return write_mstatus(env, CSR_MSTATUS, newval);
 }
 
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsie(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     /* Shift the VS bits to their S bit location in vsie */
     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_sie(CPURISCVState *env, int csrno,
+                               target_ulong *val)
 {
     if (riscv_cpu_virt_enabled(env)) {
         read_vsie(env, CSR_VSIE, val);
     } else {
         *val = env->mie & env->mideleg;
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsie(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     /* Shift the S bits to their VS bit location in mie */
     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
@@ -XXX,XX +XXX,XX @@ static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
         write_mie(env, CSR_MIE, newval);
     }
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_stvec(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->stvec;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_stvec(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
     if ((val & 3) < 2) {
@@ -XXX,XX +XXX,XX @@ static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
     } else {
         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_scounteren(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
 {
     *val = env->scounteren;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_scounteren(CPURISCVState *env, int csrno,
+                                       target_ulong val)
 {
     env->scounteren = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Supervisor Trap Handling */
-static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_sscratch(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
     *val = env->sscratch;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_sscratch(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     env->sscratch = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_sepc(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     *val = env->sepc;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_sepc(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     env->sepc = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_scause(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->scause;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_scause(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->scause = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_stval(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->stval;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_stval(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->stval = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                    target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value, target_ulong write_mask)
 {
     /* Shift the S bits to their VS bit location in mip */
     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
@@ -XXX,XX +XXX,XX @@ static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
     return ret;
 }
 
-static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                   target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_sip(CPURISCVState *env, int csrno,
+                              target_ulong *ret_value,
+                              target_ulong new_value, target_ulong write_mask)
 {
     int ret;
 
@@ -XXX,XX +XXX,XX @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 }
 
 /* Supervisor Protection and Translation */
-static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_satp(CPURISCVState *env, int csrno,
+                                target_ulong *val)
 {
     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
         *val = 0;
-        return 0;
+        return RISCV_EXCP_NONE;
     }
 
     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     } else {
         *val = env->satp;
     }
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_satp(CPURISCVState *env, int csrno,
+                                 target_ulong val)
 {
     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
-        return 0;
+        return RISCV_EXCP_NONE;
     }
     if (validate_vm(env, get_field(val, SATP_MODE)) &&
         ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
     {
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
-            return -RISCV_EXCP_ILLEGAL_INST;
+            return RISCV_EXCP_ILLEGAL_INST;
         } else {
             if ((val ^ env->satp) & SATP_ASID) {
                 tlb_flush(env_cpu(env));
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
             env->satp = val;
         }
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Hypervisor Extensions */
-static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hstatus(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->hstatus;
     if (!riscv_cpu_is_32bit(env)) {
@@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
     }
     /* We only support little endian */
     *val = set_field(*val, HSTATUS_VSBE, 0);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hstatus(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->hstatus = val;
     if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
@@ -XXX,XX +XXX,XX @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
     if (get_field(val, HSTATUS_VSBE) != 0) {
         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->hedeleg;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->hedeleg = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hideleg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->hideleg;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hideleg(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->hideleg = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                   target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hvip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
     return ret;
 }
 
-static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                   target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_hip(CPURISCVState *env, int csrno,
+                              target_ulong *ret_value,
+                              target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hip_writable_mask);
@@ -XXX,XX +XXX,XX @@ static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
     return ret;
 }
 
-static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hie(CPURISCVState *env, int csrno,
+                               target_ulong *val)
 {
     *val = env->mie & VS_MODE_INTERRUPTS;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hie(CPURISCVState *env, int csrno,
+                                target_ulong val)
 {
     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
     return write_mie(env, CSR_MIE, newval);
 }
 
-static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
 {
     *val = env->hcounteren;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
+                                       target_ulong val)
 {
     env->hcounteren = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hgeie(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hgeie(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_htval(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->htval;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_htval(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->htval = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_htinst(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->htinst;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_htinst(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hgeip(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hgeip(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_hgatp(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->hgatp;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_hgatp(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->hgatp = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
 {
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = env->htimedelta;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
+                                       target_ulong val)
 {
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     if (riscv_cpu_is_32bit(env)) {
@@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
     } else {
         env->htimedelta = val;
     }
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
 {
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = env->htimedelta >> 32;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
+                                        target_ulong val)
 {
     if (!env->rdtime_fn) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Virtual CSR Registers */
-static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
 {
     *val = env->vsstatus;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
+                                     target_ulong val)
 {
     uint64_t mask = (target_ulong)-1;
     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->vstvec;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vstvec(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->vstvec = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
+                                     target_ulong *val)
 {
     *val = env->vsscratch;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
+                                      target_ulong val)
 {
     env->vsscratch = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsepc(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->vsepc;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsepc(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->vsepc = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vscause(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = env->vscause;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vscause(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     env->vscause = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vstval(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->vstval;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vstval(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->vstval = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_vsatp(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
 {
     *val = env->vsatp;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_vsatp(CPURISCVState *env, int csrno,
+                                  target_ulong val)
 {
     env->vsatp = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mtval2(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->mtval2;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mtval2(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->mtval2 = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_mtinst(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = env->mtinst;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_mtinst(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     env->mtinst = val;
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /* Physical Memory Protection */
-static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
+                                  target_ulong *val)
 {
     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
+                                   target_ulong val)
 {
     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
+static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
 {
     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
-static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
+                                    target_ulong val)
 {
     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 #endif
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 
     /* execute combined read/write operation if it exists */
     if (csr_ops[csrno].op) {
-        return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
+        ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
+        if (ret != RISCV_EXCP_NONE) {
+            return -ret;
+        }
+        return 0;
     }
 
     /* if no accessor exists then return failure */
     if (!csr_ops[csrno].read) {
         return -RISCV_EXCP_ILLEGAL_INST;
     }
-
     /* read old value */
     ret = csr_ops[csrno].read(env, csrno, &old_value);
-    if (ret < 0) {
-        return ret;
+    if (ret != RISCV_EXCP_NONE) {
+        return -ret;
     }
 
     /* write value if writable and write mask set, otherwise drop writes */
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
         new_value = (old_value & ~write_mask) | (new_value & write_mask);
         if (csr_ops[csrno].write) {
             ret = csr_ops[csrno].write(env, csrno, new_value);
-            if (ret < 0) {
-                return ret;
+            if (ret != RISCV_EXCP_NONE) {
+                return -ret;
             }
         }
     }
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
---
 target/riscv/cpu.h       | 11 +++++++----
 target/riscv/csr.c       | 37 ++++++++++++++++++-------------------
 target/riscv/gdbstub.c   |  8 ++++----
 target/riscv/op_helper.c | 18 +++++++++---------
 4 files changed, 38 insertions(+), 36 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     *pflags = flags;
 }
 
-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                target_ulong new_value, target_ulong write_mask);
-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                      target_ulong new_value, target_ulong write_mask);
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value,
+                           target_ulong new_value, target_ulong write_mask);
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
+                                 target_ulong *ret_value,
+                                 target_ulong new_value,
+                                 target_ulong write_mask);
 
 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
                                    target_ulong val)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
  */
 
-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                target_ulong new_value, target_ulong write_mask)
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value,
+                           target_ulong new_value, target_ulong write_mask)
 {
-    int ret;
+    RISCVException ret;
     target_ulong old_value;
     RISCVCPU *cpu = env_archcpu(env);
 
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 
     if ((write_mask && read_only) ||
         (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
 
     /* ensure the CSR extension is enabled. */
     if (!cpu->cfg.ext_icsr) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
 
     /* check predicate */
     if (!csr_ops[csrno].predicate) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     ret = csr_ops[csrno].predicate(env, csrno);
     if (ret != RISCV_EXCP_NONE) {
-        return -ret;
+        return ret;
     }
 
     /* execute combined read/write operation if it exists */
     if (csr_ops[csrno].op) {
-        ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
-        if (ret != RISCV_EXCP_NONE) {
-            return -ret;
-        }
-        return 0;
+        return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
     }
 
     /* if no accessor exists then return failure */
     if (!csr_ops[csrno].read) {
-        return -RISCV_EXCP_ILLEGAL_INST;
+        return RISCV_EXCP_ILLEGAL_INST;
     }
     /* read old value */
     ret = csr_ops[csrno].read(env, csrno, &old_value);
     if (ret != RISCV_EXCP_NONE) {
-        return -ret;
+        return ret;
     }
 
     /* write value if writable and write mask set, otherwise drop writes */
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
         if (csr_ops[csrno].write) {
             ret = csr_ops[csrno].write(env, csrno, new_value);
             if (ret != RISCV_EXCP_NONE) {
-                return -ret;
+                return ret;
             }
         }
     }
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
         *ret_value = old_value;
     }
 
-    return 0;
+    return RISCV_EXCP_NONE;
 }
 
 /*
  * Debugger support.  If not in user mode, set env->debugger before the
  * riscv_csrrw call and clear it after the call.
  */
-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
-                target_ulong new_value, target_ulong write_mask)
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
+                                 target_ulong *ret_value,
+                                 target_ulong new_value,
+                                 target_ulong write_mask)
 {
-    int ret;
+    RISCVException ret;
 #if !defined(CONFIG_USER_ONLY)
     env->debugger = true;
 #endif
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
          */
         result = riscv_csrrw_debug(env, n - 32, &val,
                                    0, 0);
-        if (result == 0) {
+        if (result == RISCV_EXCP_NONE) {
             return gdb_get_regl(buf, val);
         }
     }
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
          */
         result = riscv_csrrw_debug(env, n - 32, NULL,
                                    val, -1);
-        if (result == 0) {
+        if (result == RISCV_EXCP_NONE) {
             return sizeof(target_ulong);
         }
     }
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
         int result;
 
         result = riscv_csrrw_debug(env, n, &val, 0, 0);
-        if (result == 0) {
+        if (result == RISCV_EXCP_NONE) {
             return gdb_get_regl(buf, val);
         }
     }
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
         int result;
 
         result = riscv_csrrw_debug(env, n, NULL, val, -1);
-        if (result == 0) {
+        if (result == RISCV_EXCP_NONE) {
             return sizeof(target_ulong);
         }
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
         target_ulong csr)
 {
     target_ulong val = 0;
-    int ret = riscv_csrrw(env, csr, &val, src, -1);
+    RISCVException ret = riscv_csrrw(env, csr, &val, src, -1);
 
-    if (ret < 0) {
-        riscv_raise_exception(env, -ret, GETPC());
+    if (ret != RISCV_EXCP_NONE) {
+        riscv_raise_exception(env, ret, GETPC());
     }
     return val;
 }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
         target_ulong csr, target_ulong rs1_pass)
 {
     target_ulong val = 0;
-    int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+    RISCVException ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
 
-    if (ret < 0) {
-        riscv_raise_exception(env, -ret, GETPC());
+    if (ret != RISCV_EXCP_NONE) {
+        riscv_raise_exception(env, ret, GETPC());
     }
     return val;
 }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
         target_ulong csr, target_ulong rs1_pass)
 {
     target_ulong val = 0;
-    int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+    RISCVException ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
 
-    if (ret < 0) {
-        riscv_raise_exception(env, -ret, GETPC());
+    if (ret != RISCV_EXCP_NONE) {
+        riscv_raise_exception(env, ret, GETPC());
     }
     return val;
 }
-- 
2.31.1

Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.

Also add Bin who has been helping with reviews.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
---
 MAINTAINERS | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: tests/acceptance/machine_ppc.py
 
 RISC-V TCG CPUs
 M: Palmer Dabbelt <palmer@dabbelt.com>
-M: Alistair Francis <Alistair.Francis@wdc.com>
-M: Sagar Karandikar <sagark@eecs.berkeley.edu>
-M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+M: Alistair Francis <alistair.francis@wdc.com>
+M: Bin Meng <bin.meng@windriver.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/
-- 
2.31.1

Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
---
 include/hw/riscv/opentitan.h | 16 ++++++++--------
 hw/intc/ibex_plic.c          | 20 ++++++++++----------
 hw/riscv/opentitan.c         |  8 ++++----
 3 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 enum {
-    IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
-    IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
-    IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
-    IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
-    IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
-    IBEX_UART_TX_EMPTY_IRQ = 0x23,
-    IBEX_UART_RX_WATERMARK_IRQ = 0x22,
-    IBEX_UART_TX_WATERMARK_IRQ = 0x21,
+    IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
+    IBEX_UART0_RX_TIMEOUT_IRQ = 7,
+    IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
+    IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
+    IBEX_UART0_RX_OVERFLOW_IRQ = 4,
+    IBEX_UART0_TX_EMPTY_IRQ = 3,
+    IBEX_UART0_RX_WATERMARK_IRQ = 2,
+    IBEX_UART0_TX_WATERMARK_IRQ = 1,
 };
 
 #endif
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -XXX,XX +XXX,XX @@ static void ibex_plic_irq_request(void *opaque, int irq, int level)
 
 static Property ibex_plic_properties[] = {
     DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
-    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
+    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
 
     DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
-    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
+    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
 
-    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
-    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
+    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
+    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
 
-    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
-    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
+    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
+    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
 
-    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
-    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
+    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
+    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
 
-    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
+    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
 
-    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
+    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        0, qdev_get_gpio_in(DEVICE(&s->plic),
-                       IBEX_UART_TX_WATERMARK_IRQ));
+                       IBEX_UART0_TX_WATERMARK_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        1, qdev_get_gpio_in(DEVICE(&s->plic),
-                       IBEX_UART_RX_WATERMARK_IRQ));
+                       IBEX_UART0_RX_WATERMARK_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        2, qdev_get_gpio_in(DEVICE(&s->plic),
-                       IBEX_UART_TX_EMPTY_IRQ));
+                       IBEX_UART0_TX_EMPTY_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        3, qdev_get_gpio_in(DEVICE(&s->plic),
-                       IBEX_UART_RX_OVERFLOW_IRQ));
+                       IBEX_UART0_RX_OVERFLOW_IRQ));
 
     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
-- 
2.31.1

From: Jade Fink <qemu@jade.fyi>

Previously the qemu monitor and gdbstub looked at SUM and refused to
perform accesses to user memory if it is off, which was an impediment to
debugging.

Signed-off-by: Jade Fink <qemu@jade.fyi>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210406113109.1031033-1-qemu@jade.fyi
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
  * @first_stage: Are we in first stage translation?
  *               Second stage is used for hypervisor guest translation
  * @two_stage: Are we going to perform two stage translation
+ * @is_debug: Is this access from a debugger or the monitor?
  */
 static int get_physical_address(CPURISCVState *env, hwaddr *physical,
                                 int *prot, target_ulong addr,
                                 target_ulong *fault_pte_addr,
                                 int access_type, int mmu_idx,
-                                bool first_stage, bool two_stage)
+                                bool first_stage, bool two_stage,
+                                bool is_debug)
 {
     /* NOTE: the env->pc value visible here will not be
      * correct, but the value visible to the exception handler
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         widened = 2;
     }
     /* status.SUM will be ignored if execute on background */
-    sum = get_field(env->mstatus, MSTATUS_SUM) || use_background;
+    sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
     switch (vm) {
     case VM_1_10_SV32:
       levels = 2; ptidxbits = 10; ptesize = 4; break;
@@ -XXX,XX +XXX,XX @@ restart:
             /* Do the second stage translation on the base PTE address. */
             int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
                                                  base, NULL, MMU_DATA_LOAD,
-                                                 mmu_idx, false, true);
+                                                 mmu_idx, false, true,
+                                                 is_debug);
 
             if (vbase_ret != TRANSLATE_SUCCESS) {
                 if (fault_pte_addr) {
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     int mmu_idx = cpu_mmu_index(&cpu->env, false);
 
     if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
-                             true, riscv_cpu_virt_enabled(env))) {
+                             true, riscv_cpu_virt_enabled(env), true)) {
         return -1;
     }
 
     if (riscv_cpu_virt_enabled(env)) {
         if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
-                                 0, mmu_idx, false, true)) {
+                                 0, mmu_idx, false, true, true)) {
             return -1;
         }
     }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         /* Two stage lookup */
         ret = get_physical_address(env, &pa, &prot, address,
                                    &env->guest_phys_fault_addr, access_type,
-                                   mmu_idx, true, true);
+                                   mmu_idx, true, true, false);
 
         /*
          * A G-stage exception may be triggered during two state lookup.
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             im_address = pa;
 
             ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
-                                       access_type, mmu_idx, false, true);
+                                       access_type, mmu_idx, false, true,
+                                       false);
 
             qemu_log_mask(CPU_LOG_MMU,
                     "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     } else {
         /* Single stage lookup */
         ret = get_physical_address(env, &pa, &prot, address, NULL,
-                                   access_type, mmu_idx, true, false);
+                                   access_type, mmu_idx, true, false, false);
 
         qemu_log_mask(CPU_LOG_MMU,
                       "%s address=%" VADDR_PRIx " ret %d physical "
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
However, when the predication is ture and a is 0, it should return maximum.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
 {
     int8_t res = a - b;
     if ((res ^ a) & (a ^ b) & INT8_MIN) {
-        res = a > 0 ? INT8_MAX : INT8_MIN;
+        res = a >= 0 ? INT8_MAX : INT8_MIN;
         env->vxsat = 0x1;
     }
     return res;
@@ -XXX,XX +XXX,XX @@ static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
 {
     int16_t res = a - b;
     if ((res ^ a) & (a ^ b) & INT16_MIN) {
-        res = a > 0 ? INT16_MAX : INT16_MIN;
+        res = a >= 0 ? INT16_MAX : INT16_MIN;
         env->vxsat = 0x1;
     }
     return res;
@@ -XXX,XX +XXX,XX @@ static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
 {
     int32_t res = a - b;
     if ((res ^ a) & (a ^ b) & INT32_MIN) {
-        res = a > 0 ? INT32_MAX : INT32_MIN;
+        res = a >= 0 ? INT32_MAX : INT32_MIN;
         env->vxsat = 0x1;
     }
     return res;
@@ -XXX,XX +XXX,XX @@ static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
 {
     int64_t res = a - b;
     if ((res ^ a) & (a ^ b) & INT64_MIN) {
-        res = a > 0 ? INT64_MAX : INT64_MIN;
+        res = a >= 0 ? INT64_MAX : INT64_MIN;
         env->vxsat = 0x1;
     }
     return res;
-- 
2.31.1

From: Vijai Kumar K <vijai@behindbytes.com>

Add documentation for Shakti C reference platform.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210412174248.8668-1-vijai@behindbytes.com
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
[ Changes from Bin Meng:
 - Add missing TOC
 Message-id: 20210430070534.1487242-1-bmeng.cn@gmail.com
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/shakti-c.rst | 82 ++++++++++++++++++++++++++++++++++
 docs/system/target-riscv.rst   |  1 +
 2 files changed, 83 insertions(+)
 create mode 100644 docs/system/riscv/shakti-c.rst

diff --git a/docs/system/riscv/shakti-c.rst b/docs/system/riscv/shakti-c.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/shakti-c.rst
@@ -XXX,XX +XXX,XX @@
+Shakti C Reference Platform (``shakti_c``)
+==========================================
+
+Shakti C Reference Platform is a reference platform based on arty a7 100t
+for the Shakti SoC.
+
+Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
+is a 64bit RV64GCSUN processor core.
+
+For more details on Shakti SoC, please see:
+https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/README.rst
+
+For more info on the Shakti C-class core, please see:
+https://c-class.readthedocs.io/en/latest/
+
+Supported devices
+-----------------
+
+The ``shakti_c`` machine supports the following devices:
+
+ * 1 C-class core
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * 1 UART
+
+Boot options
+------------
+
+The ``shakti_c`` machine can start using the standard -bios
+functionality for loading the baremetal application or opensbi.
+
+Boot the machine
+----------------
+
+Shakti SDK
+~~~~~~~~~~
+Shakti SDK can be used to generate the baremetal example UART applications.
+
+.. code-block:: bash
+
+   $ git clone https://gitlab.com/behindbytes/shakti-sdk.git
+   $ cd shakti-sdk
+   $ make software PROGRAM=loopback TARGET=artix7_100t
+
+Binary would be generated in:
+  software/examples/uart_applns/loopback/output/loopback.shakti
+
+You could also download the precompiled example applicatons using below
+commands.
+
+.. code-block:: bash
+
+   $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/sdk/shakti_sdk_qemu.zip
+   $ unzip shakti_sdk_qemu.zip
+
+Then we can run the UART example using:
+
+.. code-block:: bash
+
+   $ qemu-system-riscv64 -M shakti_c -nographic \
+      -bios path/to/shakti_sdk_qemu/loopback.shakti
+
+OpenSBI
+~~~~~~~
+We can also run OpenSBI with Test Payload.
+
+.. code-block:: bash
+
+   $ git clone https://github.com/riscv/opensbi.git -b v0.9
+   $ cd opensbi
+   $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/dts/shakti.dtb
+   $ export CROSS_COMPILE=riscv64-unknown-elf-
+   $ export FW_FDT_PATH=./shakti.dtb
+   $ make PLATFORM=generic
+
+fw_payload.elf would be generated in build/platform/generic/firmware/fw_payload.elf.
+Boot it using the below qemu command.
+
+.. code-block:: bash
+
+   $ qemu-system-riscv64 -M shakti_c -nographic \
+      -bios path/to/fw_payload.elf
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    :maxdepth: 1
 
    riscv/microchip-icicle-kit
+   riscv/shakti-c
    riscv/sifive_u
 
 RISC-V CPU features
-- 
2.31.1

The RISC-V spec says:
    if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
    pmpaddri-1 are ignored.

The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.

Update the pmp_is_locked() function to not check the supporting fields
and instead enforce the lock functionality in the pmpaddr write operation.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com
---
 target/riscv/pmp.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
         return 0;
     }
 
-    /* In TOR mode, need to check the lock bit of the next pmp
-     * (if there is a next)
-     */
-    const uint8_t a_field =
-        pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
-    if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
-         (PMP_AMATCH_TOR == a_field)) {
-        return 1;
-    }
-
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val)
 {
     trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
+
     if (addr_index < MAX_RISCV_PMPS) {
+        /*
+         * In TOR mode, need to check the lock bit of the next pmp
+         * (if there is a next).
+         */
+        if (addr_index + 1 < MAX_RISCV_PMPS) {
+            uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
+
+            if (pmp_cfg & PMP_LOCK &&
+                PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg)) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "ignoring pmpaddr write - pmpcfg + 1 locked\n");
+                return;
+            }
+        }
+
         if (!pmp_is_locked(env, addr_index)) {
             env->pmp_state.pmp[addr_index].addr_reg = val;
             pmp_update_rule(env, addr_index);
-- 
2.31.1

From: Hou Weiying <weiying_hou@outlook.com>

Use address 0x390 and 0x391 for the ePMP CSRs.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 target/riscv/cpu_bits.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define CSR_MTINST          0x34a
 #define CSR_MTVAL2          0x34b
 
+/* Enhanced Physical Memory Protection (ePMP) */
+#define CSR_MSECCFG         0x390
+#define CSR_MSECCFGH        0x391
 /* Physical Memory Protection */
 #define CSR_PMPCFG0         0x3a0
 #define CSR_PMPCFG1         0x3a1
-- 
2.31.1

From: Hou Weiying <weiying_hou@outlook.com>

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Rebase on master
 - Fix build errors
 - Fix some style issues
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 target/riscv/cpu.h        |  1 +
 target/riscv/pmp.h        | 14 ++++++++++++++
 target/riscv/csr.c        | 24 ++++++++++++++++++++++++
 target/riscv/pmp.c        | 34 ++++++++++++++++++++++++++++++++++
 target/riscv/trace-events |  3 +++
 5 files changed, 76 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
 
     /* physical memory protection */
     pmp_table_t pmp_state;
+    target_ulong mseccfg;
 
     /* machine specific rdtime callback */
     uint64_t (*rdtime_fn)(uint32_t);
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
     PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
 } pmp_am_t;
 
+typedef enum {
+    MSECCFG_MML  = 1 << 0,
+    MSECCFG_MMWP = 1 << 1,
+    MSECCFG_RLB  = 1 << 2
+} mseccfg_field_t;
+
 typedef struct {
     target_ulong addr_reg;
     uint8_t  cfg_reg;
@@ -XXX,XX +XXX,XX @@ typedef struct {
 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
     target_ulong val);
 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
+
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
+target_ulong mseccfg_csr_read(CPURISCVState *env);
+
 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
@@ -XXX,XX +XXX,XX @@ void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
 int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
 
+#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
+#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
+#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
+
 #endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException pmp(CPURISCVState *env, int csrno)
 
     return RISCV_EXCP_ILLEGAL_INST;
 }
+
+static RISCVException epmp(CPURISCVState *env, int csrno)
+{
+    if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
 #endif
 
 /* User Floating-Point CSRs */
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtinst(CPURISCVState *env, int csrno,
 }
 
 /* Physical Memory Protection */
+static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
+{
+    *val = mseccfg_csr_read(env);
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
+                         target_ulong val)
+{
+    mseccfg_csr_write(env, val);
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
 
     /* Physical Memory Protection */
+    [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
     return val;
 }
 
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+    int i;
+
+    trace_mseccfg_csr_write(env->mhartid, val);
+
+    /* RLB cannot be enabled if it's already 0 and if any regions are locked */
+    if (!MSECCFG_RLB_ISSET(env)) {
+        for (i = 0; i < MAX_RISCV_PMPS; i++) {
+            if (pmp_is_locked(env, i)) {
+                val &= ~MSECCFG_RLB;
+                break;
+            }
+        }
+    }
+
+    /* Sticky bits */
+    val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+    env->mseccfg = val;
+}
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+    trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+    return env->mseccfg;
+}
+
 /*
  * Calculate the TLB size if the start address or the end address of
  * PMP entry is presented in thie TLB page.
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/trace-events
+++ b/target/riscv/trace-events
@@ -XXX,XX +XXX,XX @@ pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRI
 pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
 pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
 pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
+
+mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
+mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
-- 
2.31.1

From: Hou Weiying <weiying_hou@outlook.com>

This commit adds support for ePMP v0.9.1.

The ePMP spec can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: fef23b885f9649a4d54e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Rebase on master
 - Update to latest spec
 - Use a switch case to handle ePMP MML permissions
 - Fix a few bugs
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 154 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 146 insertions(+), 8 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
 static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
 {
     if (pmp_index < MAX_RISCV_PMPS) {
-        if (!pmp_is_locked(env, pmp_index)) {
-            env->pmp_state.pmp[pmp_index].cfg_reg = val;
-            pmp_update_rule(env, pmp_index);
+        bool locked = true;
+
+        if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+            /* mseccfg.RLB is set */
+            if (MSECCFG_RLB_ISSET(env)) {
+                locked = false;
+            }
+
+            /* mseccfg.MML is not set */
+            if (!MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, pmp_index)) {
+                locked = false;
+            }
+
+            /* mseccfg.MML is set */
+            if (MSECCFG_MML_ISSET(env)) {
+                /* not adding execute bit */
+                if ((val & PMP_LOCK) != 0 && (val & PMP_EXEC) != PMP_EXEC) {
+                    locked = false;
+                }
+                /* shared region and not adding X bit */
+                if ((val & PMP_LOCK) != PMP_LOCK &&
+                    (val & 0x7) != (PMP_WRITE | PMP_EXEC)) {
+                    locked = false;
+                }
+            }
         } else {
+            if (!pmp_is_locked(env, pmp_index)) {
+                locked = false;
+            }
+        }
+
+        if (locked) {
             qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
+        } else {
+            env->pmp_state.pmp[pmp_index].cfg_reg = val;
+            pmp_update_rule(env, pmp_index);
         }
     } else {
         qemu_log_mask(LOG_GUEST_ERROR,
@@ -XXX,XX +XXX,XX @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
 {
     bool ret;
 
+    if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+        if (MSECCFG_MMWP_ISSET(env)) {
+            /*
+             * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
+             * so we default to deny all, even for M-mode.
+             */
+            *allowed_privs = 0;
+            return false;
+        } else if (MSECCFG_MML_ISSET(env)) {
+            /*
+             * The Machine Mode Lockdown (mseccfg.MML) bit is set
+             * so we can only execute code in M-mode with an applicable
+             * rule. Other modes are disabled.
+             */
+            if (mode == PRV_M && !(privs & PMP_EXEC)) {
+                ret = true;
+                *allowed_privs = PMP_READ | PMP_WRITE;
+            } else {
+                ret = false;
+                *allowed_privs = 0;
+            }
+
+            return ret;
+        }
+    }
+
     if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
         /*
          * Privileged spec v1.10 states if HW doesn't implement any PMP entry
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
             pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
 
         /*
-         * If the PMP entry is not off and the address is in range, do the priv
-         * check
+         * Convert the PMP permissions to match the truth table in the
+         * ePMP spec.
          */
+        const uint8_t epmp_operation =
+            ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
+            ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
+            (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
+            ((env->pmp_state.pmp[i].cfg_reg & PMP_EXEC) >> 2);
+
         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
-            *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-            if ((mode != PRV_M) || pmp_is_locked(env, i)) {
-                *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+            /*
+             * If the PMP entry is not off and the address is in range,
+             * do the priv check
+             */
+            if (!MSECCFG_MML_ISSET(env)) {
+                /*
+                 * If mseccfg.MML Bit is not set, do pmp priv check
+                 * This will always apply to regular PMP.
+                 */
+                *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+                if ((mode != PRV_M) || pmp_is_locked(env, i)) {
+                    *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
+                }
+            } else {
+                /*
+                 * If mseccfg.MML Bit set, do the enhanced pmp priv check
+                 */
+                if (mode == PRV_M) {
+                    switch (epmp_operation) {
+                    case 0:
+                    case 1:
+                    case 4:
+                    case 5:
+                    case 6:
+                    case 7:
+                    case 8:
+                        *allowed_privs = 0;
+                        break;
+                    case 2:
+                    case 3:
+                    case 14:
+                        *allowed_privs = PMP_READ | PMP_WRITE;
+                        break;
+                    case 9:
+                    case 10:
+                        *allowed_privs = PMP_EXEC;
+                        break;
+                    case 11:
+                    case 13:
+                        *allowed_privs = PMP_READ | PMP_EXEC;
+                        break;
+                    case 12:
+                    case 15:
+                        *allowed_privs = PMP_READ;
+                        break;
+                    }
+                } else {
+                    switch (epmp_operation) {
+                    case 0:
+                    case 8:
+                    case 9:
+                    case 12:
+                    case 13:
+                    case 14:
+                        *allowed_privs = 0;
+                        break;
+                    case 1:
+                    case 10:
+                    case 11:
+                        *allowed_privs = PMP_EXEC;
+                        break;
+                    case 2:
+                    case 4:
+                    case 15:
+                        *allowed_privs = PMP_READ;
+                        break;
+                    case 3:
+                    case 6:
+                        *allowed_privs = PMP_READ | PMP_WRITE;
+                        break;
+                    case 5:
+                        *allowed_privs = PMP_READ | PMP_EXEC;
+                        break;
+                    case 7:
+                        *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
+                        break;
+                    }
+                }
             }
 
             ret = ((privs & *allowed_privs) == privs);
-- 
2.31.1

From: Hou Weiying <weiying_hou@outlook.com>

Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         uint16_t elen;
         bool mmu;
         bool pmp;
+        bool epmp;
         uint64_t resetvec;
     } cfg;
 };
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 
     if (cpu->cfg.pmp) {
         set_feature(env, RISCV_FEATURE_PMP);
+
+        /*
+         * Enhanced PMP should only be available
+         * on harts with PMP support
+         */
+        if (cpu->cfg.epmp) {
+            set_feature(env, RISCV_FEATURE_EPMP);
+        }
     }
 
     set_resetvec(env, cpu->cfg.resetvec);
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+    DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
+
     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
     DEFINE_PROP_END_OF_LIST(),
 };
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419060302.14075-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
     uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
-    uint32_t index, i;                                                    \
+    uint64_t index;                                                       \
+    uint32_t i;                                                           \
                                                                           \
     for (i = 0; i < vl; i++) {                                            \
         if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
     uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
     uint32_t vm = vext_vm(desc);                                          \
     uint32_t vl = env->vl;                                                \
-    uint32_t index = s1, i;                                               \
+    uint64_t index = s1;                                                  \
+    uint32_t i;                                                           \
                                                                           \
     for (i = 0; i < vl; i++) {                                            \
         if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
-- 
2.31.1

From: Emmanuel Blot <emmanuel.blot@sifive.com>

When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 
     if (access_type == MMU_DATA_STORE) {
         cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
-    } else {
+    } else if (access_type == MMU_DATA_LOAD) {
         cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+    } else {
+        cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
     }
 
     env->badaddr = addr;
-- 
2.31.1

From: Alexander Wagner <alexander.wagner@ulal.de>

The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".

[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 
     /* Boot ROM */
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

In IEEE 754-2008 spec:
  Invalid operation exception is signaled when doing:
  fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
  unless c is a quiet NaN; if c is a quiet NaN then it is
  implementation defined whether the invalid operation exception
  is signaled.

In RISC-V Unprivileged ISA spec:
  The fused multiply-add instructions must set the invalid
  operation exception flag when the multiplicands are Inf and
  zero, even when the addend is a quiet NaN.

This commit set invalid operation execption flag for RISC-V when
multiplicands of muladd instructions are Inf and zero.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210420013150.21992-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 fpu/softfloat-specialize.c.inc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
     } else {
         return 1;
     }
+#elif defined(TARGET_RISCV)
+    /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
+    if (infzero) {
+        float_raise(float_flag_invalid, status);
+    }
+    return 3; /* default NaN */
 #elif defined(TARGET_XTENSA)
     /*
      * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu.h | 6 ------
 target/riscv/cpu.c | 6 +++++-
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
 
-#if defined(TARGET_RISCV32)
-#define RVXLEN RV32
-#elif defined(TARGET_RISCV64)
-#define RVXLEN RV64
-#endif
-
 #define RV(x) ((target_ulong)1 << (x - 'A'))
 
 #define RVI RV('I')
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
 static void riscv_any_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#if defined(TARGET_RISCV32)
+    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#elif defined(TARGET_RISCV64)
+    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#endif
     set_priv_version(env, PRIV_VERSION_1_11_0);
 }
 
-- 
2.31.1

This also ensures that the SD bit is not writable.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h | 6 ------
 target/riscv/csr.c      | 9 ++++++++-
 2 files changed, 8 insertions(+), 7 deletions(-)

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h   | 11 -----------
 target/riscv/cpu_helper.c | 24 +++++++++++++++---------
 2 files changed, 15 insertions(+), 20 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define CSR_HTIMEDELTA      0x605
 #define CSR_HTIMEDELTAH     0x615
 
-#if defined(TARGET_RISCV32)
-#define HGATP_MODE           SATP32_MODE
-#define HGATP_VMID           SATP32_ASID
-#define HGATP_PPN            SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define HGATP_MODE           SATP64_MODE
-#define HGATP_VMID           SATP64_ASID
-#define HGATP_PPN            SATP64_PPN
-#endif
-
 /* Virtual CSRs */
 #define CSR_VSSTATUS        0x200
 #define CSR_VSIE            0x204
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         }
         widened = 0;
     } else {
-        base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
-        vm = get_field(env->hgatp, HGATP_MODE);
+        if (riscv_cpu_is_32bit(env)) {
+            base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
+            vm = get_field(env->hgatp, SATP32_MODE);
+        } else {
+            base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
+            vm = get_field(env->hgatp, SATP64_MODE);
+        }
         widened = 2;
     }
     /* status.SUM will be ignored if execute on background */
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
                                 bool first_stage, bool two_stage)
 {
     CPUState *cs = env_cpu(env);
-    int page_fault_exceptions;
+    int page_fault_exceptions, vm;
+
     if (first_stage) {
-        page_fault_exceptions =
-            get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
-            !pmp_violation;
+        vm = get_field(env->satp, SATP_MODE);
+    } else if (riscv_cpu_is_32bit(env)) {
+        vm = get_field(env->hgatp, SATP32_MODE);
     } else {
-        page_fault_exceptions =
-            get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
-            !pmp_violation;
+        vm = get_field(env->hgatp, SATP64_MODE);
     }
+    page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
+
     switch (access_type) {
     case MMU_INST_FETCH:
         if (riscv_cpu_virt_enabled(env) && !first_stage) {
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h  | 10 ----------
 target/riscv/csr.c       | 12 ++++++++++--
 target/riscv/translate.c | 19 +++++++++++++++++--
 3 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define MXL_RV64            2
 #define MXL_RV128           3
 
-#if defined(TARGET_RISCV32)
-#define MSTATUS_SD MSTATUS32_SD
-#define MISA_MXL MISA32_MXL
-#define MXL_VAL MXL_RV32
-#elif defined(TARGET_RISCV64)
-#define MSTATUS_SD MSTATUS64_SD
-#define MISA_MXL MISA64_MXL
-#define MXL_VAL MXL_RV64
-#endif
-
 /* sstatus CSR bits */
 #define SSTATUS_UIE         0x00000001
 #define SSTATUS_SIE         0x00000002
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 
     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
-    mstatus = set_field(mstatus, MSTATUS_SD, dirty);
+    if (riscv_cpu_is_32bit(env)) {
+        mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
+    } else {
+        mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+    }
     env->mstatus = mstatus;
 
     return RISCV_EXCP_NONE;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
     }
 
     /* misa.MXL writes are not supported by QEMU */
-    val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
+    if (riscv_cpu_is_32bit(env)) {
+        val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
+    } else {
+        val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+    }
 
     /* flush translation cache */
     if (val != env->misa) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
     return ctx->misa & ext;
 }
 
+#ifdef TARGET_RISCV32
+# define is_32bit(ctx)  true
+#elif defined(CONFIG_USER_ONLY)
+# define is_32bit(ctx)  false
+#else
+static inline bool is_32bit(DisasContext *ctx)
+{
+    return (ctx->misa & RV32) == RV32;
+}
+#endif
+
 /*
  * RISC-V requires NaN-boxing of narrower width floating point values.
  * This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
+    target_ulong sd;
+
     if (ctx->mstatus_fs == MSTATUS_FS) {
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
     ctx->mstatus_fs = MSTATUS_FS;
 
     tmp = tcg_temp_new();
+    sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+
     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 
     if (ctx->virt_enabled) {
         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
     }
     tcg_temp_free(tmp);
-- 
2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h   | 11 -----------
 target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++--------
 target/riscv/csr.c        | 19 +++++++++++++++----
 target/riscv/monitor.c    | 22 +++++++++++++++++-----
 4 files changed, 56 insertions(+), 28 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define SATP64_ASID         0x0FFFF00000000000ULL
 #define SATP64_PPN          0x00000FFFFFFFFFFFULL
 
-#if defined(TARGET_RISCV32)
-#define SATP_MODE           SATP32_MODE
-#define SATP_ASID           SATP32_ASID
-#define SATP_PPN            SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define SATP_MODE           SATP64_MODE
-#define SATP_ASID           SATP64_ASID
-#define SATP_PPN            SATP64_PPN
-#endif
-
 /* VM modes (mstatus.vm) privileged ISA 1.9.1 */
 #define VM_1_09_MBARE       0
 #define VM_1_09_MBB         1
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
 
     if (first_stage == true) {
         if (use_background) {
-            base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
-            vm = get_field(env->vsatp, SATP_MODE);
+            if (riscv_cpu_is_32bit(env)) {
+                base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
+                vm = get_field(env->vsatp, SATP32_MODE);
+            } else {
+                base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
+                vm = get_field(env->vsatp, SATP64_MODE);
+            }
         } else {
-            base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
-            vm = get_field(env->satp, SATP_MODE);
+            if (riscv_cpu_is_32bit(env)) {
+                base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+                vm = get_field(env->satp, SATP32_MODE);
+            } else {
+                base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+                vm = get_field(env->satp, SATP64_MODE);
+            }
         }
         widened = 0;
     } else {
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 {
     CPUState *cs = env_cpu(env);
     int page_fault_exceptions, vm;
+    uint64_t stap_mode;
+
+    if (riscv_cpu_is_32bit(env)) {
+        stap_mode = SATP32_MODE;
+    } else {
+        stap_mode = SATP64_MODE;
+    }
 
     if (first_stage) {
-        vm = get_field(env->satp, SATP_MODE);
-    } else if (riscv_cpu_is_32bit(env)) {
-        vm = get_field(env->hgatp, SATP32_MODE);
+        vm = get_field(env->satp, stap_mode);
     } else {
-        vm = get_field(env->hgatp, SATP64_MODE);
+        vm = get_field(env->hgatp, stap_mode);
     }
+
     page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
 
     switch (access_type) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
 static RISCVException write_satp(CPURISCVState *env, int csrno,
                                  target_ulong val)
 {
+    int vm, mask, asid;
+
     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
         return RISCV_EXCP_NONE;
     }
-    if (validate_vm(env, get_field(val, SATP_MODE)) &&
-        ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
-    {
+
+    if (riscv_cpu_is_32bit(env)) {
+        vm = validate_vm(env, get_field(val, SATP32_MODE));
+        mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
+        asid = (val ^ env->satp) & SATP32_ASID;
+    } else {
+        vm = validate_vm(env, get_field(val, SATP64_MODE));
+        mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
+        asid = (val ^ env->satp) & SATP64_ASID;
+    }
+
+    if (vm && mask) {
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
             return RISCV_EXCP_ILLEGAL_INST;
         } else {
-            if ((val ^ env->satp) & SATP_ASID) {
+            if (asid) {
                 tlb_flush(env_cpu(env));
             }
             env->satp = val;
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -XXX,XX +XXX,XX @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
     target_ulong last_size;
     int last_attr;
 
-    base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+    if (riscv_cpu_is_32bit(env)) {
+        base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+        vm = get_field(env->satp, SATP32_MODE);
+    } else {
+        base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+        vm = get_field(env->satp, SATP64_MODE);
+    }
 
-    vm = get_field(env->satp, SATP_MODE);
     switch (vm) {
     case VM_1_10_SV32:
         levels = 2;
@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
         return;
     }
 
-    if (!(env->satp & SATP_MODE)) {
-        monitor_printf(mon, "No translation or protection\n");
-        return;
+    if (riscv_cpu_is_32bit(env)) {
+        if (!(env->satp & SATP32_MODE)) {
+            monitor_printf(mon, "No translation or protection\n");
+            return;
+        }
+    } else {
+        if (!(env->satp & SATP64_MODE)) {
+            monitor_printf(mon, "No translation or protection\n");
+            return;
+        }
     }
 
     mem_info_svxx(mon, env);
-- 
2.31.1

This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/helper.h                   | 18 +++--
 target/riscv/insn32-64.decode           | 88 -------------------------
 target/riscv/insn32.decode              | 67 ++++++++++++++++++-
 target/riscv/fpu_helper.c               | 16 ++---
 target/riscv/translate.c                |  9 ++-
 target/riscv/vector_helper.c            |  4 --
 target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
 target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
 target/riscv/insn_trans/trans_rvf.c.inc |  6 +-
 target/riscv/insn_trans/trans_rvh.c.inc |  8 ++-
 target/riscv/insn_trans/trans_rvi.c.inc | 16 +++--
 target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
 target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
 target/riscv/meson.build                |  2 +-
 14 files changed, 166 insertions(+), 150 deletions(-)
 delete mode 100644 target/riscv/insn32-64.decode

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Floating Point - Double Precision */
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
 DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
 DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
-DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Special functions */
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
 DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
 DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
 DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
-#ifdef TARGET_RISCV64
 DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamoaddw_v_d,  void, ptr, ptr, tl, ptr, env, i32)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
-#endif
 DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamoaddw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamoxorw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/target/riscv/insn32-64.decode
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-#
-# RISC-V translation routines for the RV Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program.  If not, see <http://www.gnu.org/licenses/>.
-
-# This is concatenated with insn32.decode for risc64 targets.
-# Most of the fields and formats are there.
-
-%sh5    20:5
-
-@sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
-
-# *** RV64I Base Instruction Set (in addition to RV32I) ***
-lwu      ............   ..... 110 ..... 0000011 @i
-ld       ............   ..... 011 ..... 0000011 @i
-sd       ....... .....  ..... 011 ..... 0100011 @s
-addiw    ............   ..... 000 ..... 0011011 @i
-slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
-srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
-sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
-addw     0000000 .....  ..... 000 ..... 0111011 @r
-subw     0100000 .....  ..... 000 ..... 0111011 @r
-sllw     0000000 .....  ..... 001 ..... 0111011 @r
-srlw     0000000 .....  ..... 101 ..... 0111011 @r
-sraw     0100000 .....  ..... 101 ..... 0111011 @r
-
-# *** RV64M Standard Extension (in addition to RV32M) ***
-mulw     0000001 .....  ..... 000 ..... 0111011 @r
-divw     0000001 .....  ..... 100 ..... 0111011 @r
-divuw    0000001 .....  ..... 101 ..... 0111011 @r
-remw     0000001 .....  ..... 110 ..... 0111011 @r
-remuw    0000001 .....  ..... 111 ..... 0111011 @r
-
-# *** RV64A Standard Extension (in addition to RV32A) ***
-lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
-sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
-amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
-amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
-amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
-amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
-amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
-amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
-amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
-
-#*** Vector AMO operations (in addition to Zvamo) ***
-vamoswapd_v     00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoaddd_v      00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoxord_v      00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoandd_v      01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoord_v       01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-
-# *** RV64F Standard Extension (in addition to RV32F) ***
-fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
-fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
-fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
-fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
-
-# *** RV64D Standard Extension (in addition to RV32D) ***
-fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
-fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
-fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
-fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
-fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
-fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
-
-# *** RV32H Base Instruction Set ***
-hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
-hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
-hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 %rs2       20:5
 %rs1       15:5
 %rd        7:5
+%sh5       20:5
 
 %sh10    20:10
 %csr    20:12
@@ -XXX,XX +XXX,XX @@
 @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
 
+# Formats 64:
+@sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
 
 # *** Privileged Instructions ***
 ecall       000000000000     00000 000 00000 1110011
@@ -XXX,XX +XXX,XX @@ csrrwi   ............     ..... 101 ..... 1110011 @csr
 csrrsi   ............     ..... 110 ..... 1110011 @csr
 csrrci   ............     ..... 111 ..... 1110011 @csr
 
+# *** RV64I Base Instruction Set (in addition to RV32I) ***
+lwu      ............   ..... 110 ..... 0000011 @i
+ld       ............   ..... 011 ..... 0000011 @i
+sd       ....... .....  ..... 011 ..... 0100011 @s
+addiw    ............   ..... 000 ..... 0011011 @i
+slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
+srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
+sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
+addw     0000000 .....  ..... 000 ..... 0111011 @r
+subw     0100000 .....  ..... 000 ..... 0111011 @r
+sllw     0000000 .....  ..... 001 ..... 0111011 @r
+srlw     0000000 .....  ..... 101 ..... 0111011 @r
+sraw     0100000 .....  ..... 101 ..... 0111011 @r
+
 # *** RV32M Standard Extension ***
 mul      0000001 .....  ..... 000 ..... 0110011 @r
 mulh     0000001 .....  ..... 001 ..... 0110011 @r
@@ -XXX,XX +XXX,XX @@ divu     0000001 .....  ..... 101 ..... 0110011 @r
 rem      0000001 .....  ..... 110 ..... 0110011 @r
 remu     0000001 .....  ..... 111 ..... 0110011 @r
 
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw     0000001 .....  ..... 000 ..... 0111011 @r
+divw     0000001 .....  ..... 100 ..... 0111011 @r
+divuw    0000001 .....  ..... 101 ..... 0111011 @r
+remw     0000001 .....  ..... 110 ..... 0111011 @r
+remuw    0000001 .....  ..... 111 ..... 0111011 @r
+
 # *** RV32A Standard Extension ***
 lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
 sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
@@ -XXX,XX +XXX,XX @@ amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
 amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
 amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
 
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
+amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
+amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
+amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
+amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
 # *** RV32F Standard Extension ***
 flw        ............   ..... 010 ..... 0000111 @i
 fsw        .......  ..... ..... 010 ..... 0100111 @s
@@ -XXX,XX +XXX,XX @@ fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
 fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
 fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
 
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
+
 # *** RV32D Standard Extension ***
 fld        ............   ..... 011 ..... 0000111 @i
 fsd        ....... .....  ..... 011 ..... 0100111 @s
@@ -XXX,XX +XXX,XX @@ fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
 fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
 fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
 
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
+fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
+fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
+fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
+
 # *** RV32H Base Instruction Set ***
 hlv_b       0110000  00000  ..... 100 ..... 1110011 @r2
 hlv_bu      0110000  00001  ..... 100 ..... 1110011 @r2
@@ -XXX,XX +XXX,XX @@ hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
 hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
 hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
 
-# *** RV32V Extension ***
+# *** RV32H Base Instruction Set ***
+hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
+hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
+hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 
 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
 vlb_v      ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
@@ -XXX,XX +XXX,XX @@ vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
 
 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
+
+#*** Vector AMO operations (in addition to Zvamo) ***
+vamoswapd_v     00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoaddd_v      00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoxord_v      00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoandd_v      01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoord_v       01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomind_v      10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
     return (int32_t)float32_to_uint32(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
 {
     float32 frs1 = check_nanbox_s(rs1);
     return float32_to_int64(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
+target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
 {
     float32 frs1 = check_nanbox_s(rs1);
     return float32_to_uint64(frs1, &env->fp_status);
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
     return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
 }
 
-uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
 {
     return nanbox_s(int64_to_float32(rs1, &env->fp_status));
 }
 
-uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
 {
     return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
 }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
     return (int32_t)float64_to_uint32(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_int64(frs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
+target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
 {
     return float64_to_uint64(frs1, &env->fp_status);
 }
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
     return uint32_to_float64((uint32_t)rs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
 {
     return int64_to_float64(rs1, &env->fp_status);
 }
 
-uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
+uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
 {
     return uint64_to_float64(rs1, &env->fp_status);
 }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
     }                              \
 } while (0)
 
+#define REQUIRE_64BIT(ctx) do { \
+    if (is_32bit(ctx)) {        \
+        return false;           \
+    }                           \
+} while (0)
+
 static int ex_rvc_register(DisasContext *ctx, int reg)
 {
     return 8 + reg;
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
     return true;
 }
 
-#ifdef TARGET_RISCV64
 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
 {
     tcg_gen_add_tl(ret, arg1, arg2);
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
     return true;
 }
 
-#endif
-
 static bool gen_arith(DisasContext *ctx, arg_r *a,
                       void(*func)(TCGv, TCGv, TCGv))
 {
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w,  32, 32, H4, DO_MIN,  l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w,  32, 32, H4, DO_MAX,  l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
-#ifdef TARGET_RISCV64
 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d,  64, 32, H8, DO_ADD,  l)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
-#endif
 
 static inline void
 vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong base,       \
                       GETPC());                                 \
 }
 
-#ifdef TARGET_RISCV64
 GEN_VEXT_AMO(vamoswapw_v_d, int32_t,  int64_t,  idx_d, clearq)
 GEN_VEXT_AMO(vamoswapd_v_d, int64_t,  int64_t,  idx_d, clearq)
 GEN_VEXT_AMO(vamoaddw_v_d,  int32_t,  int64_t,  idx_d, clearq)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
 GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
 GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
 GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
-#endif
 GEN_VEXT_AMO(vamoswapw_v_w, int32_t,  int32_t,  idx_w, clearl)
 GEN_VEXT_AMO(vamoaddw_v_w,  int32_t,  int32_t,  idx_w, clearl)
 GEN_VEXT_AMO(vamoxorw_v_w,  int32_t,  int32_t,  idx_w, clearl)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
 }
 
-#ifdef TARGET_RISCV64
-
 static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
 }
 
 static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
 }
 
 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
 }
-#endif
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
     return true;
 }
 
-#ifdef TARGET_RISCV64
-
 static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
 
 static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
 
 static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
+#ifdef TARGET_RISCV64
     gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
     return true;
+#else
+    qemu_build_not_reached();
+#endif
 }
 
 static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
 
 static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
 
 static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
+#ifdef TARGET_RISCV64
     TCGv t0 = tcg_temp_new();
     gen_get_gpr(t0, a->rs1);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
     tcg_temp_free(t0);
     mark_fs_dirty(ctx);
     return true;
-}
+#else
+    qemu_build_not_reached();
 #endif
+}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
     return true;
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
 
 static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
 
 static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
 
 static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
     tcg_temp_free(t0);
     return true;
 }
-#endif
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
 #endif
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVH);
+
 #ifndef CONFIG_USER_ONLY
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
 
 static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVH);
+
 #ifndef CONFIG_USER_ONLY
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
 
 static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVH);
+
 #ifndef CONFIG_USER_ONLY
     TCGv t0 = tcg_temp_new();
     TCGv dat = tcg_temp_new();
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
     return false;
 #endif
 }
-#endif
 
 static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
 {
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
     return gen_store(ctx, a, MO_TESL);
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_load(ctx, a, MO_TEUL);
 }
 
 static bool trans_ld(DisasContext *ctx, arg_ld *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_load(ctx, a, MO_TEQ);
 }
 
 static bool trans_sd(DisasContext *ctx, arg_sd *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_store(ctx, a, MO_TEQ);
 }
-#endif
 
 static bool trans_addi(DisasContext *ctx, arg_addi *a)
 {
@@ -XXX,XX +XXX,XX @@ static bool trans_and(DisasContext *ctx, arg_and *a)
     return gen_arith(ctx, a, &tcg_gen_and_tl);
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_arith_imm_tl(ctx, a, &gen_addw);
 }
 
 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv source1;
     source1 = tcg_temp_new();
     gen_get_gpr(source1, a->rs1);
@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 
 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv t = tcg_temp_new();
     gen_get_gpr(t, a->rs1);
     tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 
 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv t = tcg_temp_new();
     gen_get_gpr(t, a->rs1);
     tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
@@ -XXX,XX +XXX,XX @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 
 static bool trans_addw(DisasContext *ctx, arg_addw *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_arith(ctx, a, &gen_addw);
 }
 
 static bool trans_subw(DisasContext *ctx, arg_subw *a)
 {
+    REQUIRE_64BIT(ctx);
     return gen_arith(ctx, a, &gen_subw);
 }
 
 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
@@ -XXX,XX +XXX,XX @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 
 static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
@@ -XXX,XX +XXX,XX @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 
 static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 {
+    REQUIRE_64BIT(ctx);
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
@@ -XXX,XX +XXX,XX @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 
     return true;
 }
-#endif
 
 static bool trans_fence(DisasContext *ctx, arg_fence *a)
 {
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
     return gen_arith(ctx, a, &gen_remu);
 }
 
-#ifdef TARGET_RISCV64
 static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith(ctx, a, &gen_mulw);
 }
 
 static bool trans_divw(DisasContext *ctx, arg_divw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith_div_w(ctx, a, &gen_div);
 }
 
 static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith_div_uw(ctx, a, &gen_divu);
 }
 
 static bool trans_remw(DisasContext *ctx, arg_remw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith_div_w(ctx, a, &gen_rem);
 }
 
 static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
 {
+    REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
+
     return gen_arith_div_uw(ctx, a, &gen_remu);
 }
-#endif
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
         gen_helper_vamominuw_v_w,
         gen_helper_vamomaxuw_v_w
     };
-#ifdef TARGET_RISCV64
     static gen_helper_amo *const fnsd[18] = {
         gen_helper_vamoswapw_v_d,
         gen_helper_vamoaddw_v_d,
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
         gen_helper_vamominud_v_d,
         gen_helper_vamomaxud_v_d
     };
-#endif
 
     if (tb_cflags(s->base.tb) & CF_PARALLEL) {
         gen_helper_exit_atomic(cpu_env);
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
         return true;
     } else {
         if (s->sew == 3) {
-#ifdef TARGET_RISCV64
-            fn = fnsd[seq];
-#else
-            /* Check done in amo_check(). */
-            g_assert_not_reached();
-#endif
+            if (!is_32bit(s)) {
+                fn = fnsd[seq];
+            } else {
+                /* Check done in amo_check(). */
+                g_assert_not_reached();
+            }
         } else {
             assert(seq < ARRAY_SIZE(fnsw));
             fn = fnsw[seq];
@@ -XXX,XX +XXX,XX @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
             ((1 << s->sew) >= 4));
 }
 
+static bool amo_check64(DisasContext *s, arg_rwdvm* a)
+{
+    return !is_32bit(s) && amo_check(s, a);
+}
+
 GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
 GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
-#ifdef TARGET_RISCV64
-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
-#endif
+GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64)
+GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64)
 
 /*
  *** Vector Integer Arithmetic Instructions
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ gen32 = [
 
 gen64 = [
   decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
-  decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
+  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
 ]
 
 riscv_ss = ss.source_set()
-- 
2.31.1

This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/insn16-32.decode           | 28 -------------------
 target/riscv/insn16-64.decode           | 36 -------------------------
 target/riscv/insn16.decode              | 30 +++++++++++++++++++++
 target/riscv/insn_trans/trans_rvi.c.inc |  6 +++++
 target/riscv/meson.build                | 11 +++-----
 5 files changed, 39 insertions(+), 72 deletions(-)
 delete mode 100644 target/riscv/insn16-32.decode
 delete mode 100644 target/riscv/insn16-64.decode

diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/target/riscv/insn16-32.decode
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-#
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program.  If not, see <http://www.gnu.org/licenses/>.
-
-# *** RV32C Standard Extension (Quadrant 0) ***
-flw               011  ... ... .. ... 00 @cl_w
-fsw               111  ... ... .. ... 00 @cs_w
-
-# *** RV32C Standard Extension (Quadrant 1) ***
-jal               001     ........... 01 @cj    rd=1  # C.JAL
-
-# *** RV32C Standard Extension (Quadrant 2) ***
-flw               011 .  .....  ..... 10 @c_lwsp
-fsw               111 .  .....  ..... 10 @c_swsp
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/target/riscv/insn16-64.decode
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-#
-# RISC-V translation routines for the RVXI Base Integer Instruction Set.
-#
-# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
-#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2 or later, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program.  If not, see <http://www.gnu.org/licenses/>.
-
-# *** RV64C Standard Extension (Quadrant 0) ***
-ld                011  ... ... .. ... 00 @cl_d
-sd                111  ... ... .. ... 00 @cs_d
-
-# *** RV64C Standard Extension (Quadrant 1) ***
-{
-  illegal         001 -  00000  ----- 01 # c.addiw, RES rd=0
-  addiw           001 .  .....  ..... 01 @ci
-}
-subw              100 1 11 ... 00 ... 01 @cs_2
-addw              100 1 11 ... 01 ... 01 @cs_2
-
-# *** RV64C Standard Extension (Quadrant 2) ***
-{
-  illegal         011 -  00000  ----- 10 # c.ldsp, RES rd=0
-  ld              011 .  .....  ..... 10 @c_ldsp
-}
-sd                111 .  .....  ..... 10 @c_sdsp
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -XXX,XX +XXX,XX @@ lw                010  ... ... .. ... 00 @cl_w
 fsd               101  ... ... .. ... 00 @cs_d
 sw                110  ... ... .. ... 00 @cs_w
 
+# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
+{
+  ld              011  ... ... .. ... 00 @cl_d
+  flw             011  ... ... .. ... 00 @cl_w
+}
+{
+  sd              111  ... ... .. ... 00 @cs_d
+  fsw             111  ... ... .. ... 00 @cs_w
+}
+
 # *** RV32/64C Standard Extension (Quadrant 1) ***
 addi              000 .  .....  ..... 01 @ci
 addi              010 .  .....  ..... 01 @c_li
@@ -XXX,XX +XXX,XX @@ jal               101     ........... 01 @cj    rd=0  # C.J
 beq               110  ... ...  ..... 01 @cb_z
 bne               111  ... ...  ..... 01 @cb_z
 
+# *** RV64C and RV32C specific Standard Extension (Quadrant 1) ***
+{
+  c64_illegal     001 -  00000  ----- 01 # c.addiw, RES rd=0
+  addiw           001 .  .....  ..... 01 @ci
+  jal             001     ........... 01 @cj    rd=1  # C.JAL
+}
+subw              100 1 11 ... 00 ... 01 @cs_2
+addw              100 1 11 ... 01 ... 01 @cs_2
+
 # *** RV32/64C Standard Extension (Quadrant 2) ***
 slli              000 .  .....  ..... 10 @c_shift2
 fld               001 .  .....  ..... 10 @c_ldsp
@@ -XXX,XX +XXX,XX @@ fld               001 .  .....  ..... 10 @c_ldsp
 }
 fsd               101   ......  ..... 10 @c_sdsp
 sw                110 .  .....  ..... 10 @c_swsp
+
+# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
+{
+  c64_illegal     011 -  00000  ----- 10 # c.ldsp, RES rd=0
+  ld              011 .  .....  ..... 10 @c_ldsp
+  flw             011 .  .....  ..... 10 @c_lwsp
+}
+{
+  sd              111 .  .....  ..... 10 @c_sdsp
+  fsw             111 .  .....  ..... 10 @c_swsp
+}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
     return true;
 }
 
+static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
+{
+     REQUIRE_64BIT(ctx);
+     return trans_illegal(ctx, a);
+}
+
 static bool trans_lui(DisasContext *ctx, arg_lui *a)
 {
     if (a->rd != 0) {
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@
 # FIXME extra_args should accept files()
 dir = meson.current_source_dir()
-gen32 = [
-  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
-  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
-]
 
-gen64 = [
-  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+gen = [
+  decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
   decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
 ]
 
 riscv_ss = ss.source_set()
-riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
-riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
+riscv_ss.add(gen)
 riscv_ss.add(files(
   'cpu.c',
   'cpu_helper.c',
-- 
2.31.1