Patches applied successfully (
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apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20210505232312.4175486-1-alistair.francis@wdc.com
Maintainers: Alistair Francis <Alistair.Francis@wdc.com>, "Alex Bennée" <alex.bennee@linaro.org>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Palmer Dabbelt <palmer@dabbelt.com>, Peter Maydell <peter.maydell@linaro.org>, Vijai Kumar K <vijai@behindbytes.com>, Alistair Francis <alistair.francis@wdc.com>, Alistair Francis <alistair@alistair23.me>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Aurelien Jarno <aurelien@aurel32.net>, Bin Meng <bin.meng@windriver.com>, Paolo Bonzini <pbonzini@redhat.com>
docs/system/generic-loader.rst | 9 +-
docs/system/riscv/shakti-c.rst | 82 +++
docs/system/target-riscv.rst | 1 +
default-configs/devices/riscv64-softmmu.mak | 1 +
include/hw/char/shakti_uart.h | 74 +++
include/hw/riscv/opentitan.h | 16 +-
include/hw/riscv/shakti_c.h | 75 +++
target/riscv/cpu.h | 42 +-
target/riscv/cpu_bits.h | 114 +---
target/riscv/helper.h | 18 +-
target/riscv/pmp.h | 14 +
target/riscv/insn16-32.decode | 28 -
target/riscv/insn16-64.decode | 36 --
target/riscv/insn16.decode | 30 +
target/riscv/insn32-64.decode | 88 ---
target/riscv/insn32.decode | 67 ++-
hw/char/shakti_uart.c | 185 +++++++
hw/intc/ibex_plic.c | 20 +-
hw/riscv/opentitan.c | 10 +-
hw/riscv/shakti_c.c | 178 ++++++
hw/riscv/sifive_e.c | 2 +-
target/riscv/cpu.c | 26 +-
target/riscv/cpu_helper.c | 88 ++-
target/riscv/csr.c | 824 +++++++++++++++++-----------
target/riscv/fpu_helper.c | 16 +-
target/riscv/gdbstub.c | 8 +-
target/riscv/machine.c | 8 +-
target/riscv/monitor.c | 22 +-
target/riscv/op_helper.c | 18 +-
target/riscv/pmp.c | 218 +++++++-
target/riscv/translate.c | 38 +-
target/riscv/vector_helper.c | 18 +-
fpu/softfloat-specialize.c.inc | 6 +
target/riscv/insn_trans/trans_rva.c.inc | 14 +-
target/riscv/insn_trans/trans_rvd.c.inc | 17 +-
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
target/riscv/insn_trans/trans_rvh.c.inc | 8 +-
target/riscv/insn_trans/trans_rvi.c.inc | 22 +-
target/riscv/insn_trans/trans_rvm.c.inc | 12 +-
target/riscv/insn_trans/trans_rvv.c.inc | 39 +-
MAINTAINERS | 14 +-
hw/char/meson.build | 1 +
hw/char/trace-events | 4 +
hw/riscv/Kconfig | 11 +
hw/riscv/meson.build | 1 +
target/riscv/meson.build | 13 +-
target/riscv/trace-events | 3 +
47 files changed, 1756 insertions(+), 789 deletions(-)
create mode 100644 docs/system/riscv/shakti-c.rst
create mode 100644 include/hw/char/shakti_uart.h
create mode 100644 include/hw/riscv/shakti_c.h
delete mode 100644 target/riscv/insn16-32.decode
delete mode 100644 target/riscv/insn16-64.decode
delete mode 100644 target/riscv/insn32-64.decode
create mode 100644 hw/char/shakti_uart.c
create mode 100644 hw/riscv/shakti_c.c