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IronPort-SDR: vcNdUApB2DBmMYsZFoJEioCvzgcOcWaZIjS9oOJhu8ZBS8OyYLmqPiSXeZF5jdTfvTfKlVdUFw vJf++Gkhi9NQnXN2gr86kyVi8hXj0dRYuidKs3D4KCNDJqQRgV8Xcfl+WA5OQvetZm+zd5SObZ cDjSgNQGltQUE5SKtbEEIJ6safQN4yRQ+NSwG8qHljGpQ0azO0BtCBWeVcR8IdkY3WiHtCIzCz PnSngvO44cscNWl4C2nRT+q8oiY4iu1/JNkZA/lxAIHOvFZAXiVAoNIUr0qx1aqckHaDgm5Fs/ MQ0= X-IronPort-AV: E=Sophos;i="5.82,276,1613404800"; d="scan'208";a="278356859" IronPort-SDR: y3R3atnnbqbezp3zaBa4UTJsVNME2qDyKh/ESsHuyOaHyHOgl/IflK0BgonOWXWnNMD3RRVB13 +rDKFDdl5rdqMWMiUfnWY+vTNW1Wa5CHYRDYCfdKKoHxjt+dwRnO2yR7QSs+atZ8D3lBC7DSD2 eNXbspInl1TYawUEzcMoWHpk7oa49iaMLZpepMo0Zb3dQxNWDUekHICsJbDslFr4gBCHhvzqKt J2Nhl3LZIreVSf/FTYAyWqeM1QXS345E0u2t5jh9F5LKslWi+zJMDt3ibnWkC8u/V7VyBIgk6o GVySrBfldp4LpPKVK40yPpeZ IronPort-SDR: p7TUoCbF3THql5MbYY/D1wreRvZoW80niayMF70yfdTsj14rkC9SdpNv577K55Ydof+W8Cc/n+ KwGzH6Orx2D0VDYhpvvhCNw3kpEyWlWAFWs9ypQIdDCig2hQYthSD//45y7JjqLLW2SF63Ag/V Y6ktHbnhoaZxDWTPn5UhFsQMKY3HlTIEwxmi5n2HanNyK3FEsULD/xjtCi1W+Ah7vYxgn5w7gm B+Ew5QF0dPcNiwCgpdrNWvNe9x2uZTuoy/Kb84bmnjuywQtH3/Wh4gT8tuix+irfYkDeCkFm2n P28= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code Date: Thu, 6 May 2021 09:22:31 +1000 Message-Id: <20210505232312.4175486-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org, Atish Patra Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Atish Patra Qemu doesn't support RISC-V privilege specification v1.9. Remove the remaining v1.9 specific references from the implementation. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com> [Changes by AF: - Rebase on latest patches - Bump the vmstate_riscv_cpu version_id and minimum_version_id ] Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 +--- target/riscv/cpu_bits.h | 23 --------------------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 12 +++++------ target/riscv/csr.c | 42 ++++++++++----------------------------- target/riscv/machine.c | 8 +++----- target/riscv/translate.c | 4 ++-- 7 files changed, 23 insertions(+), 72 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..311b1db875 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -163,10 +163,8 @@ struct CPURISCVState { target_ulong mie; target_ulong mideleg; =20 - target_ulong sptbr; /* until: priv-1.9.1 */ target_ulong satp; /* since: priv-1.10.0 */ - target_ulong sbadaddr; - target_ulong mbadaddr; + target_ulong stval; target_ulong medeleg; =20 target_ulong stvec; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599207..b42dd4f8d8 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -153,12 +153,6 @@ /* 32-bit only */ #define CSR_MSTATUSH 0x310 =20 -/* Legacy Counter Setup (priv v1.9.1) */ -/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */ -#define CSR_MUCOUNTEREN 0x320 -#define CSR_MSCOUNTEREN 0x321 -#define CSR_MHCOUNTEREN 0x322 - /* Machine Trap Handling */ #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 @@ -166,9 +160,6 @@ #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 =20 -/* Legacy Machine Trap Handling (priv v1.9.1) */ -#define CSR_MBADADDR 0x343 - /* Supervisor Trap Setup */ #define CSR_SSTATUS 0x100 #define CSR_SEDELEG 0x102 @@ -184,9 +175,6 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 =20 -/* Legacy Supervisor Trap Handling (priv v1.9.1) */ -#define CSR_SBADADDR 0x143 - /* Supervisor Protection and Translation */ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 @@ -354,14 +342,6 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 -/* Legacy Machine Protection and Translation (priv v1.9.1) */ -#define CSR_MBASE 0x380 -#define CSR_MBOUND 0x381 -#define CSR_MIBASE 0x382 -#define CSR_MIBOUND 0x383 -#define CSR_MDBASE 0x384 -#define CSR_MDBOUND 0x385 - /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 @@ -375,10 +355,8 @@ #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 #define MSTATUS_MPRV 0x00020000 -#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define MSTATUS_MXR 0x00080000 -#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ @@ -416,7 +394,6 @@ #define SSTATUS_SPP 0x00000100 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 -#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define SSTATUS_MXR 0x00080000 =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b..86e7dbeb20 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -282,7 +282,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscaus= e); } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 21c54ef561..503c2559f8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -136,8 +136,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->vscause =3D env->scause; env->scause =3D env->scause_hs; =20 - env->vstval =3D env->sbadaddr; - env->sbadaddr =3D env->stval_hs; + env->vstval =3D env->stval; + env->stval =3D env->stval_hs; =20 env->vsatp =3D env->satp; env->satp =3D env->satp_hs; @@ -159,8 +159,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->scause_hs =3D env->scause; env->scause =3D env->vscause; =20 - env->stval_hs =3D env->sbadaddr; - env->sbadaddr =3D env->vstval; + env->stval_hs =3D env->stval; + env->stval =3D env->vstval; =20 env->satp_hs =3D env->satp; env->satp =3D env->vsatp; @@ -1023,7 +1023,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mstatus =3D s; env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); env->sepc =3D env->pc; - env->sbadaddr =3D tval; + env->stval =3D tval; env->htval =3D htval; env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); @@ -1054,7 +1054,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mstatus =3D s; env->mcause =3D cause | ~(((target_ulong)-1) >> async); env->mepc =3D env->pc; - env->mbadaddr =3D tval; + env->mtval =3D tval; env->mtval2 =3D mtval2; env->pc =3D (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d2585395bf..de7427d8f8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -644,26 +644,6 @@ static int write_mcounteren(CPURISCVState *env, int cs= rno, target_ulong val) return 0; } =20 -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ -static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) -{ - if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -RISCV_EXCP_ILLEGAL_INST; - } - *val =3D env->mcounteren; - return 0; -} - -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ -static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v= al) -{ - if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -RISCV_EXCP_ILLEGAL_INST; - } - env->mcounteren =3D val; - return 0; -} - /* Machine Trap Handling */ static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) { @@ -701,15 +681,15 @@ static int write_mcause(CPURISCVState *env, int csrno= , target_ulong val) return 0; } =20 -static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) +static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mbadaddr; + *val =3D env->mtval; return 0; } =20 -static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) +static int write_mtval(CPURISCVState *env, int csrno, target_ulong val) { - env->mbadaddr =3D val; + env->mtval =3D val; return 0; } =20 @@ -853,15 +833,15 @@ static int write_scause(CPURISCVState *env, int csrno= , target_ulong val) return 0; } =20 -static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) +static int read_stval(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->sbadaddr; + *val =3D env->stval; return 0; } =20 -static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) +static int write_stval(CPURISCVState *env, int csrno, target_ulong val) { - env->sbadaddr =3D val; + env->stval =3D val; return 0; } =20 @@ -1419,13 +1399,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_m= statush }, =20 - [CSR_MSCOUNTEREN] =3D { "msounteren", any, read_mscounteren, write_m= scounteren }, - /* Machine Trap Handling */ [CSR_MSCRATCH] =3D { "mscratch", any, read_mscratch, write_mscratch }, [CSR_MEPC] =3D { "mepc", any, read_mepc, write_mepc }, [CSR_MCAUSE] =3D { "mcause", any, read_mcause, write_mcause }, - [CSR_MBADADDR] =3D { "mbadaddr", any, read_mbadaddr, write_mbadaddr }, + [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 /* Supervisor Trap Setup */ @@ -1438,7 +1416,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch = }, [CSR_SEPC] =3D { "sepc", smode, read_sepc, write_sepc = }, [CSR_SCAUSE] =3D { "scause", smode, read_scause, write_scause = }, - [CSR_SBADADDR] =3D { "sbadaddr", smode, read_sbadaddr, write_sbadaddr = }, + [CSR_STVAL] =3D { "stval", smode, read_stval, write_stval }, [CSR_SIP] =3D { "sip", smode, NULL, NULL, rmw_sip = }, =20 /* Supervisor Protection and Translation */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 44d4015bd6..16a08302da 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -165,10 +165,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT32(env.miclaim, RISCVCPU), VMSTATE_UINTTL(env.mie, RISCVCPU), VMSTATE_UINTTL(env.mideleg, RISCVCPU), - VMSTATE_UINTTL(env.sptbr, RISCVCPU), VMSTATE_UINTTL(env.satp, RISCVCPU), - VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), - VMSTATE_UINTTL(env.mbadaddr, RISCVCPU), + VMSTATE_UINTTL(env.stval, RISCVCPU), VMSTATE_UINTTL(env.medeleg, RISCVCPU), VMSTATE_UINTTL(env.stvec, RISCVCPU), VMSTATE_UINTTL(env.sepc, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2f9f5ccc62..26eccc5eb1 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -116,7 +116,7 @@ static void generate_exception(DisasContext *ctx, int e= xcp) ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -static void generate_exception_mbadaddr(DisasContext *ctx, int excp) +static void generate_exception_mtval(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); @@ -160,7 +160,7 @@ static void gen_exception_illegal(DisasContext *ctx) =20 static void gen_exception_inst_addr_mis(DisasContext *ctx) { - generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); + generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); } =20 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620257205; cv=none; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Axel Heider , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Axel Heider Fix style to have a proper description of the parameter 'force-raw'. Signed-off-by: Axel Heider Reviewed-by: Alistair Francis Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a659ac@gmx.de Signed-off-by: Alistair Francis --- docs/system/generic-loader.rst | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst index 6bf8a4eb48..531ddbc8e3 100644 --- a/docs/system/generic-loader.rst +++ b/docs/system/generic-loader.rst @@ -92,9 +92,12 @@ shown below: specified in the executable format header. This option should only be used for the boot image. This will also cause the image to be written to the specified CPU's address space. If not specified, the - default is CPU 0. - Setting force-raw=3Don forces the file - to be treated as a raw image. This can be used to load supported - executable formats as if they were raw. + default is CPU 0. + +```` + Setting 'force-raw=3Don' forces the file to be treated as a raw image. + This can be used to load supported executable formats as if they + were raw. =20 All values are parsed using the standard QemuOpts parsing. This allows the= user to specify any values in any format supported. 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IronPort-SDR: nbthj2Y2aVvxa8XH1DbGCcDx97gsgZDSxnWEOCGL1qHrbKMCG/P82c4wQnT5ySSwf9DQTJyavz SJ8JueeB64xvWUcRkf0IeNqCCfAug40/Fm9fY0VCIKgUAjQNsylXWu+pIFvGRvwfQHXoyMb7OS TenVRC9brIsOLPw1k4GmgcFJcZ5vuOhQtrDPzIop+YFjd9mU9xQirjTZPtTC7BMikrQtiGlHTY cKXvXSzzhf23ow0jBBnKAqQ1v3v537UXtIj5J/u7wsSGG3cLL1hb45bPNZxGRft6AiRsChfxP8 rxc= X-IronPort-AV: E=Sophos;i="5.82,276,1613404800"; d="scan'208";a="278356863" IronPort-SDR: QGSH4fqZjGNnFQsQsG832TX89/V1nvTdVhpFLlJk/++Qt4fbo31wCITcKgpR3sMRZu/vcACeEI PP1kTO/FI2ZDreQ7xWe3jLIh2CenxLBnsZ7CGShDhT9E2nndRHrJwc1iHO8lhDEL6z2t4k58vN +WeBHLmMmr/L6YMDZDIoBmQ2vpPPXpcYWtUosskjB8SRuEhnfPplqmGi+l6Dt+iqk9QtiIWsYv bUM+hzf5ypokYkSqDt8yPKgLb6DmoE4ZWwHX/Y27SX0W1G9hsyHzzVEqG2vO6d8cExA00yXVhL iyC+r9eQWM/PE5xBTRYvp4A7 IronPort-SDR: Rz+qYxiszT9zbcx4mDRMHTB6jy3PjdHftaO4Wrwv3A6lhYiuONzshjX9Tj71ZVIDnikE7Wl0TP p9+OPrxmAJJ91fpm8/XQpZ3ifqNl+pv50D1Xw2GwIYrGql6WRHMkp86OAkhuQrMgacfIRZiz3D TRHVBDZ8hBBlnGe5aA35ol7IypJs+dCl9wF7/THQtyZPey4ERY2brMvxTpWviu3DjytG7PTHY0 nCmjwYjW42QKC2XorMRXFhVp8IKbVbhmH5JmQ6jM8aD3N0HtypHBiFaRvwyDoazKLce4KHpZ8U INk= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 03/42] target/riscv: Align the data type of reset vector address Date: Thu, 6 May 2021 09:22:33 +1000 Message-Id: <20210505232312.4175486-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dylan Jhong , qemu-devel@nongnu.org, Alistair Francis , Ruinland ChuanTzu Tsai , alistair23@gmail.com, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Dylan Jhong Use target_ulong to instead of uint64_t on reset vector address to adapt on both 32/64 machine. Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210329034801.22667-1-dylan@andestech.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 86e7dbeb20..047d6344fe 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature) env->features |=3D (1ULL << feature); } =20 -static void set_resetvec(CPURISCVState *env, int resetvec) +static void set_resetvec(CPURISCVState *env, target_ulong resetvec) { #ifndef CONFIG_USER_ONLY env->resetvec =3D resetvec; --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="278356866" IronPort-SDR: 4fFXAhpJA8siKSoD/nkVWeUMNlACkBcy+5LPm5665s0zNFxZbHaykZBA2AQVJTagTwZWv93tXk RfhMH1RP5t1B9rqzRS25vv+brE3AxGkXpMIvrps+oJQGycTEgNO9jIgY67BejFyacU8PNELVdS uZgKfyBEh6jazsyVt9ncf1cqelaxZLwl6XVW+6Nubp37dItDC5tkcKOBXg8e88uGitb8Ia2PDH OVJbV9NMT1fKPq/Ew9xT00oRpthoHP/WkMXE4tSWxbZMKPASc+25G5ibs4eExX0T7fK65+UEak x+HpqVd4npYZ0NPtb0OVNtp9 IronPort-SDR: c44Dhs3VcTAASm3h91ow3wQTlihJMv16sCSS688p2YPtUfrdjjXI5XkmVuN9ZxM7Ej8Yu9QVuE OmT3aUL2OWGHcbIBUP/+hYeGFJGFYyJ2vOjfeONqRyO6qnSALuckpXPfR53+ryMBV9Nv+xOKRq j9Ikc3A2jPy3nUFJe073eVUCAvg0t9KQnYkSwy+OUHqlPzHmejO38wAGPrBTzLwkCE05CJ7PrH GvpoWMhzODOQwavGXB4E/+j8fCuG2Jx0dv3SC1PcluEaTALW/kHb7q9WzEmPMszpDHnVGFwKA6 Mjo= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Date: Thu, 6 May 2021 09:22:34 +1000 Message-Id: <20210505232312.4175486-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; 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Add it back. Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'") Reported-by: Emmanuel Blot Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20210331103612.654261-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- hw/riscv/sifive_e.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e8b44b2c0..ddc658c8d6 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -48,7 +48,7 @@ #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" =20 -static MemMapEntry sifive_e_memmap[] =3D { +static const MemMapEntry sifive_e_memmap[] =3D { [SIFIVE_E_DEV_DEBUG] =3D { 0x0, 0x1000 }, [SIFIVE_E_DEV_MROM] =3D { 0x1000, 0x2000 }, [SIFIVE_E_DEV_OTP] =3D { 0x20000, 0x2000 }, --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="278356869" IronPort-SDR: vLNvDJk1CmDhsgsIGFOGRGDrRE+2dodFYJ88R/ygzFYF+IYcKmrJU0BRRYCi+3PtopysbKIdXq g5GyuvwBaJQNeL/Xnc7ZkJYpKfeSgejsqr1bRpkggz5a8cr5IGRmCA2jICxLI4zLqXrQ5a8e+5 tnbKBy7bRgMKHYE8s0y8eLxdU9eBquxSt9mtXQkkXH5Ym/xh5aYM0GIAbBLqKAPT4c/v2FiOc8 cOZaX4vJTWvJkjz+H9IQS1rHRIF0B5lBr78+IU1Eet/niVK9hD03TW2L2bHrl81QXuOLLzwb6S pSzxKM8dzfj/D9i20ANUykKz IronPort-SDR: Jsx5xyAgBuShn+TT5EHkbJ3Row0nrVGTjtZrsmAaVOTa6DLbfOriOc5uhUC+JcQDq4gX+8/M7j FOIqpc968I7fuJyAMGJFecKr96w9vQDydWgbbIorhjONwA2WYH58g3C9NpFGxNwV+Gxpg8jt2Y C1eG0Ct8l2XZUnopdhOJnzkGhabtozJfZIFyMRCtzsjKg0AaHY7ZD+iZx3o4lrc9s3k59HfpCA +X1vNb4qjopYaFxyMJceFRdNipKcMFeOjc1L3GkenQ3KQJzu6Sow2NLPXQuLqrHm4dprpSE+Q9 b10= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 05/42] target/riscv: Add Shakti C class CPU Date: Thu, 6 May 2021 09:22:35 +1000 Message-Id: <20210505232312.4175486-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Vijai Kumar K C-Class is a member of the SHAKTI family of processors from IIT-M. It is an extremely configurable and commercial-grade 5-stage in-order core supporting the standard RV64GCSUN ISA extensions. Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis Message-id: 20210401181457.73039-2-vijai@behindbytes.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 311b1db875..8079da8fa8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -38,6 +38,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 047d6344fe..6842626c69 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -708,6 +708,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), #endif }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Vijai Kumar K Add support for emulating Shakti reference platform based on C-class running on arty-100T board. https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis Message-id: 20210401181457.73039-3-vijai@behindbytes.com Signed-off-by: Alistair Francis --- default-configs/devices/riscv64-softmmu.mak | 1 + include/hw/riscv/shakti_c.h | 73 +++++++++ hw/riscv/shakti_c.c | 170 ++++++++++++++++++++ MAINTAINERS | 7 + hw/riscv/Kconfig | 10 ++ hw/riscv/meson.build | 1 + 6 files changed, 262 insertions(+) create mode 100644 include/hw/riscv/shakti_c.h create mode 100644 hw/riscv/shakti_c.c diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/= devices/riscv64-softmmu.mak index d5eec75f05..bc69301fa4 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=3Dy CONFIG_SIFIVE_U=3Dy CONFIG_RISCV_VIRT=3Dy CONFIG_MICROCHIP_PFSOC=3Dy +CONFIG_SHAKTI_C=3Dy diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h new file mode 100644 index 0000000000..8ffc2b0213 --- /dev/null +++ b/include/hw/riscv/shakti_c.h @@ -0,0 +1,73 @@ +/* + * Shakti C-class SoC emulation + * + * Copyright (c) 2021 Vijai Kumar K + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_SHAKTI_H +#define HW_SHAKTI_H + +#include "hw/riscv/riscv_hart.h" +#include "hw/boards.h" + +#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" +#define RISCV_SHAKTI_SOC(obj) \ + OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC) + +typedef struct ShaktiCSoCState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + RISCVHartArrayState cpus; + DeviceState *plic; + MemoryRegion rom; + +} ShaktiCSoCState; + +#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c") +#define RISCV_SHAKTI_MACHINE(obj) \ + OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE) +typedef struct ShaktiCMachineState { + /*< private >*/ + MachineState parent_obj; + + /*< public >*/ + ShaktiCSoCState soc; +} ShaktiCMachineState; + +enum { + SHAKTI_C_ROM, + SHAKTI_C_RAM, + SHAKTI_C_UART, + SHAKTI_C_GPIO, + SHAKTI_C_PLIC, + SHAKTI_C_CLINT, + SHAKTI_C_I2C, +}; + +#define SHAKTI_C_PLIC_HART_CONFIG "MS" +/* Including Interrupt ID 0 (no interrupt)*/ +#define SHAKTI_C_PLIC_NUM_SOURCES 28 +/* Excluding Priority 0 */ +#define SHAKTI_C_PLIC_NUM_PRIORITIES 2 +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04 +#define SHAKTI_C_PLIC_PENDING_BASE 0x1000 +#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000 +#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80 +#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000 +#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000 + +#endif diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c new file mode 100644 index 0000000000..c8205d3f22 --- /dev/null +++ b/hw/riscv/shakti_c.c @@ -0,0 +1,170 @@ +/* + * Shakti C-class SoC emulation + * + * Copyright (c) 2021 Vijai Kumar K + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/riscv/shakti_c.h" +#include "qapi/error.h" +#include "hw/intc/sifive_plic.h" +#include "hw/intc/sifive_clint.h" +#include "sysemu/sysemu.h" +#include "hw/qdev-properties.h" +#include "exec/address-spaces.h" +#include "hw/riscv/boot.h" + + +static const struct MemmapEntry { + hwaddr base; + hwaddr size; +} shakti_c_memmap[] =3D { + [SHAKTI_C_ROM] =3D { 0x00001000, 0x2000 }, + [SHAKTI_C_RAM] =3D { 0x80000000, 0x0 }, + [SHAKTI_C_UART] =3D { 0x00011300, 0x00040 }, + [SHAKTI_C_GPIO] =3D { 0x020d0000, 0x00100 }, + [SHAKTI_C_PLIC] =3D { 0x0c000000, 0x20000 }, + [SHAKTI_C_CLINT] =3D { 0x02000000, 0xc0000 }, + [SHAKTI_C_I2C] =3D { 0x20c00000, 0x00100 }, +}; + +static void shakti_c_machine_state_init(MachineState *mstate) +{ + ShaktiCMachineState *sms =3D RISCV_SHAKTI_MACHINE(mstate); + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); + + /* Allow only Shakti C CPU for this platform */ + if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) !=3D 0) { + error_report("This board can only be used with Shakti C CPU"); + exit(1); + } + + /* Initialize SoC */ + object_initialize_child(OBJECT(mstate), "soc", &sms->soc, + TYPE_RISCV_SHAKTI_SOC); + qdev_realize(DEVICE(&sms->soc), NULL, &error_abort); + + /* register RAM */ + memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram", + mstate->ram_size, &error_fatal); + memory_region_add_subregion(system_memory, + shakti_c_memmap[SHAKTI_C_RAM].base, + main_mem); + + /* ROM reset vector */ + riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus, + shakti_c_memmap[SHAKTI_C_RAM].base, + shakti_c_memmap[SHAKTI_C_ROM].base, + shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0, + NULL); + riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].ba= se, + NULL); +} + +static void shakti_c_machine_instance_init(Object *obj) +{ +} + +static void shakti_c_machine_class_init(ObjectClass *klass, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(klass); + mc->desc =3D "RISC-V Board compatible with Shakti SDK"; + mc->init =3D shakti_c_machine_state_init; + mc->default_cpu_type =3D TYPE_RISCV_CPU_SHAKTI_C; +} + +static const TypeInfo shakti_c_machine_type_info =3D { + .name =3D TYPE_RISCV_SHAKTI_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D shakti_c_machine_class_init, + .instance_init =3D shakti_c_machine_instance_init, + .instance_size =3D sizeof(ShaktiCMachineState), +}; + +static void shakti_c_machine_type_info_register(void) +{ + type_register_static(&shakti_c_machine_type_info); +} +type_init(shakti_c_machine_type_info_register) + +static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) +{ + ShaktiCSoCState *sss =3D RISCV_SHAKTI_SOC(dev); + MemoryRegion *system_memory =3D get_system_memory(); + + sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort); + + sss->plic =3D sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base, + (char *)SHAKTI_C_PLIC_HART_CONFIG, 0, + SHAKTI_C_PLIC_NUM_SOURCES, + SHAKTI_C_PLIC_NUM_PRIORITIES, + SHAKTI_C_PLIC_PRIORITY_BASE, + SHAKTI_C_PLIC_PENDING_BASE, + SHAKTI_C_PLIC_ENABLE_BASE, + SHAKTI_C_PLIC_ENABLE_STRIDE, + SHAKTI_C_PLIC_CONTEXT_BASE, + SHAKTI_C_PLIC_CONTEXT_STRIDE, + shakti_c_memmap[SHAKTI_C_PLIC].size); + + sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base, + shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + SIFIVE_CLINT_TIMEBASE_FREQ, false); + + /* ROM */ + memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", + shakti_c_memmap[SHAKTI_C_ROM].size, &error_fata= l); + memory_region_add_subregion(system_memory, + shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom); +} + +static void shakti_c_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D shakti_c_soc_state_realize; +} + +static void shakti_c_soc_instance_init(Object *obj) +{ + ShaktiCSoCState *sss =3D RISCV_SHAKTI_SOC(obj); + + object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY= ); + + /* + * CPU type is fixed and we are not supporting passing from commandlin= e yet. + * So let it be in instance_init. When supported should use ms->cpu_ty= pe + * instead of TYPE_RISCV_CPU_SHAKTI_C + */ + object_property_set_str(OBJECT(&sss->cpus), "cpu-type", + TYPE_RISCV_CPU_SHAKTI_C, &error_abort); + object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1, + &error_abort); +} + +static const TypeInfo shakti_c_type_info =3D { + .name =3D TYPE_RISCV_SHAKTI_SOC, + .parent =3D TYPE_DEVICE, + .class_init =3D shakti_c_soc_class_init, + .instance_init =3D shakti_c_soc_instance_init, + .instance_size =3D sizeof(ShaktiCSoCState), +}; + +static void shakti_c_type_info_register(void) +{ + type_register_static(&shakti_c_type_info); +} +type_init(shakti_c_type_info_register) diff --git a/MAINTAINERS b/MAINTAINERS index 6c5b5693a8..1b0386d25c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1394,6 +1394,13 @@ F: include/hw/misc/mchp_pfsoc_dmc.h F: include/hw/misc/mchp_pfsoc_ioscb.h F: include/hw/misc/mchp_pfsoc_sysreg.h =20 +Shakti C class SoC +M: Vijai Kumar K +L: qemu-riscv@nongnu.org +S: Supported +F: hw/riscv/shakti_c.c +F: include/hw/riscv/shakti_c.h + SiFive Machines M: Alistair Francis M: Bin Meng diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 1de18cdcf1..a0225716b5 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -19,6 +19,16 @@ config OPENTITAN select IBEX select UNIMP =20 +config SHAKTI + bool + +config SHAKTI_C + bool + select UNIMP + select SHAKTI + select SIFIVE_CLINT + select SIFIVE_PLIC + config RISCV_VIRT bool imply PCI_DEVICES diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 275c0f7eb7..a97454661c 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -4,6 +4,7 @@ riscv_ss.add(files('numa.c')) riscv_ss.add(files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: 7jlgCWSmFir3iIBmCrySyMlRtt+RGMyfEeK/mKFbpxFQwOpVUjaWDS4GkICvJ77w4lu9ray0y0 EITfEl60ecGcEdCbUTNURAARRpd/JZE7AqdNr0Qt1zthBufBXkg21UOMEt2BRcvr/S/KdXtVKn LH2FAPirLLjobUnQ7wtuBRmef9CZA3w/CswB2Hcz/SE1YawDJ7BdjqR+RgN3r3Wsw0TNUbaNEL LElV2Ku2rqBpG5Tk3l2T3CCigUB0LM0i2Uschl4nj84J3ozimZgZ5q8ELgLnI9ogol9pH85G50 QNI= X-IronPort-AV: E=Sophos;i="5.82,276,1613404800"; d="scan'208";a="278356875" IronPort-SDR: zjHPMgXQFmAaNqoGznx10hMfrQ/w5vp7sXtmptHb0sYQqU0unwa/KludhzbXBqSxCtxhPy+9Of Igtoi2iklEetwtiZcICsPkbXpQjPymhLbR+gwgsaJekU/phsn5Kq/uMnYlH0EosRQzmldPzYRY mrFMAooDiCE6T1A1ag90NOIUUUXg1b8o5Q8AJcBq/Cq5f7yGiaeu6CNKqp4o5FUhN+xPPpRP7w hd1fPv9RS0TKwt4SVElc/fD4iRppYq3ZEp5uQSpLxweL1dyY/Jq3dXXsFCEQhvhPBXfJf5bFEe 4xsom0FTMT1fxwcfHtOFP8FT IronPort-SDR: TEdLzeILbWT4uPde+beMVUZDtTc4ViMTQgsva/IampSZUxq1dQh3HgRVplOp+zzhP+riiKvmE6 xeLVkxyDBh7FSZFqeDoZ8R2KiIZuD0JiwbTQyIcnDvC5clPnd5+spstJXoWg0ucFvk6PKKLCb8 qFnwYYcESEkMoufAOfay8mmNdQtkhQMZx5SEpymMDgKGJHqkFIN3fevlrvZTvHDDNyzmVZK4Ub ZfwYCVzqN4RlLHpjZHXjmjLe5GnwRx9u0GFOlX6RSWjjaxNqX5lda9reAzayW20ykjCTzB2oGx Nbg= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 07/42] hw/char: Add Shakti UART emulation Date: Thu, 6 May 2021 09:22:37 +1000 Message-Id: <20210505232312.4175486-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Vijai Kumar K This is the initial implementation of Shakti UART. Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis Message-id: 20210401181457.73039-4-vijai@behindbytes.com Signed-off-by: Alistair Francis --- include/hw/char/shakti_uart.h | 74 ++++++++++++++ hw/char/shakti_uart.c | 185 ++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/char/meson.build | 1 + hw/char/trace-events | 4 + 5 files changed, 266 insertions(+) create mode 100644 include/hw/char/shakti_uart.h create mode 100644 hw/char/shakti_uart.c diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h new file mode 100644 index 0000000000..526c408233 --- /dev/null +++ b/include/hw/char/shakti_uart.h @@ -0,0 +1,74 @@ +/* + * SHAKTI UART + * + * Copyright (c) 2021 Vijai Kumar K + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_SHAKTI_UART_H +#define HW_SHAKTI_UART_H + +#include "hw/sysbus.h" +#include "chardev/char-fe.h" + +#define SHAKTI_UART_BAUD 0x00 +#define SHAKTI_UART_TX 0x04 +#define SHAKTI_UART_RX 0x08 +#define SHAKTI_UART_STATUS 0x0C +#define SHAKTI_UART_DELAY 0x10 +#define SHAKTI_UART_CONTROL 0x14 +#define SHAKTI_UART_INT_EN 0x18 +#define SHAKTI_UART_IQ_CYCLES 0x1C +#define SHAKTI_UART_RX_THRES 0x20 + +#define SHAKTI_UART_STATUS_TX_EMPTY (1 << 0) +#define SHAKTI_UART_STATUS_TX_FULL (1 << 1) +#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2) +#define SHAKTI_UART_STATUS_RX_FULL (1 << 3) +/* 9600 8N1 is the default setting */ +/* Reg value =3D (50000000 Hz)/(16 * 9600)*/ +#define SHAKTI_UART_BAUD_DEFAULT 0x0145 +#define SHAKTI_UART_CONTROL_DEFAULT 0x0100 + +#define TYPE_SHAKTI_UART "shakti-uart" +#define SHAKTI_UART(obj) \ + OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART) + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t uart_baud; + uint32_t uart_tx; + uint32_t uart_rx; + uint32_t uart_status; + uint32_t uart_delay; + uint32_t uart_control; + uint32_t uart_interrupt; + uint32_t uart_iq_cycles; + uint32_t uart_rx_threshold; + + CharBackend chr; +} ShaktiUartState; + +#endif /* HW_SHAKTI_UART_H */ diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c new file mode 100644 index 0000000000..6870821325 --- /dev/null +++ b/hw/char/shakti_uart.c @@ -0,0 +1,185 @@ +/* + * SHAKTI UART + * + * Copyright (c) 2021 Vijai Kumar K + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/char/shakti_uart.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "qemu/log.h" + +static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size) +{ + ShaktiUartState *s =3D opaque; + + switch (addr) { + case SHAKTI_UART_BAUD: + return s->uart_baud; + case SHAKTI_UART_RX: + qemu_chr_fe_accept_input(&s->chr); + s->uart_status &=3D ~SHAKTI_UART_STATUS_RX_NOT_EMPTY; + return s->uart_rx; + case SHAKTI_UART_STATUS: + return s->uart_status; + case SHAKTI_UART_DELAY: + return s->uart_delay; + case SHAKTI_UART_CONTROL: + return s->uart_control; + case SHAKTI_UART_INT_EN: + return s->uart_interrupt; + case SHAKTI_UART_IQ_CYCLES: + return s->uart_iq_cycles; + case SHAKTI_UART_RX_THRES: + return s->uart_rx_threshold; + default: + /* Also handles TX REG which is write only */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } + + return 0; +} + +static void shakti_uart_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + ShaktiUartState *s =3D opaque; + uint32_t value =3D data; + uint8_t ch; + + switch (addr) { + case SHAKTI_UART_BAUD: + s->uart_baud =3D value; + break; + case SHAKTI_UART_TX: + ch =3D value; + qemu_chr_fe_write_all(&s->chr, &ch, 1); + s->uart_status &=3D ~SHAKTI_UART_STATUS_TX_FULL; + break; + case SHAKTI_UART_STATUS: + s->uart_status =3D value; + break; + case SHAKTI_UART_DELAY: + s->uart_delay =3D value; + break; + case SHAKTI_UART_CONTROL: + s->uart_control =3D value; + break; + case SHAKTI_UART_INT_EN: + s->uart_interrupt =3D value; + break; + case SHAKTI_UART_IQ_CYCLES: + s->uart_iq_cycles =3D value; + break; + case SHAKTI_UART_RX_THRES: + s->uart_rx_threshold =3D value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static const MemoryRegionOps shakti_uart_ops =3D { + .read =3D shakti_uart_read, + .write =3D shakti_uart_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D {.min_access_size =3D 1, .max_access_size =3D 4}, + .valid =3D {.min_access_size =3D 1, .max_access_size =3D 4}, +}; + +static void shakti_uart_reset(DeviceState *dev) +{ + ShaktiUartState *s =3D SHAKTI_UART(dev); + + s->uart_baud =3D SHAKTI_UART_BAUD_DEFAULT; + s->uart_tx =3D 0x0; + s->uart_rx =3D 0x0; + s->uart_status =3D 0x0000; + s->uart_delay =3D 0x0000; + s->uart_control =3D SHAKTI_UART_CONTROL_DEFAULT; + s->uart_interrupt =3D 0x0000; + s->uart_iq_cycles =3D 0x00; + s->uart_rx_threshold =3D 0x00; +} + +static int shakti_uart_can_receive(void *opaque) +{ + ShaktiUartState *s =3D opaque; + + return !(s->uart_status & SHAKTI_UART_STATUS_RX_NOT_EMPTY); +} + +static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size) +{ + ShaktiUartState *s =3D opaque; + + s->uart_rx =3D *buf; + s->uart_status |=3D SHAKTI_UART_STATUS_RX_NOT_EMPTY; +} + +static void shakti_uart_realize(DeviceState *dev, Error **errp) +{ + ShaktiUartState *sus =3D SHAKTI_UART(dev); + qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive, + shakti_uart_receive, NULL, NULL, sus, NULL, t= rue); +} + +static void shakti_uart_instance_init(Object *obj) +{ + ShaktiUartState *sus =3D SHAKTI_UART(obj); + memory_region_init_io(&sus->mmio, + obj, + &shakti_uart_ops, + sus, + TYPE_SHAKTI_UART, + 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio); +} + +static Property shakti_uart_properties[] =3D { + DEFINE_PROP_CHR("chardev", ShaktiUartState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void shakti_uart_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->reset =3D shakti_uart_reset; + dc->realize =3D shakti_uart_realize; + device_class_set_props(dc, shakti_uart_properties); +} + +static const TypeInfo shakti_uart_info =3D { + .name =3D TYPE_SHAKTI_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(ShaktiUartState), + .class_init =3D shakti_uart_class_init, + .instance_init =3D shakti_uart_instance_init, +}; + +static void shakti_uart_register_types(void) +{ + type_register_static(&shakti_uart_info); +} +type_init(shakti_uart_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 1b0386d25c..446c776a7f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1399,7 +1399,9 @@ M: Vijai Kumar K L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/shakti_c.c +F: hw/char/shakti_uart.c F: include/hw/riscv/shakti_c.h +F: include/hw/char/shakti_uart.h =20 SiFive Machines M: Alistair Francis diff --git a/hw/char/meson.build b/hw/char/meson.build index da5bb8b762..014833dded 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -19,6 +19,7 @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('ser= ial.c')) softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c')) softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c')) softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci= -multi.c')) +softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c')) softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-consol= e.c')) softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c')) diff --git a/hw/char/trace-events b/hw/char/trace-events index 76d52938ea..c8dcade104 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -90,6 +90,10 @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: pa= rams set to %d 8N1" nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" P= RIx64 " value 0x%" PRIx64 " size %u" nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0= x%" PRIx64 " value 0x%" PRIx64 " size %u" =20 +# shakti_uart.c +shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" = PRIx64 " value 0x%" PRIx16 " size %u" +shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr = 0x%" PRIx64 " value 0x%" PRIx64 " size %u" + # exynos4210_uart.c exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)" exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready" --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: irEnJeJjwTHGA0kyyxCQzJK+OWmtSDHrcEqGy8IVXyL4Q81GMXuCgFztWwX17T8gEs6l6nF0tk 99wm44Ql79h82pCuqFIiwH9AYy5lTiE+6aEEQfCZ+bnbxgP+93RwjRjrk2fgbra5zn/8YXNIK5 Vpg3GVdWQEmDOjGYuhPxPY8G/kn0i+x2Yoofn0L6DKcGskRDbUGXUNDmUYxfT5/tOjFixnkqIa OyhlXcJLUkJ+zA7KuqT++SZ8pHoGL3SRGBgxzPvW9a4g+3SmZmeCBmhvhVt21lcJNNNPCHN8TP NJo= X-IronPort-AV: E=Sophos;i="5.82,276,1613404800"; d="scan'208";a="278356888" IronPort-SDR: 92pl+HvCm234UtbeupNkitxxvL9bDCOBnRYxRS1w0GWgnwbqmJBh0lY78/9GzVJ4qNIfeuoxbl WK+iLpRNCB3nMQWbejSZGgfxw8tGglMTlnm2g4CniQzQaJ1ufmTzCQYeEwwhqDlPgtG9d5/IYa qgtIRdD4d55ufLPzvJJbQAHKIuowVwVdvfkVgN8A7xWDGFUHOGErVTSAg2D+EYGWM8/U84Ytr6 iBKR9RCEnt0Yzr57q+4h4Mnh4qRxnjblfcbDKXWtND4MQsJUqAwgzkZIIZDmNgQZMLGMXKKzZo 4/AfvDvbZvVK+ezymwqfLAKt IronPort-SDR: uTq2waVbTyIfMlYOhIYfKUlv3Nf8vQTGE0XZRSSTzukk5GB7f3ej0w4t0ee/nTDU4w3zxEX3g+ LD5T7ZjAsfGqpusvWRGk7zg1lYKgswMee0EX9gJytuT8C0msO5ghCX0aYZxkBXRwoz8a+hf3gd k+aWiiaQ0V2ZWHWshuUhKsrUtWp1FaajrBsesdimxuN9DZmAHs55xBwHbma4fg2KO2YwUQxjXR xmEwgT1cZ9OL/5hr8aoxBXbxzoabs7GQXeAhqHHHtNZ58O23Iqu0Drz1PXKE4hnM1s33o9wjKr Tek= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform Date: Thu, 6 May 2021 09:22:38 +1000 Message-Id: <20210505232312.4175486-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Vijai Kumar K Connect one shakti uart to the shakti_c machine. Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis Message-id: 20210401181457.73039-5-vijai@behindbytes.com Signed-off-by: Alistair Francis --- include/hw/riscv/shakti_c.h | 2 ++ hw/riscv/shakti_c.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h index 8ffc2b0213..50a2b79086 100644 --- a/include/hw/riscv/shakti_c.h +++ b/include/hw/riscv/shakti_c.h @@ -21,6 +21,7 @@ =20 #include "hw/riscv/riscv_hart.h" #include "hw/boards.h" +#include "hw/char/shakti_uart.h" =20 #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" #define RISCV_SHAKTI_SOC(obj) \ @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState { /*< public >*/ RISCVHartArrayState cpus; DeviceState *plic; + ShaktiUartState uart; MemoryRegion rom; =20 } ShaktiCSoCState; diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index c8205d3f22..e207fa83dd 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -125,6 +125,13 @@ static void shakti_c_soc_state_realize(DeviceState *de= v, Error **errp) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); =20 + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, + shakti_c_memmap[SHAKTI_C_UART].base); + /* ROM */ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", shakti_c_memmap[SHAKTI_C_ROM].size, &error_fata= l); @@ -143,6 +150,7 @@ static void shakti_c_soc_instance_init(Object *obj) ShaktiCSoCState *sss =3D RISCV_SHAKTI_SOC(obj); =20 object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY= ); + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); =20 /* * CPU type is fixed and we are not supporting passing from commandlin= e yet. --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="278356910" IronPort-SDR: APBJFZqRTc8pj0MUblYSuV9OSzmay7Nelm+c32YIcrI9/fdO1NuE9D5HjdkfBB0+O65+mTaDG3 4tFhHdsgPgNm0mHVW+mkXlH84T7o20ax+nfr4oMpknPJU05zIEokB+Ognx+AgyKB49n3d9+NGE XoGXjibvNGXlq1yomnsUh3GFihH+iQLb8CpK3gJYURsJBVbW761DkWkcHPsY00RUbXyYN2JHg6 nybwboQlEtRiu3JRmXrISGY3WJKFCv7/YJS9XYfbL1HLqSk2f+73cL2KgI1egVm1E1kbTLjqXf aP2SO0q0yWzGAezNjdEOTko3 IronPort-SDR: 0yGPdBqQItVTsIgDP5XZjGdZdzKyWk/WdtQadCxWqLuCdN36cxjDrlU3KIYWrqJwIvG4NvweqN PlKmWs9NGICjUNuxbN+rar1BPgM29iq/81k4AMMC+e0W2hW8ujZF6Ch5AfI9NBboyeUjKUCaaj AgEftV6qxVVI39xTf8j2O+B7+0C5NOVCy4SnqpcxlaEUwW4qN2KynjZnjGdcILEUXjMTEXnBwE g/OXVfKUdDJXIRMHOrVXoegHAQRU2KcJHK491ywLHt/disDxq08r2ELD2OwBM0PyOPt4Z32kKw LyI= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum Date: Thu, 6 May 2021 09:22:39 +1000 Message-Id: <20210505232312.4175486-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistai= r.francis@wdc.com --- target/riscv/cpu_bits.h | 44 ++++++++++++++++++++------------------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 4 ++-- 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b42dd4f8d8..8549d77b4f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -504,27 +504,29 @@ #define DEFAULT_RSTVEC 0x1000 =20 /* Exception causes */ -#define EXCP_NONE -1 /* sentinel value */ -#define RISCV_EXCP_INST_ADDR_MIS 0x0 -#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 -#define RISCV_EXCP_ILLEGAL_INST 0x2 -#define RISCV_EXCP_BREAKPOINT 0x3 -#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 -#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 -#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 -#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 -#define RISCV_EXCP_U_ECALL 0x8 -#define RISCV_EXCP_S_ECALL 0x9 -#define RISCV_EXCP_VS_ECALL 0xa -#define RISCV_EXCP_M_ECALL 0xb -#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0= */ -#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0= */ -#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0= */ -#define RISCV_EXCP_SEMIHOST 0x10 -#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 -#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 -#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 -#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 +typedef enum RISCVException { + RISCV_EXCP_NONE =3D -1, /* sentinel value */ + RISCV_EXCP_INST_ADDR_MIS =3D 0x0, + RISCV_EXCP_INST_ACCESS_FAULT =3D 0x1, + RISCV_EXCP_ILLEGAL_INST =3D 0x2, + RISCV_EXCP_BREAKPOINT =3D 0x3, + RISCV_EXCP_LOAD_ADDR_MIS =3D 0x4, + RISCV_EXCP_LOAD_ACCESS_FAULT =3D 0x5, + RISCV_EXCP_STORE_AMO_ADDR_MIS =3D 0x6, + RISCV_EXCP_STORE_AMO_ACCESS_FAULT =3D 0x7, + RISCV_EXCP_U_ECALL =3D 0x8, + RISCV_EXCP_S_ECALL =3D 0x9, + RISCV_EXCP_VS_ECALL =3D 0xa, + RISCV_EXCP_M_ECALL =3D 0xb, + RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ + RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ + RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_SEMIHOST =3D 0x10, + RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, + RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT =3D 0x15, + RISCV_EXCP_VIRT_INSTRUCTION_FAULT =3D 0x16, + RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT =3D 0x17, +} RISCVException; =20 #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6842626c69..e530df9385 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -358,7 +358,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->pc =3D env->resetvec; env->two_stage_lookup =3D false; #endif - cs->exception_index =3D EXCP_NONE; + cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 503c2559f8..99cc388db9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -72,7 +72,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) if (irqs) { return ctz64(irqs); /* since non-zero */ } else { - return EXCP_NONE; /* indicates no pending interrupt */ + return RISCV_EXCP_NONE; /* indicates no pending interrupt */ } } #endif @@ -1069,5 +1069,5 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 env->two_stage_lookup =3D false; #endif - cs->exception_index =3D EXCP_NONE; /* mark handled to qemu */ + cs->exception_index =3D RISCV_EXCP_NONE; /* mark handled to qemu */ } --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620257909; cv=none; d=zohomail.com; s=zohoarc; b=b3Yq+2d6IC3f3T5uwrvfYtNs0DXTXtiYkNmwmVnBhWGCa0pUqTamgWW1gftlYWpeSkHaKpHkn0OhRyXNJp0rouxSvExOurEzq44GkKi9787JBI3xYrztCI7Iz3dsJ8qEY8OaAJLA35mTgHGTuHb8GpXmC1mSgkim1/asEt1hL7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620257909; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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IronPort-SDR: TiLWHvZDUAd0Cw7GX6LjydJHbMvdRUmIceq24GkBjptii5PYYlZyHD1euvb6vrdGt2J3GIiLeh VjWIUXukvLsWIJZpjgB5FgJ6CE+S3PpqNtDe5Pzgy/MRySFRHLIl7KYglZ62oFWF+rHTVJRIJB iqEQ9NaK4dTGPIhUA2WbPqKeagtYq8T3DSUVgI0Ln0aFgyG/ahrUjJ2gRJE+tJM5LyvKwsZDn7 KAj2jJmABowPzM/7pFySXJ6yS9grVF84218GXzYZ26kLKYOXchPOEyKsIkZ8/6FKc/fKuhWaFy Ses= X-IronPort-AV: E=Sophos;i="5.82,276,1613404800"; d="scan'208";a="278356925" IronPort-SDR: gI8o1SILEGhjBIygLbBqzyZG3Y/OGvu19ZRsF6Ad+UBhFwdEume1QzK7AUwK+Fv/jpspz52A6B MaSahF3QCVNy9LZjDGJ3KOLUdxXZBetL017oJp90+h3xUQyNt5nEyLvoJkARrHwsli7iZjoZG+ Ym6E+Ep2ecaIJCjJR+0NP2zIvqoSQS7uKHISgjEaFcgSflAQDr2uPcC0Y3Q1wleQUsWDOTMQKp 7iBO9F7p8gobCuyo9OoEAQf4gj/eKSz9k+8Y2IJlU1UgrPA1RsO8ZAlX2g/teREKpVY/WRFrJ7 zTtF1I9Ml02N+RkoA3tFX4Dt IronPort-SDR: CF0mkNEDDP30N8g4xJ214P9pc0BZcdIn+w8L1VuS4E5KxRC2sWUpGgls/EuLsu2Uad7QeGKB2I PR/ycqXO0/TJInbSDmbjcaD8qxDkV+cr+mFWXuRK+Yh61vGzbYAuhPjKEIdfXKugghKxkX/8Lp DfkqE+tY28W6IGKbja/zh5LJoxhyggeUS/d6NFpgcqjN+p5EtbFqjnTNSLdKcn6twMD+tg53MI 4SE7n2bVIfUSRzZMhMmIyvZWXNken/kP959EBDqS0BXMjZvR+XnTYoedw6OjxGEwMzRswUVpkR wIs= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates Date: Thu, 6 May 2021 09:22:40 +1000 Message-Id: <20210505232312.4175486-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: 187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistai= r.francis@wdc.com --- target/riscv/cpu.h | 3 +- target/riscv/csr.c | 80 +++++++++++++++++++++++++--------------------- 2 files changed, 46 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8079da8fa8..1dd42a6bc1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -472,7 +472,8 @@ static inline target_ulong riscv_csr_read(CPURISCVState= *env, int csrno) return val; } =20 -typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); +typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, + int csrno); typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, target_ulong *ret_value); typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index de7427d8f8..1938bdca7d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -35,29 +35,29 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops) } =20 /* Predicates */ -static int fs(CPURISCVState *env, int csrno) +static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) /* loose check condition for fcsr in vector extension */ if ((csrno =3D=3D CSR_FCSR) && (env->misa & RVV)) { - return 0; + return RISCV_EXCP_NONE; } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif - return 0; + return RISCV_EXCP_NONE; } =20 -static int vs(CPURISCVState *env, int csrno) +static RISCVException vs(CPURISCVState *env, int csrno) { if (env->misa & RVV) { - return 0; + return RISCV_EXCP_NONE; } - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 -static int ctr(CPURISCVState *env, int csrno) +static RISCVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); @@ -65,7 +65,7 @@ static int ctr(CPURISCVState *env, int csrno) =20 if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 if (riscv_cpu_virt_enabled(env)) { @@ -73,25 +73,25 @@ static int ctr(CPURISCVState *env, int csrno) case CSR_CYCLE: if (!get_field(env->hcounteren, HCOUNTEREN_CY) && get_field(env->mcounteren, HCOUNTEREN_CY)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_TIME: if (!get_field(env->hcounteren, HCOUNTEREN_TM) && get_field(env->mcounteren, HCOUNTEREN_TM)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_INSTRET: if (!get_field(env->hcounteren, HCOUNTEREN_IR) && get_field(env->mcounteren, HCOUNTEREN_IR)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)= ) && get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))= ) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; } @@ -100,93 +100,101 @@ static int ctr(CPURISCVState *env, int csrno) case CSR_CYCLEH: if (!get_field(env->hcounteren, HCOUNTEREN_CY) && get_field(env->mcounteren, HCOUNTEREN_CY)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_TIMEH: if (!get_field(env->hcounteren, HCOUNTEREN_TM) && get_field(env->mcounteren, HCOUNTEREN_TM)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_INSTRETH: if (!get_field(env->hcounteren, HCOUNTEREN_IR) && get_field(env->mcounteren, HCOUNTEREN_IR)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNT= ER3H)) && get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTE= R3H))) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; } } } #endif - return 0; + return RISCV_EXCP_NONE; } =20 -static int ctr32(CPURISCVState *env, int csrno) +static RISCVException ctr32(CPURISCVState *env, int csrno) { if (!riscv_cpu_is_32bit(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 return ctr(env, csrno); } =20 #if !defined(CONFIG_USER_ONLY) -static int any(CPURISCVState *env, int csrno) +static RISCVException any(CPURISCVState *env, int csrno) { - return 0; + return RISCV_EXCP_NONE; } =20 -static int any32(CPURISCVState *env, int csrno) +static RISCVException any32(CPURISCVState *env, int csrno) { if (!riscv_cpu_is_32bit(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 return any(env, csrno); =20 } =20 -static int smode(CPURISCVState *env, int csrno) +static RISCVException smode(CPURISCVState *env, int csrno) { - return -!riscv_has_ext(env, RVS); + if (riscv_has_ext(env, RVS)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; } =20 -static int hmode(CPURISCVState *env, int csrno) +static RISCVException hmode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) { /* Hypervisor extension is supported */ if ((env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || env->priv =3D=3D PRV_M) { - return 0; + return RISCV_EXCP_NONE; } else { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } =20 - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 -static int hmode32(CPURISCVState *env, int csrno) +static RISCVException hmode32(CPURISCVState *env, int csrno) { if (!riscv_cpu_is_32bit(env)) { - return 0; + return RISCV_EXCP_NONE; } =20 return hmode(env, csrno); =20 } =20 -static int pmp(CPURISCVState *env, int csrno) +static RISCVException pmp(CPURISCVState *env, int csrno) { - return -!riscv_feature(env, RISCV_FEATURE_PMP); + if (riscv_feature(env, RISCV_FEATURE_PMP)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; } #endif =20 @@ -1293,8 +1301,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, return -RISCV_EXCP_ILLEGAL_INST; } ret =3D csr_ops[csrno].predicate(env, csrno); - if (ret < 0) { - return ret; + if (ret !=3D RISCV_EXCP_NONE) { + return -ret; } =20 /* execute combined read/write operation if it exists */ --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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d="scan'208";a="278356943" IronPort-SDR: RU5bS2cJVNsUM8iw9T1b3U8wDJ8XAOdJKQJZ3mYN7W3uF/DlDHrd+WWRFXwoM+cxApWERYISrw G10+PqX+5T7JnKKEgDR3wDi2zCenwp5Iu/kjTlUAsKSjpwmFH1GG/UXP/EaQGyY/S/1bzvPQhn tC4daZRgpNe4T7NLooI2rKg/bHheHIZbxKTaODhZt922P0xFXfL58dMdqPo2iVLMLXKqwzc9QN qOu7vyS9DjyZAD5bCEkZuJotZZf49KhX/fz1gD7tApGNcob5EMKiMlebebJx+VRDmNFVtRlOe5 ge6Du4wgSjfbv6dP8OYlD5hO IronPort-SDR: nOp+PNJ+mYZd/wJscY2UAs8SD4tDSOK0tLQfuU+18iGyPy3VMlphVpwRLAaddfFx37O7FGtaCl nj+bQfpQ+jo2tvBbBcYsZjkLBo6oWu+WrU5es0OfpJrz5/m+KH6/+WMNcbqjrTn6B1GeZ1LkcW yWLZx/C58niQalALf0l7y/nnGQqT7jFpfsovhBZkdnE1IAqpCm2W5wr5HUvKR9zaECJTzkhWMd vSHIpBO70bWFBFnoG87LNIygQaX4Vgxppn90XWzKIDLQjqwunbcw+q5ewFiAn1YQ50wd/sKq6j Nmc= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions Date: Thu, 6 May 2021 09:22:41 +1000 Message-Id: <20210505232312.4175486-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistai= r.francis@wdc.com --- target/riscv/csr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1938bdca7d..6a39c4aa96 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -181,7 +181,11 @@ static RISCVException hmode(CPURISCVState *env, int cs= rno) static RISCVException hmode32(CPURISCVState *env, int csrno) { if (!riscv_cpu_is_32bit(env)) { - return RISCV_EXCP_NONE; + if (riscv_cpu_virt_enabled(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } else { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } } =20 return hmode(env, csrno); --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620258076; cv=none; d=zohomail.com; s=zohoarc; b=lqAfYVApQdl0c5f3EOSo7Ubuf6M8vxO2jc2oAkGHQNmMDsW7zdgfGjbV2mWfej6yT8QN+lYS5b5XZJ/maRrh0ZeTkBsAoZm22T9/20UWs7tEQ0GWfABAMrLUZuBcSYlc7CoFPpo5ruHsFG+sTGgLfHBvLRN0mFWNoJy1PYtuRd8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620258076; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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IronPort-SDR: rYPBol1V6Oh8X+2VU58Nd9x/+xs2v//CFxBVyM5ykpnBODxdBDVzCgQ+PqWbY8Ct09s8yhB3Dw opR7PsJsjXJBRTfpwCsU9U6m59p/BIWidDOe8l+hEm9ivbBNMa2Rjh2QrgJZhBi9qGoEg772ug kWJoGjB3H2c++cziVLB3WXenUoWlpBoqJSft/encZyIiLj37Dmw8YDomOdjceOeCYnhTLEFDSL oMg1b/P70wqISrEwv1tpMPAwywS4eAr6d9AIbIuZSdUAXjozATaeH324n8yxpXCmwZqK394AII VOw= X-IronPort-AV: E=Sophos;i="5.82,276,1613404800"; d="scan'208";a="166585895" IronPort-SDR: JiZn//IDRWAT3w7DRe5Pue0nqPqlPMfBHsqYqmXZKWYu0v/tWpCgG+pCKtj0b13eiJsKd9ruVG vHcQABSfDBR8o0ANICVkoWgDh6koA+bMzBtvRQkCkk74OwXbI/yg753OGGfy/JQgC+djMP3z/x GMfEybo3b7qNh1pOl526Ll4yKgzijsW03do8vI+k5N87NTXn5ddKXd/xZIqi5/YZdfmZkIeW2k en81bOuJnYRkwi7WKm7U9LeENw1BC/FLEqo31tw1bkW0OC8Y4R2t2uhC1ifQMv8CxjvxjBD0P8 1xlHBVZDFzlPrW4H16N4jHdj IronPort-SDR: xOB0KbicmY42XuOR5iHqCbEyAePvQJH+jn9EXB+aMOGiljBeve1oyyhMW3H2Kb8LWvgnF5WZ37 pexRqbOnasylQ0u1DCTFSZowvyqyu3qyZwht+xx0xwZ8r2puxS33IjQMgVCNHp2fQA1TMyWVqx E8j+xK7sKKVBFylwxZ7lhpCjKiZzgervi6cxciEItiW5RW/Yf3ZqED6otcIhMvaMeSr0PI2TSK EeU53xUeZ0Rmye0BmJvgTW5IfJcGkrV/WvNQTwWdBzNshW/TKII+Rss0VaEOnERYyFytwGf27D g4k= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations Date: Thu, 6 May 2021 09:22:42 +1000 Message-Id: <20210505232312.4175486-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: 8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistai= r.francis@wdc.com --- target/riscv/cpu.h | 14 +- target/riscv/csr.c | 629 +++++++++++++++++++++++++++------------------ 2 files changed, 382 insertions(+), 261 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1dd42a6bc1..a7b8876ea0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,12 +474,14 @@ static inline target_ulong riscv_csr_read(CPURISCVSta= te *env, int csrno) =20 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); -typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value); -typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, - target_ulong new_value); -typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value, target_ulong new_value, target_ulong write_ma= sk); +typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value); +typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, + target_ulong new_value); +typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask); =20 typedef struct { const char *name; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6a39c4aa96..f67eaf4042 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -203,57 +203,62 @@ static RISCVException pmp(CPURISCVState *env, int csr= no) #endif =20 /* User Floating-Point CSRs */ -static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_fflags(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D riscv_cpu_get_fflags(env); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_fflags(CPURISCVState *env, int csrno, + target_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_frm(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D env->frm; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_frm(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_frm(CPURISCVState *env, int csrno, + target_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D val & (FSR_RD >> FSR_RD_SHIFT); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_fcsr(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) @@ -262,14 +267,15 @@ static int read_fcsr(CPURISCVState *env, int csrno, t= arget_ulong *val) *val |=3D (env->vxrm << FSR_VXRM_SHIFT) | (env->vxsat << FSR_VXSAT_SHIFT); } - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_fcsr(CPURISCVState *env, int csrno, + target_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -279,59 +285,68 @@ static int write_fcsr(CPURISCVState *env, int csrno, = target_ulong val) env->vxsat =3D (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; } riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vtype(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vtype; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vl(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vl(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vl; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vxrm(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vxrm; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vxrm(CPURISCVState *env, int csrno, + target_ulong val) { env->vxrm =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vxsat(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vxsat; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vxsat(CPURISCVState *env, int csrno, + target_ulong val) { env->vxsat =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vstart(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vstart; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vstart(CPURISCVState *env, int csrno, + target_ulong val) { env->vstart =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 /* User Timers and Counters */ -static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_instret(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { @@ -342,10 +357,11 @@ static int read_instret(CPURISCVState *env, int csrno= , target_ulong *val) #else *val =3D cpu_get_host_ticks(); #endif - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_instreth(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { @@ -356,46 +372,50 @@ static int read_instreth(CPURISCVState *env, int csrn= o, target_ulong *val) #else *val =3D cpu_get_host_ticks() >> 32; #endif - return 0; + return RISCV_EXCP_NONE; } =20 #if defined(CONFIG_USER_ONLY) -static int read_time(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_time(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D cpu_get_host_ticks(); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_timeh(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D cpu_get_host_ticks() >> 32; - return 0; + return RISCV_EXCP_NONE; } =20 #else /* CONFIG_USER_ONLY */ =20 -static int read_time(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_time(CPURISCVState *env, int csrno, + target_ulong *val) { uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_timeh(CPURISCVState *env, int csrno, + target_ulong *val) { uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; - return 0; + return RISCV_EXCP_NONE; } =20 /* Machine constants */ @@ -449,22 +469,26 @@ static const char valid_vm_1_10_64[16] =3D { }; =20 /* Machine Information Registers */ -static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_zero(CPURISCVState *env, int csrno, + target_ulong *val) { - return *val =3D 0; + *val =3D 0; + return RISCV_EXCP_NONE; } =20 -static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mhartid(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mhartid; - return 0; + return RISCV_EXCP_NONE; } =20 /* Machine Trap Setup */ -static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mstatus(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mstatus; - return 0; + return RISCV_EXCP_NONE; } =20 static int validate_vm(CPURISCVState *env, target_ulong vm) @@ -476,7 +500,8 @@ static int validate_vm(CPURISCVState *env, target_ulong= vm) } } =20 -static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mstatus(CPURISCVState *env, int csrno, + target_ulong val) { uint64_t mstatus =3D env->mstatus; uint64_t mask =3D 0; @@ -507,16 +532,18 @@ static int write_mstatus(CPURISCVState *env, int csrn= o, target_ulong val) mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); env->mstatus =3D mstatus; =20 - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mstatush(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mstatus >> 32; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mstatush(CPURISCVState *env, int csrno, + target_ulong val) { uint64_t valh =3D (uint64_t)val << 32; uint64_t mask =3D MSTATUS_MPV | MSTATUS_GVA; @@ -527,26 +554,28 @@ static int write_mstatush(CPURISCVState *env, int csr= no, target_ulong val) =20 env->mstatus =3D (env->mstatus & ~mask) | (valh & mask); =20 - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_misa(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->misa; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_misa(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_misa(CPURISCVState *env, int csrno, + target_ulong val) { if (!riscv_feature(env, RISCV_FEATURE_MISA)) { /* drop write to misa */ - return 0; + return RISCV_EXCP_NONE; } =20 /* 'I' or 'E' must be present */ if (!(val & (RVI | RVE))) { /* It is not, drop write to misa */ - return 0; + return RISCV_EXCP_NONE; } =20 /* 'E' excludes all other extensions */ @@ -554,7 +583,7 @@ static int write_misa(CPURISCVState *env, int csrno, ta= rget_ulong val) /* when we support 'E' we can do "val =3D RVE;" however * for now we just drop writes if 'E' is present. */ - return 0; + return RISCV_EXCP_NONE; } =20 /* Mask extensions that are not supported by this hart */ @@ -585,55 +614,63 @@ static int write_misa(CPURISCVState *env, int csrno, = target_ulong val) =20 env->misa =3D val; =20 - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_medeleg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->medeleg; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_medeleg(CPURISCVState *env, int csrno, + target_ulong val) { env->medeleg =3D (env->medeleg & ~delegable_excps) | (val & delegable_= excps); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mideleg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mideleg; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mideleg(CPURISCVState *env, int csrno, + target_ulong val) { env->mideleg =3D (env->mideleg & ~delegable_ints) | (val & delegable_i= nts); if (riscv_has_ext(env, RVH)) { env->mideleg |=3D VS_MODE_INTERRUPTS; } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mie(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mie; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mie(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mie(CPURISCVState *env, int csrno, + target_ulong val) { env->mie =3D (env->mie & ~all_ints) | (val & all_ints); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mtvec(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mtvec; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mtvec(CPURISCVState *env, int csrno, + target_ulong val) { /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ if ((val & 3) < 2) { @@ -641,72 +678,83 @@ static int write_mtvec(CPURISCVState *env, int csrno,= target_ulong val) } else { qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n= "); } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *va= l) +static RISCVException read_mcounteren(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mcounteren; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong va= l) +static RISCVException write_mcounteren(CPURISCVState *env, int csrno, + target_ulong val) { env->mcounteren =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 /* Machine Trap Handling */ -static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mscratch(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mscratch; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mscratch(CPURISCVState *env, int csrno, + target_ulong val) { env->mscratch =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mepc(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mepc; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mepc(CPURISCVState *env, int csrno, + target_ulong val) { env->mepc =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mcause(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mcause; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mcause(CPURISCVState *env, int csrno, + target_ulong val) { env->mcause =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mtval(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mtval; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mtval(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mtval(CPURISCVState *env, int csrno, + target_ulong val) { env->mtval =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RISCVException rmw_mip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_m= ask) { RISCVCPU *cpu =3D env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardw= are */ @@ -723,42 +771,47 @@ static int rmw_mip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, *ret_value =3D old_mip; } =20 - return 0; + return RISCV_EXCP_NONE; } =20 /* Supervisor Trap Setup */ -static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_sstatus(CPURISCVState *env, int csrno, + target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); *val =3D env->mstatus & mask; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_sstatus(CPURISCVState *env, int csrno, + target_ulong val) { target_ulong mask =3D (sstatus_v1_10_mask); target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } =20 -static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vsie(CPURISCVState *env, int csrno, + target_ulong *val) { /* Shift the VS bits to their S bit location in vsie */ *val =3D (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_sie(CPURISCVState *env, int csrno, + target_ulong *val) { if (riscv_cpu_virt_enabled(env)) { read_vsie(env, CSR_VSIE, val); } else { *val =3D env->mie & env->mideleg; } - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vsie(CPURISCVState *env, int csrno, + target_ulong val) { /* Shift the S bits to their VS bit location in mie */ target_ulong newval =3D (env->mie & ~VS_MODE_INTERRUPTS) | @@ -776,16 +829,18 @@ static int write_sie(CPURISCVState *env, int csrno, t= arget_ulong val) write_mie(env, CSR_MIE, newval); } =20 - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_stvec(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->stvec; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_stvec(CPURISCVState *env, int csrno, + target_ulong val) { /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ if ((val & 3) < 2) { @@ -793,72 +848,83 @@ static int write_stvec(CPURISCVState *env, int csrno,= target_ulong val) } else { qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n= "); } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *va= l) +static RISCVException read_scounteren(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->scounteren; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_scounteren(CPURISCVState *env, int csrno, target_ulong va= l) +static RISCVException write_scounteren(CPURISCVState *env, int csrno, + target_ulong val) { env->scounteren =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 /* Supervisor Trap Handling */ -static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_sscratch(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->sscratch; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_sscratch(CPURISCVState *env, int csrno, + target_ulong val) { env->sscratch =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_sepc(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->sepc; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_sepc(CPURISCVState *env, int csrno, + target_ulong val) { env->sepc =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_scause(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->scause; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_scause(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_scause(CPURISCVState *env, int csrno, + target_ulong val) { env->scause =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_stval(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_stval(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->stval; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_stval(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_stval(CPURISCVState *env, int csrno, + target_ulong val) { env->stval =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RISCVException rmw_vsip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_= mask) { /* Shift the S bits to their VS bit location in mip */ int ret =3D rmw_mip(env, 0, ret_value, new_value << 1, @@ -869,8 +935,9 @@ static int rmw_vsip(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, return ret; } =20 -static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RISCVException rmw_sip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_m= ask) { int ret; =20 @@ -886,32 +953,34 @@ static int rmw_sip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, } =20 /* Supervisor Protection and Translation */ -static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_satp(CPURISCVState *env, int csrno, + target_ulong *val) { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { *val =3D 0; - return 0; + return RISCV_EXCP_NONE; } =20 if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } else { *val =3D env->satp; } =20 - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_satp(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_satp(CPURISCVState *env, int csrno, + target_ulong val) { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { - return 0; + return RISCV_EXCP_NONE; } if (validate_vm(env, get_field(val, SATP_MODE)) && ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } else { if ((val ^ env->satp) & SATP_ASID) { tlb_flush(env_cpu(env)); @@ -919,11 +988,12 @@ static int write_satp(CPURISCVState *env, int csrno, = target_ulong val) env->satp =3D val; } } - return 0; + return RISCV_EXCP_NONE; } =20 /* Hypervisor Extensions */ -static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hstatus(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hstatus; if (!riscv_cpu_is_32bit(env)) { @@ -932,10 +1002,11 @@ static int read_hstatus(CPURISCVState *env, int csrn= o, target_ulong *val) } /* We only support little endian */ *val =3D set_field(*val, HSTATUS_VSBE, 0); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hstatus(CPURISCVState *env, int csrno, + target_ulong val) { env->hstatus =3D val; if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) !=3D 2) { @@ -944,35 +1015,40 @@ static int write_hstatus(CPURISCVState *env, int csr= no, target_ulong val) if (get_field(val, HSTATUS_VSBE) !=3D 0) { qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.= "); } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hedeleg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hedeleg; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hedeleg(CPURISCVState *env, int csrno, + target_ulong val) { env->hedeleg =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hideleg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hideleg; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hideleg(CPURISCVState *env, int csrno, + target_ulong val) { env->hideleg =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RISCVException rmw_hvip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_= mask) { int ret =3D rmw_mip(env, 0, ret_value, new_value, write_mask & hvip_writable_mask); @@ -982,8 +1058,9 @@ static int rmw_hvip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, return ret; } =20 -static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RISCVException rmw_hip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_m= ask) { int ret =3D rmw_mip(env, 0, ret_value, new_value, write_mask & hip_writable_mask); @@ -993,103 +1070,119 @@ static int rmw_hip(CPURISCVState *env, int csrno, = target_ulong *ret_value, return ret; } =20 -static int read_hie(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hie(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mie & VS_MODE_INTERRUPTS; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hie(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hie(CPURISCVState *env, int csrno, + target_ulong val) { target_ulong newval =3D (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_M= ODE_INTERRUPTS); return write_mie(env, CSR_MIE, newval); } =20 -static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *va= l) +static RISCVException read_hcounteren(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hcounteren; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong va= l) +static RISCVException write_hcounteren(CPURISCVState *env, int csrno, + target_ulong val) { env->hcounteren =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hgeie(CPURISCVState *env, int csrno, + target_ulong *val) { qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hgeie(CPURISCVState *env, int csrno, + target_ulong val) { qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_htval(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->htval; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_htval(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_htval(CPURISCVState *env, int csrno, + target_ulong val) { env->htval =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_htinst(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->htinst; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_htinst(CPURISCVState *env, int csrno, + target_ulong val) { - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hgeip(CPURISCVState *env, int csrno, + target_ulong *val) { qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hgeip(CPURISCVState *env, int csrno, + target_ulong val) { qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hgatp(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hgatp; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hgatp(CPURISCVState *env, int csrno, + target_ulong val) { env->hgatp =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *va= l) +static RISCVException read_htimedelta(CPURISCVState *env, int csrno, + target_ulong *val) { if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->htimedelta; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong va= l) +static RISCVException write_htimedelta(CPURISCVState *env, int csrno, + target_ulong val) { if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 if (riscv_cpu_is_32bit(env)) { @@ -1097,162 +1190,185 @@ static int write_htimedelta(CPURISCVState *env, i= nt csrno, target_ulong val) } else { env->htimedelta =3D val; } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *v= al) +static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, + target_ulong *val) { if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->htimedelta >> 32; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong v= al) +static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, + target_ulong val) { if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 env->htimedelta =3D deposit64(env->htimedelta, 32, 32, (uint64_t)val); - return 0; + return RISCV_EXCP_NONE; } =20 /* Virtual CSR Registers */ -static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vsstatus(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vsstatus; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vsstatus(CPURISCVState *env, int csrno, + target_ulong val) { uint64_t mask =3D (target_ulong)-1; env->vsstatus =3D (env->vsstatus & ~mask) | (uint64_t)val; - return 0; + return RISCV_EXCP_NONE; } =20 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->vstvec; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vstvec(CPURISCVState *env, int csrno, + target_ulong val) { env->vstvec =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vsscratch(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vsscratch; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vsscratch(CPURISCVState *env, int csrno, + target_ulong val) { env->vsscratch =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vsepc(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vsepc; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vsepc(CPURISCVState *env, int csrno, + target_ulong val) { env->vsepc =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vscause(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vscause; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vscause(CPURISCVState *env, int csrno, + target_ulong val) { env->vscause =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vstval(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vstval; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vstval(CPURISCVState *env, int csrno, + target_ulong val) { env->vstval =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vsatp(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vsatp; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vsatp(CPURISCVState *env, int csrno, + target_ulong val) { env->vsatp =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mtval2(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mtval2; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mtval2(CPURISCVState *env, int csrno, + target_ulong val) { env->mtval2 =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mtinst(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mtinst; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mtinst(CPURISCVState *env, int csrno, + target_ulong val) { env->mtinst =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 /* Physical Memory Protection */ -static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, + target_ulong val) { pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, + target_ulong val) { pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); - return 0; + return RISCV_EXCP_NONE; } =20 #endif @@ -1311,18 +1427,21 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, =20 /* execute combined read/write operation if it exists */ if (csr_ops[csrno].op) { - return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_m= ask); + ret =3D csr_ops[csrno].op(env, csrno, ret_value, new_value, write_= mask); + if (ret !=3D RISCV_EXCP_NONE) { + return -ret; + } + return 0; } =20 /* if no accessor exists then return failure */ if (!csr_ops[csrno].read) { return -RISCV_EXCP_ILLEGAL_INST; } - /* read old value */ ret =3D csr_ops[csrno].read(env, csrno, &old_value); - if (ret < 0) { - return ret; + if (ret !=3D RISCV_EXCP_NONE) { + return -ret; } =20 /* write value if writable and write mask set, otherwise drop writes */ @@ -1330,8 +1449,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, new_value =3D (old_value & ~write_mask) | (new_value & write_mask); if (csr_ops[csrno].write) { ret =3D csr_ops[csrno].write(env, csrno, new_value); - if (ret < 0) { - return ret; + if (ret !=3D RISCV_EXCP_NONE) { + return -ret; } } } --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="166585897" IronPort-SDR: 3n30lTmTGw7q3Ri0/+g+17P9xlICql8/jO/p7P1SoVmve7SmxrINz3PFb7g8c5pAYg72c493zc fmyRKV1t5iHe0xWjo/ZTcPRWcCKgjYBaSKxj0wRvcOFYDaq+wqMuvZRdiJaiJHzroabKE81zaE u34qda3bBAI2bgsqb2tlEUT03qwODcXT/Yj5ZtSJrl+DzXtkVqKIxqbyXicNyEeIbyxZ5+dkWg SgDEWpIPleTLnrwzRWb6P0xA5FJPNXJmtAQwTD3iPdbR1py2+coLB71p4LXzOVfrmcqtE5Qwn2 S0K9/jWf2Ym4hS9Drc6eK61v IronPort-SDR: Jsv+rrN0nA1wVNGuOWH3BxVZfDsIh9PBkOc4YOmfa5WMQDjacu3xrdQcRbDHCYTXwRKZb5XrFc g/EOjCD86oDwJwVYblYA99LQF7XecVBgXaEaPZEmFKU3Fs8lS6cpBYZaBGUZBRWBHRwwm2eCWr BbEBVjvTQ+O8SouFgZHqEvObTMkuMQE7ZA6zdxtelLQ3a7knHiwPTorEGbh0mY4VKpihLjB7aF MSk2BB1MHETGvmlWp1oENIa4W6T/DQixx4rIL5nnuv/UcX489tUhXx5cS+g+dqLh6xFb+RanNX kzo= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access Date: Thu, 6 May 2021 09:22:43 +1000 Message-Id: <20210505232312.4175486-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistai= r.francis@wdc.com --- target/riscv/cpu.h | 11 +++++++---- target/riscv/csr.c | 37 ++++++++++++++++++------------------- target/riscv/gdbstub.c | 8 ++++---- target/riscv/op_helper.c | 18 +++++++++--------- 4 files changed, 38 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a7b8876ea0..842d3ab810 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -454,10 +454,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState= *env, target_ulong *pc, *pflags =3D flags; } =20 -int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask); -int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_val= ue, - target_ulong new_value, target_ulong write_mask); +RISCVException riscv_csrrw(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask= ); +RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask); =20 static inline void riscv_csr_write(CPURISCVState *env, int csrno, target_ulong val) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f67eaf4042..f0a74f0eb8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1382,10 +1382,11 @@ static RISCVException write_pmpaddr(CPURISCVState *= env, int csrno, * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); */ =20 -int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +RISCVException riscv_csrrw(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) { - int ret; + RISCVException ret; target_ulong old_value; RISCVCPU *cpu =3D env_archcpu(env); =20 @@ -1407,41 +1408,37 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, =20 if ((write_mask && read_only) || (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif =20 /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 /* check predicate */ if (!csr_ops[csrno].predicate) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } ret =3D csr_ops[csrno].predicate(env, csrno); if (ret !=3D RISCV_EXCP_NONE) { - return -ret; + return ret; } =20 /* execute combined read/write operation if it exists */ if (csr_ops[csrno].op) { - ret =3D csr_ops[csrno].op(env, csrno, ret_value, new_value, write_= mask); - if (ret !=3D RISCV_EXCP_NONE) { - return -ret; - } - return 0; + return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_m= ask); } =20 /* if no accessor exists then return failure */ if (!csr_ops[csrno].read) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } /* read old value */ ret =3D csr_ops[csrno].read(env, csrno, &old_value); if (ret !=3D RISCV_EXCP_NONE) { - return -ret; + return ret; } =20 /* write value if writable and write mask set, otherwise drop writes */ @@ -1450,7 +1447,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, if (csr_ops[csrno].write) { ret =3D csr_ops[csrno].write(env, csrno, new_value); if (ret !=3D RISCV_EXCP_NONE) { - return -ret; + return ret; } } } @@ -1460,17 +1457,19 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, *ret_value =3D old_value; } =20 - return 0; + return RISCV_EXCP_NONE; } =20 /* * Debugger support. If not in user mode, set env->debugger before the * riscv_csrrw call and clear it after the call. */ -int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_val= ue, - target_ulong new_value, target_ulong write_mask) +RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask) { - int ret; + RISCVException ret; #if !defined(CONFIG_USER_ONLY) env->debugger =3D true; #endif diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5f96b7ea2a..ca78682cf4 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -71,7 +71,7 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArr= ay *buf, int n) */ result =3D riscv_csrrw_debug(env, n - 32, &val, 0, 0); - if (result =3D=3D 0) { + if (result =3D=3D RISCV_EXCP_NONE) { return gdb_get_regl(buf, val); } } @@ -94,7 +94,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t = *mem_buf, int n) */ result =3D riscv_csrrw_debug(env, n - 32, NULL, val, -1); - if (result =3D=3D 0) { + if (result =3D=3D RISCV_EXCP_NONE) { return sizeof(target_ulong); } } @@ -108,7 +108,7 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteA= rray *buf, int n) int result; =20 result =3D riscv_csrrw_debug(env, n, &val, 0, 0); - if (result =3D=3D 0) { + if (result =3D=3D RISCV_EXCP_NONE) { return gdb_get_regl(buf, val); } } @@ -122,7 +122,7 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_= t *mem_buf, int n) int result; =20 result =3D riscv_csrrw_debug(env, n, NULL, val, -1); - if (result =3D=3D 0) { + if (result =3D=3D RISCV_EXCP_NONE) { return sizeof(target_ulong); } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f0bbd73ca5..170b494227 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -41,10 +41,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ul= ong src, target_ulong csr) { target_ulong val =3D 0; - int ret =3D riscv_csrrw(env, csr, &val, src, -1); + RISCVException ret =3D riscv_csrrw(env, csr, &val, src, -1); =20 - if (ret < 0) { - riscv_raise_exception(env, -ret, GETPC()); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); } return val; } @@ -53,10 +53,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ul= ong src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - int ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0); + RISCVException ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src = : 0); =20 - if (ret < 0) { - riscv_raise_exception(env, -ret, GETPC()); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); } return val; } @@ -65,10 +65,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ul= ong src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - int ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0); + RISCVException ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src := 0); =20 - if (ret < 0) { - riscv_raise_exception(env, -ret, GETPC()); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Alistair Francis , alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Update the RISC-V maintainers by removing Sagar and Bastian who haven't been involved recently. Also add Bin who has been helping with reviews. Signed-off-by: Alistair Francis Acked-by: Bin Meng Acked-by: Bastian Koppelmann Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistai= r.francis@wdc.com --- MAINTAINERS | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 446c776a7f..0a2d89ccaa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,9 +295,8 @@ F: tests/acceptance/machine_ppc.py =20 RISC-V TCG CPUs M: Palmer Dabbelt -M: Alistair Francis -M: Sagar Karandikar -M: Bastian Koppelmann +M: Alistair Francis +M: Bin Meng L: qemu-riscv@nongnu.org S: Supported F: target/riscv/ --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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d="scan'208";a="166585909" IronPort-SDR: JmpGMn/QowWMG80vS5h+3lQchmMDQnft9ACQODRh2E91oLIUzUE/cNIFdHWfpJAdnxKi0XfpzC iuOKqEv1QUn6z58Gu3jueOkI7cvvYHoBYQzVUPAOeKSHDH7wKfQHN9QtrfyHqSTGxV1w/3wadn 73rKYSzx5ugGOjy2ZWIki3wU9RZDw3dLsrGConDMYaMtzJzLZtiqN5lu24baE/qxDl9Wx/sfO9 q8ZI99V3dhHanOTvHObhz3cPg3NUUZwNZwrAuLhth4C4GOt7Ocd0W4ZSKWfZfYz1UbANnCklev LV/u2+8NVBDXnURMEcrydXVO IronPort-SDR: gZgJIfhlLWOZWKQGkQulG9HC25/Yw7jq/zXzlaSEmRrCwq4ugipUW8A/vVmJPQw7u09V3bsqZd hlWqgrLV44oJdhl6Q70/8w/nh4+vCBXINjwOVFvZR2fyQwjWhbRgCnxSTy/kGpwPsCGlHo7b7I 7l/MzXoysmyy2AvWAYoGK7XJu6PAl6EUSuyi9dTDyRJw+jFroTCXiClyeqDIZNWk+QE3yWtW5c PFF8I5OZ/+am6tzt7tIFJ0bYIKBhKHG3qKYQdow0+I7/ZhStWwMwnHuQzIufF25n4ORotQlS0Q HiE= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 15/42] hw/opentitan: Update the interrupt layout Date: Thu, 6 May 2021 09:22:45 +1000 Message-Id: <20210505232312.4175486-16-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Update the OpenTitan interrupt layout to match the latest OpenTitan bitstreams. This involves changing the Ibex PLIC memory layout and the UART interrupts. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistai= r.francis@wdc.com --- include/hw/riscv/opentitan.h | 16 ++++++++-------- hw/intc/ibex_plic.c | 20 ++++++++++---------- hw/riscv/opentitan.c | 8 ++++---- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index a5ea3a5e4e..aab9bc9245 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -82,14 +82,14 @@ enum { }; =20 enum { - IBEX_UART_RX_PARITY_ERR_IRQ =3D 0x28, - IBEX_UART_RX_TIMEOUT_IRQ =3D 0x27, - IBEX_UART_RX_BREAK_ERR_IRQ =3D 0x26, - IBEX_UART_RX_FRAME_ERR_IRQ =3D 0x25, - IBEX_UART_RX_OVERFLOW_IRQ =3D 0x24, - IBEX_UART_TX_EMPTY_IRQ =3D 0x23, - IBEX_UART_RX_WATERMARK_IRQ =3D 0x22, - IBEX_UART_TX_WATERMARK_IRQ =3D 0x21, + IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8, + IBEX_UART0_RX_TIMEOUT_IRQ =3D 7, + IBEX_UART0_RX_BREAK_ERR_IRQ =3D 6, + IBEX_UART0_RX_FRAME_ERR_IRQ =3D 5, + IBEX_UART0_RX_OVERFLOW_IRQ =3D 4, + IBEX_UART0_TX_EMPTY_IRQ =3D 3, + IBEX_UART0_RX_WATERMARK_IRQ =3D 2, + IBEX_UART0_TX_WATERMARK_IRQ =3D 1, }; =20 #endif diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index c1b72fcab0..edf76e4f61 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -225,23 +225,23 @@ static void ibex_plic_irq_request(void *opaque, int i= rq, int level) =20 static Property ibex_plic_properties[] =3D { DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1), - DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80), + DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176), =20 DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0), - DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3), + DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6), =20 - DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c), - DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3), + DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18), + DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6), =20 - DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18= ), - DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80), + DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30= ), + DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177), =20 - DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200), - DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3), + DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300), + DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6), =20 - DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x= 20c), + DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x= 318), =20 - DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210), + DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index dc9dea117e..557d73726b 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -148,16 +148,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev= _soc, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].bas= e); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, qdev_get_gpio_in(DEVICE(&s->plic), - IBEX_UART_TX_WATERMARK_IRQ)); + IBEX_UART0_TX_WATERMARK_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 1, qdev_get_gpio_in(DEVICE(&s->plic), - IBEX_UART_RX_WATERMARK_IRQ)); + IBEX_UART0_RX_WATERMARK_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 2, qdev_get_gpio_in(DEVICE(&s->plic), - IBEX_UART_TX_EMPTY_IRQ)); + IBEX_UART0_TX_EMPTY_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 3, qdev_get_gpio_in(DEVICE(&s->plic), - IBEX_UART_RX_OVERFLOW_IRQ)); + IBEX_UART0_RX_OVERFLOW_IRQ)); =20 create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" imply VIRTIO_VGA for the virt machine, this fixes the following error when specifying `-vga virtio` as a command line argument: qemu-system-riscv64: Virtio VGA not available Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 7ac26fafee8bd59d2a0640f3233f8ad1ab270e1e.1617367317.git.alistai= r.francis@wdc.com --- hw/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index a0225716b5..86957ec7b0 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -32,6 +32,7 @@ config SHAKTI_C config RISCV_VIRT bool imply PCI_DEVICES + imply VIRTIO_VGA imply TEST_DEVICES select GOLDFISH_RTC select MSI_NONBROKEN --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org, Jade Fink Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Jade Fink Previously the qemu monitor and gdbstub looked at SUM and refused to perform accesses to user memory if it is off, which was an impediment to debugging. Signed-off-by: Jade Fink Reviewed-by: Alistair Francis Message-id: 20210406113109.1031033-1-qemu@jade.fyi Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 99cc388db9..659ca8a173 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -342,12 +342,14 @@ static int get_physical_address_pmp(CPURISCVState *en= v, int *prot, * @first_stage: Are we in first stage translation? * Second stage is used for hypervisor guest translation * @two_stage: Are we going to perform two stage translation + * @is_debug: Is this access from a debugger or the monitor? */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *prot, target_ulong addr, target_ulong *fault_pte_addr, int access_type, int mmu_idx, - bool first_stage, bool two_stage) + bool first_stage, bool two_stage, + bool is_debug) { /* NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler @@ -416,7 +418,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, widened =3D 2; } /* status.SUM will be ignored if execute on background */ - sum =3D get_field(env->mstatus, MSTATUS_SUM) || use_background; + sum =3D get_field(env->mstatus, MSTATUS_SUM) || use_background || is_d= ebug; switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; @@ -475,7 +477,8 @@ restart: /* Do the second stage translation on the base PTE address. */ int vbase_ret =3D get_physical_address(env, &vbase, &vbase_pro= t, base, NULL, MMU_DATA_LOAD, - mmu_idx, false, true); + mmu_idx, false, true, + is_debug); =20 if (vbase_ret !=3D TRANSLATE_SUCCESS) { if (fault_pte_addr) { @@ -666,13 +669,13 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) int mmu_idx =3D cpu_mmu_index(&cpu->env, false); =20 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, - true, riscv_cpu_virt_enabled(env))) { + true, riscv_cpu_virt_enabled(env), true)) { return -1; } =20 if (riscv_cpu_virt_enabled(env)) { if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, - 0, mmu_idx, false, true)) { + 0, mmu_idx, false, true, true)) { return -1; } } @@ -768,7 +771,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_typ= e, - mmu_idx, true, true); + mmu_idx, true, true, false); =20 /* * A G-stage exception may be triggered during two state lookup. @@ -790,7 +793,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, im_address =3D pa; =20 ret =3D get_physical_address(env, &pa, &prot2, im_address, NUL= L, - access_type, mmu_idx, false, true); + access_type, mmu_idx, false, true, + false); =20 qemu_log_mask(CPU_LOG_MMU, "%s 2nd-stage address=3D%" VADDR_PRIx " ret %d physica= l " @@ -825,7 +829,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, } else { /* Single stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, NULL, - access_type, mmu_idx, true, false); + access_type, mmu_idx, true, false, fals= e); =20 qemu_log_mask(CPU_LOG_MMU, "%s address=3D%" VADDR_PRIx " ret %d physical " --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , Richard Henderson , qemu-devel@nongnu.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right. However, when the predication is ture and a is 0, it should return maximum. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a156573d28..356cef8a09 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2451,7 +2451,7 @@ static inline int8_t ssub8(CPURISCVState *env, int vx= rm, int8_t a, int8_t b) { int8_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT8_MIN) { - res =3D a > 0 ? INT8_MAX : INT8_MIN; + res =3D a >=3D 0 ? INT8_MAX : INT8_MIN; env->vxsat =3D 0x1; } return res; @@ -2461,7 +2461,7 @@ static inline int16_t ssub16(CPURISCVState *env, int = vxrm, int16_t a, int16_t b) { int16_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT16_MIN) { - res =3D a > 0 ? INT16_MAX : INT16_MIN; + res =3D a >=3D 0 ? INT16_MAX : INT16_MIN; env->vxsat =3D 0x1; } return res; @@ -2471,7 +2471,7 @@ static inline int32_t ssub32(CPURISCVState *env, int = vxrm, int32_t a, int32_t b) { int32_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT32_MIN) { - res =3D a > 0 ? INT32_MAX : INT32_MIN; + res =3D a >=3D 0 ? INT32_MAX : INT32_MIN; env->vxsat =3D 0x1; } return res; @@ -2481,7 +2481,7 @@ static inline int64_t ssub64(CPURISCVState *env, int = vxrm, int64_t a, int64_t b) { int64_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT64_MIN) { - res =3D a > 0 ? INT64_MAX : INT64_MIN; + res =3D a >=3D 0 ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , alistair23@gmail.com, Bin Meng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Vijai Kumar K Add documentation for Shakti C reference platform. Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis Message-id: 20210412174248.8668-1-vijai@behindbytes.com Signed-off-by: Bin Meng [ Changes from Bin Meng: - Add missing TOC Message-id: 20210430070534.1487242-1-bmeng.cn@gmail.com ] Signed-off-by: Alistair Francis --- docs/system/riscv/shakti-c.rst | 82 ++++++++++++++++++++++++++++++++++ docs/system/target-riscv.rst | 1 + 2 files changed, 83 insertions(+) create mode 100644 docs/system/riscv/shakti-c.rst diff --git a/docs/system/riscv/shakti-c.rst b/docs/system/riscv/shakti-c.rst new file mode 100644 index 0000000000..a6035d42b0 --- /dev/null +++ b/docs/system/riscv/shakti-c.rst @@ -0,0 +1,82 @@ +Shakti C Reference Platform (``shakti_c``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Shakti C Reference Platform is a reference platform based on arty a7 100t +for the Shakti SoC. + +Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C +is a 64bit RV64GCSUN processor core. + +For more details on Shakti SoC, please see: +https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/board= s/artya7-100t/c-class/README.rst + +For more info on the Shakti C-class core, please see: +https://c-class.readthedocs.io/en/latest/ + +Supported devices +----------------- + +The ``shakti_c`` machine supports the following devices: + + * 1 C-class core + * Core Level Interruptor (CLINT) + * Platform-Level Interrupt Controller (PLIC) + * 1 UART + +Boot options +------------ + +The ``shakti_c`` machine can start using the standard -bios +functionality for loading the baremetal application or opensbi. + +Boot the machine +---------------- + +Shakti SDK +~~~~~~~~~~ +Shakti SDK can be used to generate the baremetal example UART applications. + +.. code-block:: bash + + $ git clone https://gitlab.com/behindbytes/shakti-sdk.git + $ cd shakti-sdk + $ make software PROGRAM=3Dloopback TARGET=3Dartix7_100t + +Binary would be generated in: + software/examples/uart_applns/loopback/output/loopback.shakti + +You could also download the precompiled example applicatons using below +commands. + +.. code-block:: bash + + $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/s= dk/shakti_sdk_qemu.zip + $ unzip shakti_sdk_qemu.zip + +Then we can run the UART example using: + +.. code-block:: bash + + $ qemu-system-riscv64 -M shakti_c -nographic \ + -bios path/to/shakti_sdk_qemu/loopback.shakti + +OpenSBI +~~~~~~~ +We can also run OpenSBI with Test Payload. + +.. code-block:: bash + + $ git clone https://github.com/riscv/opensbi.git -b v0.9 + $ cd opensbi + $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/d= ts/shakti.dtb + $ export CROSS_COMPILE=3Driscv64-unknown-elf- + $ export FW_FDT_PATH=3D./shakti.dtb + $ make PLATFORM=3Dgeneric + +fw_payload.elf would be generated in build/platform/generic/firmware/fw_pa= yload.elf. +Boot it using the below qemu command. + +.. code-block:: bash + + $ qemu-system-riscv64 -M shakti_c -nographic \ + -bios path/to/fw_payload.elf diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 8d5946fbbb..4b3c78382c 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -67,6 +67,7 @@ undocumented; you can get a complete list by running :maxdepth: 1 =20 riscv/microchip-icicle-kit + riscv/shakti-c riscv/sifive_u =20 RISC-V CPU features --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620257584; cv=none; d=zohomail.com; s=zohoarc; b=nXf4ZJXQRUwrNnN9jWHdSWwPQZ0ECSCO18fE/bIowg+zxzxFjTqT0W5NTZIyeHxJlTaGJMGU7oUjm+frozb01d40eRsPUTXVRPCblsWK5m52djQgLqaAavSDs9wNoVlfMIYiwdRxl2ZTL71h6SJjno6TNVJfR9t8V7b4ofjMEwY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620257584; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The RISC-V spec says: if PMP entry i is locked and pmpicfg.A is set to TOR, writes to pmpaddri-1 are ignored. The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which is incorrect. Update the pmp_is_locked() function to not check the supporting fields and instead enforce the lock functionality in the pmpaddr write operation. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistai= r.francis@wdc.com --- target/riscv/pmp.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index cff020122a..a3b253bb15 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -59,16 +59,6 @@ static inline int pmp_is_locked(CPURISCVState *env, uint= 32_t pmp_index) return 0; } =20 - /* In TOR mode, need to check the lock bit of the next pmp - * (if there is a next) - */ - const uint8_t a_field =3D - pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg); - if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) && - (PMP_AMATCH_TOR =3D=3D a_field)) { - return 1; - } - return 0; } =20 @@ -380,7 +370,23 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t ad= dr_index, target_ulong val) { trace_pmpaddr_csr_write(env->mhartid, addr_index, val); + if (addr_index < MAX_RISCV_PMPS) { + /* + * In TOR mode, need to check the lock bit of the next pmp + * (if there is a next). + */ + if (addr_index + 1 < MAX_RISCV_PMPS) { + uint8_t pmp_cfg =3D env->pmp_state.pmp[addr_index + 1].cfg_reg; + + if (pmp_cfg & PMP_LOCK && + PMP_AMATCH_TOR =3D=3D pmp_get_a_field(pmp_cfg)) { + qemu_log_mask(LOG_GUEST_ERROR, + "ignoring pmpaddr write - pmpcfg + 1 locked\= n"); + return; + } + } + if (!pmp_is_locked(env, addr_index)) { env->pmp_state.pmp[addr_index].addr_reg =3D val; pmp_update_rule(env, addr_index); --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620257742; cv=none; d=zohomail.com; s=zohoarc; b=cx/xbrvi2/h6WRNgncJqFLTaMh43Z2R5kwLlchGUgtUCiS5w4GVwNMfL/orvSjGkHN+T8nmIjmOqAT+J0f3lc/znOwQ2o79GjFwUxRBH6l60L/T886kQU/g21i6tlehBC0cJ3lGlhOfDLhWBO5tXk2GNq/X3kkG9928EfGfX/4E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hou Weiying , qemu-devel@nongnu.org, Hongzheng-Li , Alistair Francis , alistair23@gmail.com, Bin Meng , Myriad-Dreamin Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Hou Weiying Use address 0x390 and 0x391 for the ePMP CSRs. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistai= r.francis@wdc.com [ Changes by AF: - Tidy up commit message ] Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8549d77b4f..24d89939a0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -220,6 +220,9 @@ #define CSR_MTINST 0x34a #define CSR_MTVAL2 0x34b =20 +/* Enhanced Physical Memory Protection (ePMP) */ +#define CSR_MSECCFG 0x390 +#define CSR_MSECCFGH 0x391 /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; 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IronPort-SDR: 0342+Ql0viGBf1Vmyxs8KifivaEbdZ9p6+X352G3FVL9ue94iycyUm1ApTpcs+BCbq1VjyvZ0s yrGZPaYCQwWd5HKO0/YWwy1nwjVCf7rN7GD3hjQxQkwXJWIHPxF3iGDYQOUFMtCG5PC51vqmRc FtL0yJq5xL3VKzCpEStwZaLkZGRHp53jZjCqucAuGipmkOfD3OAFcU/B+5rbW5IRaNyRpQKIuf xdHG4+jW3MgT5PMlh7B1ipY0n37RXRZuG9iW+wbMMyKUprw0urrvULk+ILgdo7vC+cxy2Is3LS fJI= X-IronPort-AV: E=Sophos;i="5.82,276,1613404800"; d="scan'208";a="166585947" IronPort-SDR: m1HH+fbSyxzgws8y5f3QZHJknAG71nvNsjVX6biw2eorJNE6/Ir31ezfceHTGoiZQ7AXVopT21 Q99rowVAnbsihmPgbuosyFky+M0P0K6njwmyYQJlOoTxkmdH7WZQfGyUxiihgv5rRnPjZKO86W pTLwQubPEDUpWMW1c+yPlXH8150UT1uzt6ypR2xKxQVpLeMfN9eC3nX8NAUdaHxQYHLrVGPWyM m1XcbpTNl8jwApPj5672J7mM4Sr3mvGI2B1ggp32Lgs0t9L2vFASSViRn1pZNdTJwJLk1ahmyU 3b54rqg/UhOKDTEDojhHLrZ7 IronPort-SDR: YitEQNkWOTV7q0f+yo+F9wybsghWDIvjnrQ1To+MmvkeCET/lZ1gfBnoWPKWfPNJwo6S12l08z f2Cw8gKeQDKd1glRttMIUtE9jsVsuPH+0IHBhtvY8oX6mhqLzqzkHQFUZVW/47fSPsRp0ZJTf0 pizrs92sCUBVoWl+wmJdlw/BeQ9pb6LvTw6FB+L4FPj1W03o3DkRTdZ6wQKjqJVcIFAlKWipMf QukTGRJh2rN8v0da8lFBxjCCczt3oz4MLhbc2z9VvUEjcTTwkTEBX5i/J6aK/QQ7r9YpTttsF/ FZQ= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 22/42] target/riscv: Add the ePMP feature Date: Thu, 6 May 2021 09:22:52 +1000 Message-Id: <20210505232312.4175486-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The spec is avaliable at: https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUz= bvc8 Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 28c8855c80b0388a08c3ae009f5467e2b3960ce0.1618812899.git.alistai= r.francis@wdc.com --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 842d3ab810..13a08b86f6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, + RISCV_FEATURE_EPMP, RISCV_FEATURE_MISA }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hou Weiying , qemu-devel@nongnu.org, Hongzheng-Li , Alistair Francis , alistair23@gmail.com, Bin Meng , Myriad-Dreamin Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Hou Weiying Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistai= r.francis@wdc.com [ Changes by AF: - Rebase on master - Fix build errors - Fix some style issues ] Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 1 + target/riscv/pmp.h | 14 ++++++++++++++ target/riscv/csr.c | 24 ++++++++++++++++++++++++ target/riscv/pmp.c | 34 ++++++++++++++++++++++++++++++++++ target/riscv/trace-events | 3 +++ 5 files changed, 76 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 13a08b86f6..83b315e0b2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -230,6 +230,7 @@ struct CPURISCVState { =20 /* physical memory protection */ pmp_table_t pmp_state; + target_ulong mseccfg; =20 /* machine specific rdtime callback */ uint64_t (*rdtime_fn)(uint32_t); diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index b82a30f0d5..a9a0b363a7 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -36,6 +36,12 @@ typedef enum { PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */ } pmp_am_t; =20 +typedef enum { + MSECCFG_MML =3D 1 << 0, + MSECCFG_MMWP =3D 1 << 1, + MSECCFG_RLB =3D 1 << 2 +} mseccfg_field_t; + typedef struct { target_ulong addr_reg; uint8_t cfg_reg; @@ -55,6 +61,10 @@ typedef struct { void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, target_ulong val); target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); + +void mseccfg_csr_write(CPURISCVState *env, target_ulong val); +target_ulong mseccfg_csr_read(CPURISCVState *env); + void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, target_ulong val); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); @@ -68,4 +78,8 @@ void pmp_update_rule_nums(CPURISCVState *env); uint32_t pmp_get_num_rules(CPURISCVState *env); int pmp_priv_to_page_prot(pmp_priv_t pmp_priv); =20 +#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML) +#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP) +#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB) + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f0a74f0eb8..97ceff718f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -200,6 +200,15 @@ static RISCVException pmp(CPURISCVState *env, int csrn= o) =20 return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException epmp(CPURISCVState *env, int csrno) +{ + if (env->priv =3D=3D PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif =20 /* User Floating-Point CSRs */ @@ -1343,6 +1352,20 @@ static RISCVException write_mtinst(CPURISCVState *en= v, int csrno, } =20 /* Physical Memory Protection */ +static RISCVException read_mseccfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D mseccfg_csr_read(env); + return RISCV_EXCP_NONE; +} + +static RISCVException write_mseccfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + mseccfg_csr_write(env, val); + return RISCV_EXCP_NONE; +} + static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1581,6 +1604,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, writ= e_mtinst }, =20 /* Physical Memory Protection */ + [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg }, [CSR_PMPCFG0] =3D { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] =3D { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index a3b253bb15..e35988eec2 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -419,6 +419,40 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint= 32_t addr_index) return val; } =20 +/* + * Handle a write to a mseccfg CSR + */ +void mseccfg_csr_write(CPURISCVState *env, target_ulong val) +{ + int i; + + trace_mseccfg_csr_write(env->mhartid, val); + + /* RLB cannot be enabled if it's already 0 and if any regions are lock= ed */ + if (!MSECCFG_RLB_ISSET(env)) { + for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + if (pmp_is_locked(env, i)) { + val &=3D ~MSECCFG_RLB; + break; + } + } + } + + /* Sticky bits */ + val |=3D (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); + + env->mseccfg =3D val; +} + +/* + * Handle a read from a mseccfg CSR + */ +target_ulong mseccfg_csr_read(CPURISCVState *env) +{ + trace_mseccfg_csr_read(env->mhartid, env->mseccfg); + return env->mseccfg; +} + /* * Calculate the TLB size if the start address or the end address of * PMP entry is presented in thie TLB page. diff --git a/target/riscv/trace-events b/target/riscv/trace-events index b7e371ee97..49ec4d3b7d 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -6,3 +6,6 @@ pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint6= 4_t val) "hart %" PRI pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart= %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64 pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "har= t %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64 pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "ha= rt %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64 + +mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read m= seccfg, val: 0x%" PRIx64 +mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write= mseccfg, val: 0x%" PRIx64 --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: BfiI9aWGzCyN4BczF/mktbWYWmh9TCeRrm9+V6O3QoDgm+kzMkbO5rDFvumEmDysYEYLUVw4k1 deU7glOqC+ibDrnIIZJrp4qKyfoALvIOOs5f51fVceFSIStfPmRBEcrcUVV4px4FMfLHyNfE2R 2NPwOVOYHONNHQHOeY44nLH/+a/uYe04WPisgMg7xrpTa3hueYPn8SeBrQNODrx3QKqM7jJZs/ 6swUKaL/I86xwAmxcVFMqsssxzpXyWj+KD5I/p3VkC6eCCw0pCs5QAWoZQfrTMTBlFtDibjKm6 I4M= X-IronPort-AV: E=Sophos;i="5.82,276,1613404800"; d="scan'208";a="166585955" IronPort-SDR: cAdPkJfdZQs412JmA17FNJuOm/wziZjAIIsKRTXzi1kfCvt46c4d/4SzZe++/u/UhI/p5ReCAC 9WLFnTOGdQTgehL+6l8BxflZIqKBxYBQ0MdTi/JYCf534MXb/IMFDtfkMp6UlzSC6vC27q9TfJ 5+qePST0qctIOVi5H30ycKgNPrcPeT5ItRpH40EkGE3DkwkaNeELVwP+pJN51WkM5AGUuZwh3m IRoytQ+Gt6irJybQ91AWn2/rNpG/cMHSp7HyqY7gnOYquCpSXk+tM6eEz6N62G/HRz7Nfh0D+l duOe28diwP6a/JkQwP71PX1v IronPort-SDR: r3j5nrECWcTjVdhESWatgb14bhrHhe/9kQWFmAn68ECHRl1ZG+oixb86A4Nqg5OqX5V0ypYxX2 f/qK/RAJibAsfmiBNqCGApmsUbkkShx4VnRKq9NgOh44KR6n7+nJgIBPTLlTvqcUTz9fJDtmx3 aaeMiCYv+N/sodECp1L1p91BUsSAX3p/V4yvjPy2hZYD2zbH4X6/NkSPGe0iKqOynaY5lp0Cr7 x7Hl/wrbQ5w/ELg67HuRG2ih2rEvQpBuYGT2Ri/UD0QJ5GhX5SXrBeIhNLpLp1Bfvt/p2FrOvx i3c= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP) Date: Thu, 6 May 2021 09:22:54 +1000 Message-Id: <20210505232312.4175486-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hou Weiying , qemu-devel@nongnu.org, Hongzheng-Li , Alistair Francis , alistair23@gmail.com, Bin Meng , Myriad-Dreamin Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Hou Weiying This commit adds support for ePMP v0.9.1. The ePMP spec can be found in: https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUz= bvc8 Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: fef23b885f9649a4d54e7c98b168bdec5d297bb1.1618812899.git.alistai= r.francis@wdc.com [ Changes by AF: - Rebase on master - Update to latest spec - Use a switch case to handle ePMP MML permissions - Fix a few bugs ] Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 154 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 146 insertions(+), 8 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index e35988eec2..e1f5776316 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -90,11 +90,42 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, = uint32_t pmp_index) static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t = val) { if (pmp_index < MAX_RISCV_PMPS) { - if (!pmp_is_locked(env, pmp_index)) { - env->pmp_state.pmp[pmp_index].cfg_reg =3D val; - pmp_update_rule(env, pmp_index); + bool locked =3D true; + + if (riscv_feature(env, RISCV_FEATURE_EPMP)) { + /* mseccfg.RLB is set */ + if (MSECCFG_RLB_ISSET(env)) { + locked =3D false; + } + + /* mseccfg.MML is not set */ + if (!MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, pmp_index))= { + locked =3D false; + } + + /* mseccfg.MML is set */ + if (MSECCFG_MML_ISSET(env)) { + /* not adding execute bit */ + if ((val & PMP_LOCK) !=3D 0 && (val & PMP_EXEC) !=3D PMP_E= XEC) { + locked =3D false; + } + /* shared region and not adding X bit */ + if ((val & PMP_LOCK) !=3D PMP_LOCK && + (val & 0x7) !=3D (PMP_WRITE | PMP_EXEC)) { + locked =3D false; + } + } } else { + if (!pmp_is_locked(env, pmp_index)) { + locked =3D false; + } + } + + if (locked) { qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked= \n"); + } else { + env->pmp_state.pmp[pmp_index].cfg_reg =3D val; + pmp_update_rule(env, pmp_index); } } else { qemu_log_mask(LOG_GUEST_ERROR, @@ -217,6 +248,32 @@ static bool pmp_hart_has_privs_default(CPURISCVState *= env, target_ulong addr, { bool ret; =20 + if (riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (MSECCFG_MMWP_ISSET(env)) { + /* + * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set + * so we default to deny all, even for M-mode. + */ + *allowed_privs =3D 0; + return false; + } else if (MSECCFG_MML_ISSET(env)) { + /* + * The Machine Mode Lockdown (mseccfg.MML) bit is set + * so we can only execute code in M-mode with an applicable + * rule. Other modes are disabled. + */ + if (mode =3D=3D PRV_M && !(privs & PMP_EXEC)) { + ret =3D true; + *allowed_privs =3D PMP_READ | PMP_WRITE; + } else { + ret =3D false; + *allowed_privs =3D 0; + } + + return ret; + } + } + if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode =3D=3D PRV_M)) { /* * Privileged spec v1.10 states if HW doesn't implement any PMP en= try @@ -294,13 +351,94 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ul= ong addr, pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); =20 /* - * If the PMP entry is not off and the address is in range, do the= priv - * check + * Convert the PMP permissions to match the truth table in the + * ePMP spec. */ + const uint8_t epmp_operation =3D + ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) | + ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) | + (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) | + ((env->pmp_state.pmp[i].cfg_reg & PMP_EXEC) >> 2); + if (((s + e) =3D=3D 2) && (PMP_AMATCH_OFF !=3D a_field)) { - *allowed_privs =3D PMP_READ | PMP_WRITE | PMP_EXEC; - if ((mode !=3D PRV_M) || pmp_is_locked(env, i)) { - *allowed_privs &=3D env->pmp_state.pmp[i].cfg_reg; + /* + * If the PMP entry is not off and the address is in range, + * do the priv check + */ + if (!MSECCFG_MML_ISSET(env)) { + /* + * If mseccfg.MML Bit is not set, do pmp priv check + * This will always apply to regular PMP. + */ + *allowed_privs =3D PMP_READ | PMP_WRITE | PMP_EXEC; + if ((mode !=3D PRV_M) || pmp_is_locked(env, i)) { + *allowed_privs &=3D env->pmp_state.pmp[i].cfg_reg; + } + } else { + /* + * If mseccfg.MML Bit set, do the enhanced pmp priv check + */ + if (mode =3D=3D PRV_M) { + switch (epmp_operation) { + case 0: + case 1: + case 4: + case 5: + case 6: + case 7: + case 8: + *allowed_privs =3D 0; + break; + case 2: + case 3: + case 14: + *allowed_privs =3D PMP_READ | PMP_WRITE; + break; + case 9: + case 10: + *allowed_privs =3D PMP_EXEC; + break; + case 11: + case 13: + *allowed_privs =3D PMP_READ | PMP_EXEC; + break; + case 12: + case 15: + *allowed_privs =3D PMP_READ; + break; + } + } else { + switch (epmp_operation) { + case 0: + case 8: + case 9: + case 12: + case 13: + case 14: + *allowed_privs =3D 0; + break; + case 1: + case 10: + case 11: + *allowed_privs =3D PMP_EXEC; + break; + case 2: + case 4: + case 15: + *allowed_privs =3D PMP_READ; + break; + case 3: + case 6: + *allowed_privs =3D PMP_READ | PMP_WRITE; + break; + case 5: + *allowed_privs =3D PMP_READ | PMP_EXEC; + break; + case 7: + *allowed_privs =3D PMP_READ | PMP_WRITE | PMP_EXEC; + break; + } + } } =20 ret =3D ((privs & *allowed_privs) =3D=3D privs); --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620258082; cv=none; d=zohomail.com; s=zohoarc; b=fG7ss7KkyWJihw6f1iWCicFZpyRzzJIfrpakErqekago84N9SGqxJ/IeOyllM2qGr467hMRa4o25hxC6ixthj08diQmDxl5UUYuzd23LBZmtfD+heavIWGtutx+TEjQ7H7Ruftp2OymlKbmFF/SX680bRCbtA41sFrqXGBkn4LI= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hou Weiying , qemu-devel@nongnu.org, Hongzheng-Li , Alistair Francis , alistair23@gmail.com, Bin Meng , Myriad-Dreamin Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Hou Weiying Add a config option to enable experimental support for ePMP. This is disabled by default and can be enabled with 'x-epmp=3Dtrue'. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistai= r.francis@wdc.com Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 83b315e0b2..add734bbbd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -304,6 +304,7 @@ struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; + bool epmp; uint64_t resetvec; } cfg; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e530df9385..66787d019c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -412,6 +412,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) =20 if (cpu->cfg.pmp) { set_feature(env, RISCV_FEATURE_PMP); + + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + if (cpu->cfg.epmp) { + set_feature(env, RISCV_FEATURE_EPMP); + } } =20 set_resetvec(env, cpu->cfg.resetvec); @@ -554,6 +562,8 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620257190; cv=none; d=zohomail.com; s=zohoarc; b=LxHdnCyyh83FiKVlsG0bdmwjoeUXy1CYEzkdp5tl8JyC2j20bagBnHSnh8JGC2QOYSFpmcW9KMQUy2Y/n4lS/fO8O3n6polpHmayECLm3wudZZRtKFNLxC201ffaNdnelnov80shBnHvJ2aTms9lGgFCLjGp9GFC7XJo4Mciop0= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistai= r.francis@wdc.com --- target/riscv/pmp.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index e1f5776316..78203291de 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -19,10 +19,6 @@ * this program. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The physical Ibex CPU has ePMP support and it's enabled for the OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistai= r.francis@wdc.com --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 66787d019c..4bf6a00636 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -202,6 +202,7 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, RV32 | RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); + qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); } =20 static void rv32_imafcu_nommu_cpu_init(Object *obj) --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , alistair23@gmail.com, Alistair Francis , Richard Henderson , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Frank Chang ETYPE may be type of uint64_t, thus index variable has to be declared as type of uint64_t, too. Otherwise the value read from vs1 register may be truncated to type of uint32_t. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20210419060302.14075-1-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 356cef8a09..4651a1e224 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4796,7 +4796,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ - uint32_t index, i; \ + uint64_t index; \ + uint32_t i; \ \ for (i =3D 0; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, mlen, i)) { \ @@ -4826,7 +4827,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ - uint32_t index =3D s1, i; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org, Emmanuel Blot Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Emmanuel Blot When no MMU is used and the guest code attempts to fetch an instruction from an invalid memory location, the exception index defaults to a data load access fault, rather an instruction access fault. Signed-off-by: Emmanuel Blot Reviewed-by: Alistair Francis Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 659ca8a173..1018c0036d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -694,8 +694,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, =20 if (access_type =3D=3D MMU_DATA_STORE) { cs->exception_index =3D RISCV_EXCP_STORE_AMO_ACCESS_FAULT; - } else { + } else if (access_type =3D=3D MMU_DATA_LOAD) { cs->exception_index =3D RISCV_EXCP_LOAD_ACCESS_FAULT; + } else { + cs->exception_index =3D RISCV_EXCP_INST_ACCESS_FAULT; } =20 env->badaddr =3D addr; --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org, Alexander Wagner Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Alexander Wagner The IBEX documentation [1] specifies the reset vector to be "the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte". [1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_= interrupts.rst Signed-off-by: Alexander Wagner Reviewed-by: Alistair Francis Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de Signed-off-by: Alistair Francis --- hw/riscv/opentitan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 557d73726b..7545dcda9c 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -119,7 +119,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); - object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_a= bort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_a= bort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); =20 /* Boot ROM */ --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , alistair23@gmail.com, Alistair Francis , Richard Henderson , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Frank Chang In IEEE 754-2008 spec: Invalid operation exception is signaled when doing: fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whether the invalid operation exception is signaled. In RISC-V Unprivileged ISA spec: The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are Inf and zero, even when the addend is a quiet NaN. This commit set invalid operation execption flag for RISC-V when multiplicands of muladd instructions are Inf and zero. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20210420013150.21992-1-frank.chang@sifive.com Signed-off-by: Alistair Francis --- fpu/softfloat-specialize.c.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9ea318f3e2..78f699d6f8 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -627,6 +627,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass = b_cls, FloatClass c_cls, } else { return 1; } +#elif defined(TARGET_RISCV) + /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ + if (infzero) { + float_raise(float_flag_invalid, status); + } + return 3; /* default NaN */ #elif defined(TARGET_XTENSA) /* * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , qemu-devel@nongnu.org, Emmanuel Blot Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Emmanuel Blot Interrupt names have been swapped in 205377f8 and do not follow IRQ_*_EXT definition order. Signed-off-by: Emmanuel Blot Reviewed-by: Alistair Francis Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4bf6a00636..04ac03f8c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -88,8 +88,8 @@ const char * const riscv_intr_names[] =3D { "vs_timer", "m_timer", "u_external", + "s_external", "vs_external", - "h_external", "m_external", "reserved", "reserved", --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620258478; cv=none; d=zohomail.com; s=zohoarc; b=nEZ/s0jWgfnEb5yFSsSjHzdYKQ8UoyrxA8bTCC438syWtEBj7fTvt40dMH1baswddtO1cUDF92/zsQ1CW8puGQwU1E2aTLfprDs8ho8wjmnuR5LSabluPeuNeihzOJEp7EkeLQdmWjgaWHjbgQ5MLgF5z2f/hEXNTsO0BfhjnYM= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistai= r.francis@wdc.com --- target/riscv/cpu.h | 6 ------ target/riscv/cpu.c | 6 +++++- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index add734bbbd..7e879fb9ca 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -54,12 +54,6 @@ #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) =20 -#if defined(TARGET_RISCV32) -#define RVXLEN RV32 -#elif defined(TARGET_RISCV64) -#define RVXLEN RV64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) =20 #define RVI RV('I') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 04ac03f8c9..3191fd0082 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, target_ul= ong resetvec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#if defined(TARGET_RISCV32) + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#elif defined(TARGET_RISCV64) + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#endif set_priv_version(env, PRIV_VERSION_1_11_0); } =20 --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620258579; cv=none; d=zohomail.com; s=zohoarc; b=R72tf6zQUpEGCTnCyqC8M57EPpAioIk91P4+YC1IoO5rwYmoE/vTglgPJFgDFoUwsP3RUwUnSTc+mtVcqWIeU4LlNDtAPcpKKDKKrWnOsvFuWHpNYnbDlrfJevyriOXE0DCzFPb06xTq0L4boGYR0RcD/Rom8KVA5mAlQIvpCoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This also ensures that the SD bit is not writable. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: 9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistai= r.francis@wdc.com --- target/riscv/cpu_bits.h | 6 ------ target/riscv/csr.c | 9 ++++++++- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 24d89939a0..3a0e79e545 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -403,12 +403,6 @@ #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000ULL =20 -#if defined(TARGET_RISCV32) -#define SSTATUS_SD SSTATUS32_SD -#elif defined(TARGET_RISCV64) -#define SSTATUS_SD SSTATUS64_SD -#endif - /* hstatus CSR bits */ #define HSTATUS_VSBE 0x00000020 #define HSTATUS_GVA 0x00000040 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 97ceff718f..41951a0a84 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -459,7 +459,7 @@ static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; + SSTATUS_SUM | SSTATUS_MXR; static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; @@ -788,6 +788,13 @@ static RISCVException read_sstatus(CPURISCVState *env,= int csrno, target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); + + if (riscv_cpu_is_32bit(env)) { + mask |=3D SSTATUS32_SD; + } else { + mask |=3D SSTATUS64_SD; + } + *val =3D env->mstatus & mask; return RISCV_EXCP_NONE; } --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="166586011" IronPort-SDR: jCxKKnJ9sSZVPdLyJ7EQ/PrcRCRvOoa033IQwvjhIelGilHGHrtcxhp0OtUHQgYj42NPCDGoxA R4pd5cy0/Fz30S+UCfHKmJWqtaU5OoxAM1p5cmD7flXfPf5JaHWAR+UB4raj79ZWPgl7tLmC+C VLC8IV1VZfx4SgwjDG8rLpgHM5F8UbvR1XmntOCulFkTWnedqW8BnLUCKmYoUuIcWqvigrFd0r DKQic2SJN/zW7f8fOag29VhCSN7FTnUd1H1VqUYFucekVbDHZFKO0Xeg6W/dldF1+bwlE2JoJe DUqBXn/crTqqohOA2LsmJnsj IronPort-SDR: 4GG2t7tP9RSq6K+iNmVv2bPxl6eMo8bGXUmhp+CTe+Na/uobf+0GxkOspTK7v1CF4YF4ND8uAS Hq6g3u/GkrCQR4qd5xQBeN9KfdYfJG16Eh+RjRHUgrnhdDdLaxJKq4i+9VmR4zHOECZ7qAB3bx mzt3Pux2TvWlhioe+khLMbCv2WoDfpmluNUicCatRUHfOvrR1xrLYAl9dVufAHEW8EVz1drdjI 65OIu3BUMs3/nqIM6qpKG1jtMkLznmosejZEzPL7IMspKDQ5B4xAp3dgqKNebBrtqjy2Xfp5By xMk= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro Date: Thu, 6 May 2021 09:23:05 +1000 Message-Id: <20210505232312.4175486-36-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: 665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistai= r.francis@wdc.com --- target/riscv/cpu_bits.h | 11 ----------- target/riscv/cpu_helper.c | 24 +++++++++++++++--------- 2 files changed, 15 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 3a0e79e545..d738e2fdbd 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -195,17 +195,6 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 =20 -#if defined(TARGET_RISCV32) -#define HGATP_MODE SATP32_MODE -#define HGATP_VMID SATP32_ASID -#define HGATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define HGATP_MODE SATP64_MODE -#define HGATP_VMID SATP64_ASID -#define HGATP_PPN SATP64_PPN -#endif - /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1018c0036d..d9defbdd34 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -413,8 +413,13 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, } widened =3D 0; } else { - base =3D (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; - vm =3D get_field(env->hgatp, HGATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, SATP64_MODE); + } widened =3D 2; } /* status.SUM will be ignored if execute on background */ @@ -618,16 +623,17 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, bool first_stage, bool two_stage) { CPUState *cs =3D env_cpu(env); - int page_fault_exceptions; + int page_fault_exceptions, vm; + if (first_stage) { - page_fault_exceptions =3D - get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && - !pmp_violation; + vm =3D get_field(env->satp, SATP_MODE); + } else if (riscv_cpu_is_32bit(env)) { + vm =3D get_field(env->hgatp, SATP32_MODE); } else { - page_fault_exceptions =3D - get_field(env->hgatp, HGATP_MODE) !=3D VM_1_10_MBARE && - !pmp_violation; + vm =3D get_field(env->hgatp, SATP64_MODE); } + page_fault_exceptions =3D vm !=3D VM_1_10_MBARE && !pmp_violation; + switch (access_type) { case MMU_INST_FETCH: if (riscv_cpu_virt_enabled(env) && !first_stage) { --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620257549; cv=none; d=zohomail.com; s=zohoarc; b=bhFyc0hYkCseH7ZLj0CnpPgbwai6/BHRy8TXOLd6OIr91MfTcHCnfzyP6K83+fdwEoML9b1NeH92o0BY6mBF+QQKvJt4BMiEy5daPT6DNYCU00TT+2vsiQKlF0YIgdvfBgA5bfgSbXI7eYlc+TwIPYYhwrDlrO4gLsqs+rErf7s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620257549; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistai= r.francis@wdc.com --- target/riscv/cpu_bits.h | 10 ---------- target/riscv/csr.c | 12 ++++++++++-- target/riscv/translate.c | 19 +++++++++++++++++-- 3 files changed, 27 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index d738e2fdbd..6e30b312f0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -368,16 +368,6 @@ #define MXL_RV64 2 #define MXL_RV128 3 =20 -#if defined(TARGET_RISCV32) -#define MSTATUS_SD MSTATUS32_SD -#define MISA_MXL MISA32_MXL -#define MXL_VAL MXL_RV32 -#elif defined(TARGET_RISCV64) -#define MSTATUS_SD MSTATUS64_SD -#define MISA_MXL MISA64_MXL -#define MXL_VAL MXL_RV64 -#endif - /* sstatus CSR bits */ #define SSTATUS_UIE 0x00000001 #define SSTATUS_SIE 0x00000002 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 41951a0a84..e955753441 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -538,7 +538,11 @@ static RISCVException write_mstatus(CPURISCVState *env= , int csrno, =20 dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); - mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, dirty); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, dirty); + } env->mstatus =3D mstatus; =20 return RISCV_EXCP_NONE; @@ -614,7 +618,11 @@ static RISCVException write_misa(CPURISCVState *env, i= nt csrno, } =20 /* misa.MXL writes are not supported by QEMU */ - val =3D (env->misa & MISA_MXL) | (val & ~MISA_MXL); + if (riscv_cpu_is_32bit(env)) { + val =3D (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); + } else { + val =3D (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); + } =20 /* flush translation cache */ if (val !=3D env->misa) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 26eccc5eb1..a596f80f20 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t e= xt) return ctx->misa & ext; } =20 +#ifdef TARGET_RISCV32 +# define is_32bit(ctx) true +#elif defined(CONFIG_USER_ONLY) +# define is_32bit(ctx) false +#else +static inline bool is_32bit(DisasContext *ctx) +{ + return (ctx->misa & RV32) =3D=3D RV32; +} +#endif + /* * RISC-V requires NaN-boxing of narrower width floating point values. * This applies when a 32-bit value is assigned to a 64-bit FP register. @@ -369,6 +380,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_u= long imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; + target_ulong sd; + if (ctx->mstatus_fs =3D=3D MSTATUS_FS) { return; } @@ -376,13 +389,15 @@ static void mark_fs_dirty(DisasContext *ctx) ctx->mstatus_fs =3D MSTATUS_FS; =20 tmp =3D tcg_temp_new(); + sd =3D is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); =20 if (ctx->virt_enabled) { tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); } tcg_temp_free(tmp); --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620258212; cv=none; d=zohomail.com; s=zohoarc; b=kWRHuJKPeAo9lvN+d+7IEH/raMNEb/OWEeUZ5GnkyELAiRyWHElZvTNHjZ4SRd/TzPKhyVQYtL8/vWyOEvXz+752E3wHiEyR4pTRDSvf5tHm0zBcS7igNGbl/VZIleAEgr8exddqXKmEAURODu0a4YUbM4zGwUPECn1TCTmLTeA= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistai= r.francis@wdc.com --- target/riscv/cpu_bits.h | 11 ----------- target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++-------- target/riscv/csr.c | 19 +++++++++++++++---- target/riscv/monitor.c | 22 +++++++++++++++++----- 4 files changed, 56 insertions(+), 28 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6e30b312f0..d98f3bc8bc 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -432,17 +432,6 @@ #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 -#if defined(TARGET_RISCV32) -#define SATP_MODE SATP32_MODE -#define SATP_ASID SATP32_ASID -#define SATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define SATP_MODE SATP64_MODE -#define SATP_ASID SATP64_ASID -#define SATP_PPN SATP64_PPN -#endif - /* VM modes (mstatus.vm) privileged ISA 1.9.1 */ #define VM_1_09_MBARE 0 #define VM_1_09_MBB 1 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d9defbdd34..968cb8046f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -405,11 +405,21 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 if (first_stage =3D=3D true) { if (use_background) { - base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->vsatp, SATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP64_MODE); + } } else { - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->satp, SATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP64_MODE); + } } widened =3D 0; } else { @@ -624,14 +634,20 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, { CPUState *cs =3D env_cpu(env); int page_fault_exceptions, vm; + uint64_t stap_mode; + + if (riscv_cpu_is_32bit(env)) { + stap_mode =3D SATP32_MODE; + } else { + stap_mode =3D SATP64_MODE; + } =20 if (first_stage) { - vm =3D get_field(env->satp, SATP_MODE); - } else if (riscv_cpu_is_32bit(env)) { - vm =3D get_field(env->hgatp, SATP32_MODE); + vm =3D get_field(env->satp, stap_mode); } else { - vm =3D get_field(env->hgatp, SATP64_MODE); + vm =3D get_field(env->hgatp, stap_mode); } + page_fault_exceptions =3D vm !=3D VM_1_10_MBARE && !pmp_violation; =20 switch (access_type) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e955753441..fe5628fea6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -997,16 +997,27 @@ static RISCVException read_satp(CPURISCVState *env, i= nt csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { + int vm, mask, asid; + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE; } - if (validate_vm(env, get_field(val, SATP_MODE)) && - ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) - { + + if (riscv_cpu_is_32bit(env)) { + vm =3D validate_vm(env, get_field(val, SATP32_MODE)); + mask =3D (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_P= PN); + asid =3D (val ^ env->satp) & SATP32_ASID; + } else { + vm =3D validate_vm(env, get_field(val, SATP64_MODE)); + mask =3D (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_P= PN); + asid =3D (val ^ env->satp) & SATP64_ASID; + } + + if (vm && mask) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { return RISCV_EXCP_ILLEGAL_INST; } else { - if ((val ^ env->satp) & SATP_ASID) { + if (asid) { tlb_flush(env_cpu(env)); } env->satp =3D val; diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index e51188f919..f7e6ea72b3 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *= env) target_ulong last_size; int last_attr; =20 - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP64_MODE); + } =20 - vm =3D get_field(env->satp, SATP_MODE); switch (vm) { case VM_1_10_SV32: levels =3D 2; @@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } =20 - if (!(env->satp & SATP_MODE)) { - monitor_printf(mon, "No translation or protection\n"); - return; + if (riscv_cpu_is_32bit(env)) { + if (!(env->satp & SATP32_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } + } else { + if (!(env->satp & SATP64_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } } =20 mem_info_svxx(mon, env); --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="166586029" IronPort-SDR: zlvGoCPhNJNAVweqIR5JO05MvvVKFya1k1IfT1jHjJMuXNO4zmCs+4hpBXZ0va2BhteLI6UW4e mgi8Q4tr47HUQRyVADsyWiCsZgL5FaZ2j6Fd1Al1djaW70ElARGKuoHWP80/A35uPsT6AO+uGY 7JXHTjtJTsLcuZx35JZHUERLRqJWqQRrsTp6q6HLI0UkgugOJ4gNemGB2mX0r3hD10EvV+aP9S 6hAeiDFkH3tu/WGpUc0fdAdkpWi3L8VtV9o3nFVesJav9kYTaWfnCbqiFZHf/ou2LuTw4sKkRD GTj13B9CIVSTGxvCQ0T2WlxH IronPort-SDR: 5qqj5U3QybXrMeeKIrXXLwzmkULr0eJA5g1+Fe1PPF4ReqTNm+m7K38kFdJfUHmGimDuGKSHGz 6+4an3JDMjTZi2lwUQDnNr+MW+ZLkGRS87A9NIaT4cfJipzgTZ0CsQ9aeLtpChv5LdaH7mJwJ1 I/3JM5f8MWjA3c0J8o+ZDHvQ1FS0NJG8d7LI40EkvZn51KJ3PUHagbFHmtpV0jKLI/4P99fE5G Lz0Oyd7YV6K1n+MHa0a+48zE/14cedfvFaLf1olYQLMBuoq3X4UnM3085YMr+8i+IOQho8tVPp yFs= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Date: Thu, 6 May 2021 09:23:08 +1000 Message-Id: <20210505232312.4175486-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com> References: <20210505232312.4175486-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistai= r.francis@wdc.com --- target/riscv/cpu_bits.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index d98f3bc8bc..52640e6856 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -396,12 +396,6 @@ #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL =20 -#if defined(TARGET_RISCV32) -#define HSTATUS_WPRI HSTATUS32_WPRI -#elif defined(TARGET_RISCV64) -#define HSTATUS_WPRI HSTATUS64_WPRI -#endif - #define HCOUNTEREN_CY (1 << 0) #define HCOUNTEREN_TM (1 << 1) #define HCOUNTEREN_IR (1 << 2) --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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} DisasContext; =20 -#ifdef TARGET_RISCV64 -#define CASE_OP_32_64(X) case X: case glue(X, W) -#else -#define CASE_OP_32_64(X) case X -#endif - static inline bool has_ext(DisasContext *ctx, uint32_t ext) { return ctx->misa & ext; --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620258326; cv=none; d=zohomail.com; s=zohoarc; b=QJKD3CAHmPDNlPjV99gi6ltO4H8F76EEZoI3usMtfmJo1bzxSRI2yrE/fJ81Qhs6MenDaqiq41APKMGKo9S/92QgQZR9MvBj41g6kAyi3RoGVcHWqhoWGLgvDb1hxYFCUcAKINpz8+smVnkO4RIM9O1lTzIYLkNQMwgah7svGks= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620258326; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistai= r.francis@wdc.com --- target/riscv/helper.h | 18 +++-- target/riscv/insn32-64.decode | 88 ------------------------- target/riscv/insn32.decode | 67 ++++++++++++++++++- target/riscv/fpu_helper.c | 16 ++--- target/riscv/translate.c | 9 ++- target/riscv/vector_helper.c | 4 -- target/riscv/insn_trans/trans_rva.c.inc | 14 +++- target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++- target/riscv/insn_trans/trans_rvf.c.inc | 6 +- target/riscv/insn_trans/trans_rvh.c.inc | 8 ++- target/riscv/insn_trans/trans_rvi.c.inc | 16 +++-- target/riscv/insn_trans/trans_rvm.c.inc | 12 +++- target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------ target/riscv/meson.build | 2 +- 14 files changed, 166 insertions(+), 150 deletions(-) delete mode 100644 target/riscv/insn32-64.decode diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e3f3f41e89..c7267593c3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -27,12 +27,12 @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64= , i64) DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64) DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64) -DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64) DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64) =20 /* Floating Point - Double Precision */ @@ -50,12 +50,12 @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64= , i64) DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64) DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64) -DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64) DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) =20 /* Special functions */ @@ -241,7 +241,6 @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32) -#ifdef TARGET_RISCV64 DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32) @@ -260,7 +259,6 @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, en= v, i32) DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32) -#endif DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode deleted file mode 100644 index 8157dee8b7..0000000000 --- a/target/riscv/insn32-64.decode +++ /dev/null @@ -1,88 +0,0 @@ -# -# RISC-V translation routines for the RV Instruction Set. -# -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de -# Bastian Koppelmann, kbastian@mail.uni-paderborn.de -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2 or later, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License along = with -# this program. If not, see . - -# This is concatenated with insn32.decode for risc64 targets. -# Most of the fields and formats are there. - -%sh5 20:5 - -@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd - -# *** RV64I Base Instruction Set (in addition to RV32I) *** -lwu ............ ..... 110 ..... 0000011 @i -ld ............ ..... 011 ..... 0000011 @i -sd ....... ..... ..... 011 ..... 0100011 @s -addiw ............ ..... 000 ..... 0011011 @i -slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 -srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 -sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 -addw 0000000 ..... ..... 000 ..... 0111011 @r -subw 0100000 ..... ..... 000 ..... 0111011 @r -sllw 0000000 ..... ..... 001 ..... 0111011 @r -srlw 0000000 ..... ..... 101 ..... 0111011 @r -sraw 0100000 ..... ..... 101 ..... 0111011 @r - -# *** RV64M Standard Extension (in addition to RV32M) *** -mulw 0000001 ..... ..... 000 ..... 0111011 @r -divw 0000001 ..... ..... 100 ..... 0111011 @r -divuw 0000001 ..... ..... 101 ..... 0111011 @r -remw 0000001 ..... ..... 110 ..... 0111011 @r -remuw 0000001 ..... ..... 111 ..... 0111011 @r - -# *** RV64A Standard Extension (in addition to RV32A) *** -lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld -sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st -amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st -amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st -amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st -amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st -amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st -amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st -amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st -amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st -amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st - -#*** Vector AMO operations (in addition to Zvamo) *** -vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm - -# *** RV64F Standard Extension (in addition to RV32F) *** -fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm -fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm -fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm -fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm - -# *** RV64D Standard Extension (in addition to RV32D) *** -fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm -fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm -fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 -fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm -fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm -fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 - -# *** RV32H Base Instruction Set *** -hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 -hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 -hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 84080dd18c..fecf0f15d5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -21,6 +21,7 @@ %rs2 20:5 %rs1 15:5 %rd 7:5 +%sh5 20:5 =20 %sh10 20:10 %csr 20:12 @@ -86,6 +87,8 @@ @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 =20 +# Formats 64: +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd =20 # *** Privileged Instructions *** ecall 000000000000 00000 000 00000 1110011 @@ -144,6 +147,20 @@ csrrwi ............ ..... 101 ..... 1110011 @csr csrrsi ............ ..... 110 ..... 1110011 @csr csrrci ............ ..... 111 ..... 1110011 @csr =20 +# *** RV64I Base Instruction Set (in addition to RV32I) *** +lwu ............ ..... 110 ..... 0000011 @i +ld ............ ..... 011 ..... 0000011 @i +sd ....... ..... ..... 011 ..... 0100011 @s +addiw ............ ..... 000 ..... 0011011 @i +slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 +srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 +sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 +addw 0000000 ..... ..... 000 ..... 0111011 @r +subw 0100000 ..... ..... 000 ..... 0111011 @r +sllw 0000000 ..... ..... 001 ..... 0111011 @r +srlw 0000000 ..... ..... 101 ..... 0111011 @r +sraw 0100000 ..... ..... 101 ..... 0111011 @r + # *** RV32M Standard Extension *** mul 0000001 ..... ..... 000 ..... 0110011 @r mulh 0000001 ..... ..... 001 ..... 0110011 @r @@ -154,6 +171,13 @@ divu 0000001 ..... ..... 101 ..... 0110011 @r rem 0000001 ..... ..... 110 ..... 0110011 @r remu 0000001 ..... ..... 111 ..... 0110011 @r =20 +# *** RV64M Standard Extension (in addition to RV32M) *** +mulw 0000001 ..... ..... 000 ..... 0111011 @r +divw 0000001 ..... ..... 100 ..... 0111011 @r +divuw 0000001 ..... ..... 101 ..... 0111011 @r +remw 0000001 ..... ..... 110 ..... 0111011 @r +remuw 0000001 ..... ..... 111 ..... 0111011 @r + # *** RV32A Standard Extension *** lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st @@ -167,6 +191,19 @@ amomax_w 10100 . . ..... ..... 010 ..... 0101111 @at= om_st amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st =20 +# *** RV64A Standard Extension (in addition to RV32A) *** +lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld +sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st +amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st +amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st +amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st +amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st +amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st +amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st +amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st +amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st +amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st + # *** RV32F Standard Extension *** flw ............ ..... 010 ..... 0000111 @i fsw ....... ..... ..... 010 ..... 0100111 @s @@ -195,6 +232,12 @@ fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_= rm fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 =20 +# *** RV64F Standard Extension (in addition to RV32F) *** +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm + # *** RV32D Standard Extension *** fld ............ ..... 011 ..... 0000111 @i fsd ....... ..... ..... 011 ..... 0100111 @s @@ -223,6 +266,14 @@ fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_= rm fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm =20 +# *** RV64D Standard Extension (in addition to RV32D) *** +fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm +fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 +fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm +fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 + # *** RV32H Base Instruction Set *** hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 @@ -237,7 +288,10 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r= 2_s hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma =20 -# *** RV32V Extension *** +# *** RV32H Base Instruction Set *** +hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 +hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 +hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s =20 # *** Vector loads and stores are encoded within LOADFP/STORE-FP *** vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm @@ -592,3 +646,14 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111= @r =20 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r + +#*** Vector AMO operations (in addition to Zvamo) *** +vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 7c4ab92ecb..8700516a14 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -223,13 +223,13 @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uin= t64_t rs1) return (int32_t)float32_to_uint32(frs1, &env->fp_status); } =20 -uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1) +target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(rs1); return float32_to_int64(frs1, &env->fp_status); } =20 -uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1) +target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(rs1); return float32_to_uint64(frs1, &env->fp_status); @@ -245,12 +245,12 @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_= ulong rs1) return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status)); } =20 -uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1) +uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1) { return nanbox_s(int64_to_float32(rs1, &env->fp_status)); } =20 -uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) +uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1) { return nanbox_s(uint64_to_float32(rs1, &env->fp_status)); } @@ -332,12 +332,12 @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uin= t64_t frs1) return (int32_t)float64_to_uint32(frs1, &env->fp_status); } =20 -uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1) +target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1) { return float64_to_int64(frs1, &env->fp_status); } =20 -uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1) +target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1) { return float64_to_uint64(frs1, &env->fp_status); } @@ -352,12 +352,12 @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_= ulong rs1) return uint32_to_float64((uint32_t)rs1, &env->fp_status); } =20 -uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1) +uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1) { return int64_to_float64(rs1, &env->fp_status); } =20 -uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1) +uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1) { return uint64_to_float64(rs1, &env->fp_status); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a1f794ffda..e945352bca 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -435,6 +435,12 @@ EX_SH(12) } \ } while (0) =20 +#define REQUIRE_64BIT(ctx) do { \ + if (is_32bit(ctx)) { \ + return false; \ + } \ +} while (0) + static int ex_rvc_register(DisasContext *ctx, int reg) { return 8 + reg; @@ -482,7 +488,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *= a, return true; } =20 -#ifdef TARGET_RISCV64 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) { tcg_gen_add_tl(ret, arg1, arg2); @@ -543,8 +548,6 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *= a, return true; } =20 -#endif - static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 4651a1e224..12c31aa4b4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -751,7 +751,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_= MIN, l) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l) GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l) -#ifdef TARGET_RISCV64 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l) GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q) GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l) @@ -770,7 +769,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_= MINU, l) GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q) -#endif =20 static inline void vext_amo_noatomic(void *vs3, void *v0, target_ulong base, @@ -814,7 +812,6 @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong bas= e, \ GETPC()); \ } =20 -#ifdef TARGET_RISCV64 GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq) GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq) GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq) @@ -833,7 +830,6 @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, = clearq) GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq) GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq) GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq) -#endif GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl) GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl) GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index be8a9f06dd..ab2ec4f0a5 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -165,60 +165,68 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_am= omaxu_w *a) return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= ESL)); } =20 -#ifdef TARGET_RISCV64 - static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) { + REQUIRE_64BIT(ctx); return gen_lr(ctx, a, MO_ALIGN | MO_TEQ); } =20 static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) { + REQUIRE_64BIT(ctx); return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ)); } =20 static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ)); } =20 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TE= Q)); } =20 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TE= Q)); } =20 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TE= Q)); } =20 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ= )); } =20 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_T= EQ)); } =20 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_T= EQ)); } =20 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_T= EQ)); } =20 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= EQ)); } -#endif diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 4f832637fa..7e45538ae0 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -358,10 +358,9 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcv= t_d_wu *a) return true; } =20 -#ifdef TARGET_RISCV64 - static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 @@ -375,6 +374,7 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_= l_d *a) =20 static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 @@ -388,15 +388,21 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fc= vt_lu_d *a) =20 static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 +#ifdef TARGET_RISCV64 gen_set_gpr(a->rd, cpu_fpr[a->rs1]); return true; +#else + qemu_build_not_reached(); +#endif } =20 static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 @@ -412,6 +418,7 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_= d_l *a) =20 static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 @@ -427,9 +434,11 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcv= t_d_lu *a) =20 static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 +#ifdef TARGET_RISCV64 TCGv t0 =3D tcg_temp_new(); gen_get_gpr(t0, a->rs1); =20 @@ -437,5 +446,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_= x *a) tcg_temp_free(t0); mark_fs_dirty(ctx); return true; -} +#else + qemu_build_not_reached(); #endif +} diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 3dfec8211d..db1c0c9974 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -415,9 +415,9 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_= x *a) return true; } =20 -#ifdef TARGET_RISCV64 static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 @@ -431,6 +431,7 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_= l_s *a) =20 static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 @@ -444,6 +445,7 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt= _lu_s *a) =20 static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 @@ -460,6 +462,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_= s_l *a) =20 static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 @@ -473,4 +476,3 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt= _s_lu *a) tcg_temp_free(t0); return true; } -#endif diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index ce7ed5affb..6b5edf82b7 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -203,10 +203,11 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w = *a) #endif } =20 -#ifdef TARGET_RISCV64 static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); + #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -228,7 +229,9 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu = *a) =20 static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); + #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -250,7 +253,9 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) =20 static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); + #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); @@ -269,7 +274,6 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) return false; #endif } -#endif =20 static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) { diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index d04ca0394c..1340676209 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -204,22 +204,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) return gen_store(ctx, a, MO_TESL); } =20 -#ifdef TARGET_RISCV64 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { + REQUIRE_64BIT(ctx); return gen_load(ctx, a, MO_TEUL); } =20 static bool trans_ld(DisasContext *ctx, arg_ld *a) { + REQUIRE_64BIT(ctx); return gen_load(ctx, a, MO_TEQ); } =20 static bool trans_sd(DisasContext *ctx, arg_sd *a) { + REQUIRE_64BIT(ctx); return gen_store(ctx, a, MO_TEQ); } -#endif =20 static bool trans_addi(DisasContext *ctx, arg_addi *a) { @@ -361,14 +362,15 @@ static bool trans_and(DisasContext *ctx, arg_and *a) return gen_arith(ctx, a, &tcg_gen_and_tl); } =20 -#ifdef TARGET_RISCV64 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { + REQUIRE_64BIT(ctx); return gen_arith_imm_tl(ctx, a, &gen_addw); } =20 static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { + REQUIRE_64BIT(ctx); TCGv source1; source1 =3D tcg_temp_new(); gen_get_gpr(source1, a->rs1); @@ -383,6 +385,7 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) =20 static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { + REQUIRE_64BIT(ctx); TCGv t =3D tcg_temp_new(); gen_get_gpr(t, a->rs1); tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); @@ -395,6 +398,7 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a) =20 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { + REQUIRE_64BIT(ctx); TCGv t =3D tcg_temp_new(); gen_get_gpr(t, a->rs1); tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); @@ -405,16 +409,19 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw = *a) =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) { + REQUIRE_64BIT(ctx); return gen_arith(ctx, a, &gen_addw); } =20 static bool trans_subw(DisasContext *ctx, arg_subw *a) { + REQUIRE_64BIT(ctx); return gen_arith(ctx, a, &gen_subw); } =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { + REQUIRE_64BIT(ctx); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 @@ -433,6 +440,7 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a) =20 static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { + REQUIRE_64BIT(ctx); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 @@ -453,6 +461,7 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a) =20 static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { + REQUIRE_64BIT(ctx); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 @@ -473,7 +482,6 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a) =20 return true; } -#endif =20 static bool trans_fence(DisasContext *ctx, arg_fence *a) { diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 47cd6edc72..10ecc456fc 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -87,34 +87,42 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a) return gen_arith(ctx, a, &gen_remu); } =20 -#ifdef TARGET_RISCV64 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, &gen_mulw); } =20 static bool trans_divw(DisasContext *ctx, arg_divw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith_div_w(ctx, a, &gen_div); } =20 static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith_div_uw(ctx, a, &gen_divu); } =20 static bool trans_remw(DisasContext *ctx, arg_remw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith_div_w(ctx, a, &gen_rem); } =20 static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith_div_uw(ctx, a, &gen_remu); } -#endif diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 887c6b8883..47914a3b69 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -705,7 +705,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) gen_helper_vamominuw_v_w, gen_helper_vamomaxuw_v_w }; -#ifdef TARGET_RISCV64 static gen_helper_amo *const fnsd[18] =3D { gen_helper_vamoswapw_v_d, gen_helper_vamoaddw_v_d, @@ -726,7 +725,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) gen_helper_vamominud_v_d, gen_helper_vamomaxud_v_d }; -#endif =20 if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); @@ -734,12 +732,12 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uin= t8_t seq) return true; } else { if (s->sew =3D=3D 3) { -#ifdef TARGET_RISCV64 - fn =3D fnsd[seq]; -#else - /* Check done in amo_check(). */ - g_assert_not_reached(); -#endif + if (!is_32bit(s)) { + fn =3D fnsd[seq]; + } else { + /* Check done in amo_check(). */ + g_assert_not_reached(); + } } else { assert(seq < ARRAY_SIZE(fnsw)); fn =3D fnsw[seq]; @@ -769,6 +767,11 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) ((1 << s->sew) >=3D 4)); } =20 +static bool amo_check64(DisasContext *s, arg_rwdvm* a) +{ + return !is_32bit(s) && amo_check(s, a); +} + GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check) @@ -778,17 +781,15 @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_chec= k) GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check) -#ifdef TARGET_RISCV64 -GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check) -#endif +GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64) =20 /* *** Vector Integer Arithmetic Instructions diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 88ab850682..24bf049164 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -7,7 +7,7 @@ gen32 =3D [ =20 gen64 =3D [ decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode= ', '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), - decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode= ', '--static-decode=3Ddecode_insn32']), + decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), ] =20 riscv_ss =3D ss.source_set() --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1620258482; cv=none; d=zohomail.com; s=zohoarc; b=kAgfue9PhEX/obhBfEl83I25oRz+POIWPJrINckgH7Tg/muw/0TgOvT/0i93OxzwJNOjjx0GCMOCf1Z4TqeZ6G986mr4srPd0k0GHRpkzhRx1hoY5MhRjSooAEvK84kAwT+UJKP6qu8R4kv6onjTzyehQ91TspW7eIlVDwPmvYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620258482; 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List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This patch removes the insn16-32.decode and insn16-64.decode decode files and consolidates the instructions into the general RISC-V insn16.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistai= r.francis@wdc.com --- target/riscv/insn16-32.decode | 28 ------------------- target/riscv/insn16-64.decode | 36 ------------------------- target/riscv/insn16.decode | 30 +++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.c.inc | 6 +++++ target/riscv/meson.build | 11 +++----- 5 files changed, 39 insertions(+), 72 deletions(-) delete mode 100644 target/riscv/insn16-32.decode delete mode 100644 target/riscv/insn16-64.decode diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode deleted file mode 100644 index 0819b17028..0000000000 --- a/target/riscv/insn16-32.decode +++ /dev/null @@ -1,28 +0,0 @@ -# -# RISC-V translation routines for the RVXI Base Integer Instruction Set. -# -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de -# Bastian Koppelmann, kbastian@mail.uni-paderborn.de -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2 or later, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License along = with -# this program. If not, see . - -# *** RV32C Standard Extension (Quadrant 0) *** -flw 011 ... ... .. ... 00 @cl_w -fsw 111 ... ... .. ... 00 @cs_w - -# *** RV32C Standard Extension (Quadrant 1) *** -jal 001 ........... 01 @cj rd=3D1 # C.JAL - -# *** RV32C Standard Extension (Quadrant 2) *** -flw 011 . ..... ..... 10 @c_lwsp -fsw 111 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode deleted file mode 100644 index 672e1e916f..0000000000 --- a/target/riscv/insn16-64.decode +++ /dev/null @@ -1,36 +0,0 @@ -# -# RISC-V translation routines for the RVXI Base Integer Instruction Set. -# -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de -# Bastian Koppelmann, kbastian@mail.uni-paderborn.de -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2 or later, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License along = with -# this program. If not, see . - -# *** RV64C Standard Extension (Quadrant 0) *** -ld 011 ... ... .. ... 00 @cl_d -sd 111 ... ... .. ... 00 @cs_d - -# *** RV64C Standard Extension (Quadrant 1) *** -{ - illegal 001 - 00000 ----- 01 # c.addiw, RES rd=3D0 - addiw 001 . ..... ..... 01 @ci -} -subw 100 1 11 ... 00 ... 01 @cs_2 -addw 100 1 11 ... 01 ... 01 @cs_2 - -# *** RV64C Standard Extension (Quadrant 2) *** -{ - illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=3D0 - ld 011 . ..... ..... 10 @c_ldsp -} -sd 111 . ..... ..... 10 @c_sdsp diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 1cb93876fe..2e9212663c 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -92,6 +92,16 @@ lw 010 ... ... .. ... 00 @cl_w fsd 101 ... ... .. ... 00 @cs_d sw 110 ... ... .. ... 00 @cs_w =20 +# *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** +{ + ld 011 ... ... .. ... 00 @cl_d + flw 011 ... ... .. ... 00 @cl_w +} +{ + sd 111 ... ... .. ... 00 @cs_d + fsw 111 ... ... .. ... 00 @cs_w +} + # *** RV32/64C Standard Extension (Quadrant 1) *** addi 000 . ..... ..... 01 @ci addi 010 . ..... ..... 01 @c_li @@ -111,6 +121,15 @@ jal 101 ........... 01 @cj rd=3D0= # C.J beq 110 ... ... ..... 01 @cb_z bne 111 ... ... ..... 01 @cb_z =20 +# *** RV64C and RV32C specific Standard Extension (Quadrant 1) *** +{ + c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=3D0 + addiw 001 . ..... ..... 01 @ci + jal 001 ........... 01 @cj rd=3D1 # C.JAL +} +subw 100 1 11 ... 00 ... 01 @cs_2 +addw 100 1 11 ... 01 ... 01 @cs_2 + # *** RV32/64C Standard Extension (Quadrant 2) *** slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp @@ -130,3 +149,14 @@ fld 001 . ..... ..... 10 @c_ldsp } fsd 101 ...... ..... 10 @c_sdsp sw 110 . ..... ..... 10 @c_swsp + +# *** RV32C and RV64C specific Standard Extension (Quadrant 2) *** +{ + c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=3D0 + ld 011 . ..... ..... 10 @c_ldsp + flw 011 . ..... ..... 10 @c_lwsp +} +{ + sd 111 . ..... ..... 10 @c_sdsp + fsw 111 . ..... ..... 10 @c_swsp +} diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 1340676209..bd93f634cf 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -24,6 +24,12 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *= a) return true; } =20 +static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a) +{ + REQUIRE_64BIT(ctx); + return trans_illegal(ctx, a); +} + static bool trans_lui(DisasContext *ctx, arg_lui *a) { if (a->rd !=3D 0) { diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 24bf049164..af6c3416b7 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -1,18 +1,13 @@ # FIXME extra_args should accept files() dir =3D meson.current_source_dir() -gen32 =3D [ - decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode= ', '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), - decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), -] =20 -gen64 =3D [ - decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode= ', '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), +gen =3D [ + decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), ] =20 riscv_ss =3D ss.source_set() -riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32) -riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64) +riscv_ss.add(gen) riscv_ss.add(files( 'cpu.c', 'cpu_helper.c', --=20 2.31.1 From nobody Thu May 2 18:16:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=752564754=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47 Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistai= r.francis@wdc.com --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index fecf0f15d5..8901ba1e1b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2= _s hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma =20 -# *** RV32H Base Instruction Set *** +# *** RV64H Base Instruction Set *** hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s --=20 2.31.1