On 28/05/2024 22:29, Mark Cave-Ayland wrote:
> On 26/05/2024 20:42, Richard Henderson wrote:
>
>> Now tested with RISU, using a Solaris M8 host as reference.
>> This exposed a few bugs in the existing VIS1 support as well,
>> so fix those before anything else. It also exposed a few bugs
>> in the implementation of VIS3, so fixes squashed there as well.
>>
>>
>> r~
>>
>>
>> Richard Henderson (37):
>> target/sparc: Fix ARRAY8
>> target/sparc: Rewrite gen_edge
>> target/sparc: Fix do_dc
>> target/sparc: Fix helper_fmul8ulx16
>> target/sparc: Perform DFPREG/QFPREG in decodetree
>> target/sparc: Remove gen_dest_fpr_D
>> target/sparc: Remove cpu_fpr[]
>> target/sparc: Use gvec for VIS1 parallel add/sub
>> target/sparc: Implement FMAf extension
>> target/sparc: Add feature bits for VIS 3
>> target/sparc: Implement ADDXC, ADDXCcc
>> target/sparc: Implement CMASK instructions
>> target/sparc: Implement FCHKSM16
>> target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL
>> target/sparc: Implement FLCMP
>> target/sparc: Implement FMEAN16
>> target/sparc: Implement FPADD64, FPSUB64
>> target/sparc: Implement FPADDS, FPSUBS
>> target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8
>> target/sparc: Implement FSLL, FSRL, FSRA, FSLAS
>> target/sparc: Implement LDXEFSR
>> target/sparc: Implement LZCNT
>> target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd
>> target/sparc: Implement PDISTN
>> target/sparc: Implement UMULXHI
>> target/sparc: Implement XMULX
>> target/sparc: Enable VIS3 feature bit
>> target/sparc: Implement IMA extension
>> target/sparc: Add feature bit for VIS4
>> target/sparc: Implement FALIGNDATAi
>> target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS
>> target/sparc: Implement VIS4 comparisons
>> target/sparc: Implement FPMIN, FPMAX
>> target/sparc: Implement SUBXC, SUBXCcc
>> target/sparc: Implement MWAIT
>> target/sparc: Implement monitor ASIs
>> target/sparc: Enable VIS4 feature bit
>>
>> target/sparc/asi.h | 4 +
>> target/sparc/helper.h | 27 +-
>> target/sparc/cpu-feature.h.inc | 4 +
>> target/sparc/insns.decode | 338 ++++++++----
>> linux-user/elfload.c | 3 +
>> target/sparc/cpu.c | 12 +
>> target/sparc/fop_helper.c | 136 +++++
>> target/sparc/ldst_helper.c | 4 +
>> target/sparc/translate.c | 938 ++++++++++++++++++++++++++-------
>> target/sparc/vis_helper.c | 392 +++++++++++---
>> fpu/softfloat-specialize.c.inc | 31 ++
>> 11 files changed, 1558 insertions(+), 331 deletions(-)
>
> Thanks - I'll give this series a quick run over my test images over the next few days
> just to make sure there are no regressions (unlikely as I don't have much in the way
> of current VIS test cases) and report back.
This series passes all my sun4u boot tests so:
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
I don't have any other pending patches so feel free to take this via your TCG branch
if you would like it merged in the near future.
ATB,
Mark.